[llvm-branch-commits] [GlobalISel] Combiner: Observer-based DCE and retrying of combines (PR #102163)

@@ -45,61 +45,190 @@ cl::OptionCategory GICombinerOptionCategory( ); } // end namespace llvm -/// This class acts as the glue the joins the CombinerHelper to the overall +/// This class acts as the glue that joins the CombinerHelper to the overall /// Combine algorithm. The C

[llvm-branch-commits] [GlobalISel] Combiner: Observer-based DCE and retrying of combines (PR #102163)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/102163 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [GlobalISel] Combiner: Observer-based DCE and retrying of combines (PR #102163)

@@ -45,61 +45,190 @@ cl::OptionCategory GICombinerOptionCategory( ); } // end namespace llvm -/// This class acts as the glue the joins the CombinerHelper to the overall +/// This class acts as the glue that joins the CombinerHelper to the overall /// Combine algorithm. The C

[llvm-branch-commits] [llvm] AArch64: Use consistent atomicrmw expansion for FP operations (PR #103702)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/103702 >From b8fbc44dbbfe3f0bcfc6c72c4beaf279bc7a99de Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 14 Aug 2024 00:43:03 +0400 Subject: [PATCH 1/2] AArch64: Use consistent atomicrmw expansion for FP operatio

[llvm-branch-commits] [llvm] AArch64: Use consistent atomicrmw expansion for FP operations (PR #103702)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/103702 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f16 builtins (PR #96873)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96873 >From 0a01c3aa950322fae803d31812affbd358d368b9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:12:59 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f1

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96874 >From 4d880b9b40b85d0ed2d19da2d89880cefd4ae661 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:15:26 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtins (PR #96875)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96875 >From 75cbc81c7f6c7b63a9d6cc33ce194e77b4c2b119 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:34:43 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtin

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64 builtins (PR #96876)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96876 >From 2c9916f78076a6885ba7b9c847433fec8e413103 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 23:18:32 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics (PR #97050)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/97050 >From f0843b296d9858d8e6b6a2b4e1cea0702c200b6b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Jun 2024 16:32:48 +0200 Subject: [PATCH] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics These a

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96874 >From 681262015dbc0b6dcfdeb781dcc8db8fb9053649 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:15:26 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtins (PR #96875)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96875 >From c45510746e382ec4c7e2111037b1ae5e715ddf25 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:34:43 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtin

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64 builtins (PR #96876)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96876 >From c0e5b88ab0d952dea59ca313a197cf1b495ffd62 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 23:18:32 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics (PR #97050)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/97050 >From 0f8ef026d8b6e7e26093294eee95a86b6c7cad50 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Jun 2024 16:32:48 +0200 Subject: [PATCH] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics These a

[llvm-branch-commits] [llvm] [WIP] AMDGPU: Handle v_add* in eliminateFrameIndex (PR #102346)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/102346 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [WIP] AMDGPU: Handle v_add* in eliminateFrameIndex (PR #102346)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102346 error: too big or took too long to generate ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96874 >From e10cf564b3f902655d465a2a62f1d25d3ac82018 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:15:26 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtins (PR #96875)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96875 >From f162998c081c4e6a6162fede2878d7a85add640e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:34:43 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtin

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64 builtins (PR #96876)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96876 >From 7e0bed6a0511eeaaae318b9fe80bdd4ce06d527a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 23:18:32 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics (PR #97050)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/97050 >From 04528075a6cd460a4db7f1e6412ce54cca123468 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Jun 2024 16:32:48 +0200 Subject: [PATCH] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics These a

[llvm-branch-commits] [llvm] AArch64: Use consistent atomicrmw expansion for FP operations (PR #103702)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/103702 >From 3c1ef5cfbcc6c14215681c1d6aff3c8e2486bdc1 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 14 Aug 2024 00:43:03 +0400 Subject: [PATCH 1/3] AArch64: Use consistent atomicrmw expansion for FP operatio

[llvm-branch-commits] [llvm] [AMDGPU][R600] Move createMachineFunctionInfo into R600 TM. (PR #104038)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/104038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][R600] Move createMachineFunctionInfo into R600 TM. (PR #104038)

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/104038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][R600] Move R600CodeGenPassBuilder into R600TargetMachine(NFC). (PR #103721)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/103721 >From a10910597e6ee30e87dd09a4f77fcfa1729873f0 Mon Sep 17 00:00:00 2001 From: Christudasan Devadasan Date: Wed, 14 Aug 2024 14:18:59 +0530 Subject: [PATCH 1/3] [AMDGPU][R600] Move R600TargetMachine into R600Code

[llvm-branch-commits] [llvm] [AMDGPU][R600] Move R600CodeGenPassBuilder into R600TargetMachine(NFC). (PR #103721)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/103721 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare (PR #102867)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102867 >From 12b9f7af4cb81d0dfc6c59d9472acb0d73c8d209 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 12 Aug 2024 13:09:55 +0400 Subject: [PATCH] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare AMDGPUAnnota

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare (PR #102867)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102867 >From 12b9f7af4cb81d0dfc6c59d9472acb0d73c8d209 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 12 Aug 2024 13:09:55 +0400 Subject: [PATCH] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare AMDGPUAnnota

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Start filling out addIRPasses (PR #102884)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102884 >From cb9f6024536905aa2819c168519eef8aca736b13 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 12 Aug 2024 15:26:25 +0400 Subject: [PATCH] AMDGPU/NewPM: Start filling out addIRPasses This is not complet

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare (PR #102867)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/102867 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Declare pass control flags in header (PR #102865)

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/102865 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Declare pass control flags in header (PR #102865)

arsenm wrote: Moved AMDGPUCodeGenPassBuilder into AMDGPUTargetMachine instead https://github.com/llvm/llvm-project/pull/102865 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare (PR #102867)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102867 >From fe6695d0b4b48d55d76e76ed31a058ca7880fbdd Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 12 Aug 2024 13:09:55 +0400 Subject: [PATCH] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare AMDGPUAnnota

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Start filling out addIRPasses (PR #102884)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102884 >From 284f29cba21e1e2770f479c90793efd071159d8b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 12 Aug 2024 15:26:25 +0400 Subject: [PATCH] AMDGPU/NewPM: Start filling out addIRPasses This is not complet

[llvm-branch-commits] [llvm] release/19.x: [GlobalISel] Bail out early for big-endian (#103310) (PR #104823)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/104823 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [GlobalISel] Bail out early for big-endian (#103310) (PR #104823)

@@ -539,3 +546,5 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo & return true; } + +bool ARMCallLowering::enableBigEndian() const { return EnableGISelBigEndian; } arsenm wrote: Missing end of line but I guess that's an up

[llvm-branch-commits] [llvm] AArch64: Use consistent atomicrmw expansion for FP operations (PR #103702)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/103702 >From 25c93fb74e90189dc132793b1d08e081c78028d7 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 14 Aug 2024 00:43:03 +0400 Subject: [PATCH 1/3] AArch64: Use consistent atomicrmw expansion for FP operatio

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Start filling out addIRPasses (PR #102884)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102884 >From 62393209c160ec9dad171cc133ad5da9d2654ca2 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 12 Aug 2024 15:26:25 +0400 Subject: [PATCH] AMDGPU/NewPM: Start filling out addIRPasses This is not complet

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics (PR #97050)

arsenm wrote: ping https://github.com/llvm/llvm-project/pull/97050 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtins (PR #96875)

arsenm wrote: ### Merge activity * **Aug 20, 2:53 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/96875). https://github.com/llvm/llvm-project/pull/96875 __

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

arsenm wrote: ### Merge activity * **Aug 20, 2:53 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/96874). https://github.com/llvm/llvm-project/pull/96874 __

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64 builtins (PR #96876)

arsenm wrote: ### Merge activity * **Aug 20, 2:53 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/96876). https://github.com/llvm/llvm-project/pull/96876 __

[llvm-branch-commits] [llvm] AMDGPU/NewPM: Start filling out addIRPasses (PR #102884)

arsenm wrote: ### Merge activity * **Aug 20, 3:25 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/102884). https://github.com/llvm/llvm-project/pull/102884

[llvm-branch-commits] [llvm] release/19.x: [AMDGPU] Disable inline constants for pseudo scalar transcendentals (#104395) (PR #105472)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/105472 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [FixIrreducible] Use CycleInfo instead of a custom SCC traversal (PR #101386)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/101386 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79718 (PR #81241)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/81241 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISel] Don't pointlessly lower G_TRUNC (#81479) (PR #81581)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/81581 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [TableGen] Fix wrong codegen of BothFusionPredicateWithMCInstPredicate (#83990) (PR #83999)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/83999 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: Convert many LivePhysRegs uses to LiveRegUnits (PR #84118)

arsenm wrote: I don't think this should be rushed to the release branch. In particular patches should not deviate from the original main version in exceptional circumstances, but mostly this isn't fixing any known correctness issue https://github.com/llvm/llvm-project/pull/84118 _

[llvm-branch-commits] [IR] Introduce `llvm.experimental.hot()` (PR #84850)

@@ -7276,6 +7276,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, setValue(&I, getValue(I.getArgOperand(0))); return; + case Intrinsic::experimental_hot: +// Default lowering to false. It's intended to be lowered as soon as profile +// i

[llvm-branch-commits] [IR] Introduce `llvm.experimental.hot()` (PR #84850)

@@ -7276,6 +7276,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, setValue(&I, getValue(I.getArgOperand(0))); return; + case Intrinsic::experimental_hot: +// Default lowering to false. It's intended to be lowered as soon as profile +// i

[llvm-branch-commits] [MacroFusion] Add SingleFusion that accepts a single instruction pair (PR #85750)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/85750 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CostModel] No cost for llvm.allow.{runtime, ubsan}.check() (PR #86064)

@@ -714,6 +714,8 @@ class TargetTransformInfoImplBase { switch (ICA.getID()) { default: break; +case Intrinsic::allow_runtime_check: arsenm wrote: This whole function seems to be reinventing isAssumeLikeIntrinsic https://github.com/llvm/llvm

[llvm-branch-commits] [CodeGen] Add default lowering for llvm.allow.{runtime, ubsan}.check() (PR #86049)

@@ -0,0 +1,30 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=aarch64 | FileCheck %s arsenm wrote: Should use explicit -global-isel=0 for the dag test https://github.com/llvm/llv

[llvm-branch-commits] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

@@ -2220,6 +2220,14 @@ CGObjCCommonMac::EmitMessageSend(CodeGen::CodeGenFunction &CGF, RValue rvalue = CGF.EmitCall(MSI.CallInfo, Callee, Return, ActualArgs, &CallSite); + // Set type identifier metadata of indirect calls for call graph secti

[llvm-branch-commits] [llvm] release/18.x [SelectionDAG] Prevent combination on inconsistent type in 'carryDiamond' (PR #86697)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/86697 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [Sparc] Fix instr desc of special register stores (PR #88971)

https://github.com/arsenm approved this pull request. Knowing nothing about SPARC, I don't see how having the address to a store in the output made sense https://github.com/llvm/llvm-project/pull/88971 ___ llvm-branch-commits mailing list llvm-branch

[llvm-branch-commits] [TableGen][InstrInfoEmitter] Count sub-operands on def operands (PR #88972)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/88972 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [TableGen][InstrInfoEmitter] Count sub-operands on def operands (PR #88972)

@@ -1181,9 +1181,15 @@ void InstrInfoEmitter::emitRecord( // Each logical operand can be multiple MI operands. MinOperands = Inst.Operands.back().MIOperandNo + Inst.Operands.back().MINumOperands; + // Even the logical output operand may be multiple MI operands.

[llvm-branch-commits] [llvm] release/18.x: [GlobalISel] Fix fewerElementsVectorPhi to insert after G_PHIs (#87927) (PR #89240)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/89240 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [GlobalISel] Fix fewerElementsVectorPhi to insert after G_PHIs (#87927) (PR #89240)

https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89240 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] Fix miscompile bug in combineShiftOfShiftedLogic (#89616) (PR #89766)

=?utf-8?q?Björn?= Pettersson Message-ID: In-Reply-To: https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89766 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/

[llvm-branch-commits] [llvm] release/18.x: [AArch64] Remove invalid uabdl patterns. (#89272) (PR #89380)

https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89380 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [TableGen] Fix ReplaceRegAction RTTI Kind (PR #89790)

https://github.com/arsenm milestoned https://github.com/llvm/llvm-project/pull/89790 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

@@ -5687,6 +5688,39 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, AllocAlignAttrEmitter AllocAlignAttrEmitter(*this, TargetDecl, CallArgs); Attrs = AllocAlignAttrEmitter.TryEmitAsCallSiteAttribute(Attrs); + if (CGM.getCodeGenOpts().CallGraphSection)

[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/90204 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen] Add default lowering for llvm.allow.{runtime, ubsan}.check() (PR #86049)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/86049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT (PR #90827)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/90827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

@@ -187,8 +187,12 @@ VmemType getVmemType(const MachineInstr &Inst) { const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode()); const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo = AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); - return BaseInfo->BVH ? VMEM_BVH

[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91126)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91126 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Mark frame index as "aliased" at argument copy elison (PR #91035)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91035 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

@@ -5693,6 +5699,36 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, AllocAlignAttrEmitter AllocAlignAttrEmitter(*this, TargetDecl, CallArgs); Attrs = AllocAlignAttrEmitter.TryEmitAsCallSiteAttribute(Attrs); + if (CGM.getCodeGenOpts().CallGraphSection)

[llvm-branch-commits] [clang] [clang][CallGraphSection] Add type id metadata to indirect call and targets (PR #87573)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/87573 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} + +/// Extracts the numeric type id from the CallBase's type operand bundle, +/// and sets TypeId. This is used as

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} arsenm wrote: ```suggestion CallSiteInfo() = default; ``` https://github.com/llvm/llvm-project/pull/

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} + +/// Extracts the numeric type id from the CallBase's type operand bundle, +/// and sets TypeId. This is used as

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -488,6 +490,35 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Callee type id. ConstantInt *TypeId = nullptr; + +CallSiteInfo() {} + +/// Extracts the numeric type id from the CallBase's type operand bundle, +/// and sets TypeId. This is used as

[llvm-branch-commits] [CallSiteInfo][CallGraphSection] Extract and propagate indirect call type ids (PR #87575)

@@ -7922,6 +7923,10 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, *DAG.getContext()); RetCCInfo.AnalyzeCallResult(Ins, RetCC); + // Set type id for call site info. + if (MF.getTarget().Options.EmitCallGraphSection && CB && CB->isIndirectCa

[llvm-branch-commits] [llvm] release/18.x: [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972) (PR #91580)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91580 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT - manual merge (PR #91672)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/91672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Fill 17.x/ReleaseNotes with my works (PR #73461)

arsenm wrote: > Oh, this is 1st time pull request to me. For release branches, I think you are still supposed to use https://github.com/llvm/llvm-project-release-prs https://github.com/llvm/llvm-project/pull/73461 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [llvm] 5e94080 - AMDGPU: Regenerate test checks

Author: Matt Arsenault Date: 2023-12-02T21:42:05+07:00 New Revision: 5e94080fc7cd920107d3d2291c872b510b6ab017 URL: https://github.com/llvm/llvm-project/commit/5e94080fc7cd920107d3d2291c872b510b6ab017 DIFF: https://github.com/llvm/llvm-project/commit/5e94080fc7cd920107d3d2291c872b510b6ab017.diff

[llvm-branch-commits] [llvm] 3c86bc0 - AMDGPU: Add more tests for rootn libcall handling

Author: Matt Arsenault Date: 2023-12-02T21:53:31+07:00 New Revision: 3c86bc0ae9b3df289ca005d3c451512f01be6d61 URL: https://github.com/llvm/llvm-project/commit/3c86bc0ae9b3df289ca005d3c451512f01be6d61 DIFF: https://github.com/llvm/llvm-project/commit/3c86bc0ae9b3df289ca005d3c451512f01be6d61.diff

[llvm-branch-commits] [clang] [mlir] [llvm] PR for llvm/llvm-project#79293 (PR #79461)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79461 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79420 (PR #79595)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79595 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79451 (PR #79457)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79457 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Backport 45d2d7757feb386186f69af6ef57bde7b5adc2db to release/18.x (PR #79839)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/79839 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Backport 45d2d7757feb386186f69af6ef57bde7b5adc2db to release/18.x (PR #79839)

@@ -6883,6 +6883,23 @@ bool AMDGPULegalizerInfo::legalizeStackSave(MachineInstr &MI, return true; } +bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI, + MachineIRBuilder &B) const { + // With architected SGPRs, waveIDinGroup

[llvm-branch-commits] [llvm] Backport 45d2d7757feb386186f69af6ef57bde7b5adc2db to release/18.x (PR #79839)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/79839 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] GFX12 VMEM instructions can write VGPR results out of order (PR #105549)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/105549 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Check if is_fpclass is custom, instead of isLegalOrCustom (PR #105577)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/105577 For some reason, isOperationLegalOrCustom is not the same as isOperationLegal || isOperationCustom. Unfortunately, it checks if the type is legal which makes it uesless for custom lowering on non-legal types (whic

[llvm-branch-commits] [llvm] DAG: Check if is_fpclass is custom, instead of isLegalOrCustom (PR #105577)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/105577?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] DAG: Check if is_fpclass is custom, instead of isLegalOrCustom (PR #105577)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/105577 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Handle lowering unordered compare with inf (PR #100378)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/100378 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Lower single infinity is.fpclass tests to fcmp (PR #100380)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100380 >From eaf47a26b0c0d79b29ea6d8c9dd64052f286b52b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 1 Feb 2023 09:52:34 -0400 Subject: [PATCH] DAG: Lower single infinity is.fpclass tests to fcmp InstCombine

[llvm-branch-commits] [llvm] DAG: Lower fcNormal is.fpclass to compare with inf (PR #100389)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100389 >From 1e2a2b6e533ab591481fd755ab2b1f0c922b84bd Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 1 Feb 2023 09:06:59 -0400 Subject: [PATCH] DAG: Lower fcNormal is.fpclass to compare with inf Looks worse f

[llvm-branch-commits] [llvm] DAG: Handle lowering unordered compare with inf (PR #100378)

@@ -117,10 +117,12 @@ define i1 @isinf_float(float %x) nounwind { define i1 @isinf_ppc_fp128(ppc_fp128 %x) nounwind { ; CHECK-LABEL: isinf_ppc_fp128: ; CHECK: # %bb.0: -; CHECK-NEXT:xststdcdp 0, 1, 48 -; CHECK-NEXT:li 3, 0 -; CHECK-NEXT:li 4, 1 -; CHECK-NEXT:

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global fmin/fmax intrinsics (PR #105642)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/105642 These have been replaced with atomicrmw >From be7d2aef3110181609d70b7aec9a15409f18026d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 28 Jun 2024 20:38:01 +0200 Subject: [PATCH] AMDGPU: Remove flat/glo

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global fmin/fmax intrinsics (PR #105642)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/105642 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global fmin/fmax intrinsics (PR #105642)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/105642?utm_source=stack-comment-downstack-mergeability-warning";

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