https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/102130
isExtractHiElt should return new source register instead of returning
instruction that defines it. Src = MI.getOperand(0).getReg() is not
correct when MI(for example G_UNMERGE_VALUES) defines multiple reg
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102130?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic ready_for_review
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Author: Petar Avramovic
Date: 2021-01-20T10:37:09+01:00
New Revision: 4ab704d62820396af5bd4a4322a5cbc2700a7ec3
URL:
https://github.com/llvm/llvm-project/commit/4ab704d62820396af5bd4a4322a5cbc2700a7ec3
DIFF:
https://github.com/llvm/llvm-project/commit/4ab704d62820396af5bd4a4322a5cbc2700a7ec3.dif
Author: Petar Avramovic
Date: 2020-12-07T14:00:08+01:00
New Revision: 3a042dcd2e1ab53244d504cd87a81b577a62a6ea
URL:
https://github.com/llvm/llvm-project/commit/3a042dcd2e1ab53244d504cd87a81b577a62a6ea
DIFF:
https://github.com/llvm/llvm-project/commit/3a042dcd2e1ab53244d504cd87a81b577a62a6ea.dif
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From f354d303a9addd878dbca7ba88ae71a196173518 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 17 Oct 2024 16:39:55 +0200
Subject: [PATCH] AMDGPU/GlobalISel: RBLegalize rules for load
Add IDs
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 317c41b80b26e55ee35c5859700d91d36e58cd2a Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 17 Oct 2024 15:43:06 +0200
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/112882
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petar-avramovic wrote:
Ignore this, see https://github.com/llvm/llvm-project/pull/112882
https://github.com/llvm/llvm-project/pull/112865
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@@ -0,0 +1,334 @@
+//===-- AMDGPURBLegalizeRules.cpp
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,258 @@
+//===- AMDGPURBLegalizeRules -*- C++
-*-==//
petar-avramovic wrote:
Don't think sharing is good option for this patch. RBLegalizeRules are much
more flexible and I would assume faster because of "FastPredic
@@ -0,0 +1,118 @@
+//===- AMDGPURBLegalizeHelper *- C++
-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/112882
Add IDs for bit width that cover multiple LLTs: B32 B64 etc.
"Predicate" wrapper class for bool predicate functions used to
write pretty rules. Predicates can be combined using &&, || and !.
Lowering for
https://github.com/petar-avramovic edited
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petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/112882?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 0be714e28b9a7d2c0ee070827efc1587524bbc28 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Tue, 22 Oct 2024 17:46:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 1b1d2f95a8e6fb552d1853b93e15a12775a7b01b Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Tue, 22 Oct 2024 18:06:55 +0200
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 74a1970b576cb6943271614cfe616459cd73956c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From a8d15f3f4854a364fc0b905544840112283b41a3 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
@@ -66,9 +81,232 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
@@ -69,11 +82,297 @@ FunctionPass *llvm::createAMDGPURegBankLegalizePass() {
return new AMDGPURegBankLegalize();
}
-using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ stat
@@ -697,6 +697,15 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
}
+MachineInstrBuilder
+MachineIRBuilder::buildUnmerge(MachineRegisterInfo::VRegAttrs Attrs,
+ const
@@ -217,6 +217,74 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr
&I) const {
return true;
}
+bool AMDGPUInstructionSelector::selectCOPY_SCC_VCC(MachineInstr &I) const {
petar-avramovic wrote:
This allows for more registers to be allocated to sg
petar-avramovic wrote:
Added LLVM_DEBUG around dumps, RB->RegBank rename for methods and class names
https://github.com/llvm/llvm-project/pull/112864
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petar-avramovic wrote:
Ping. There were changes because of improvements to builder accepting
regbank+LLT, think I addressed most of the comments.
https://github.com/llvm/llvm-project/pull/112864
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https://github.com/llvm/llvm-project/pull/112866
>From 98a00e5a2ed28da3a4608d9c209a04f0cff6fe12 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:41:59 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 4675f79f28222cef60d1607acb1b682ca3363eb6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
@@ -0,0 +1,334 @@
+//===-- AMDGPURBLegalizeRules.cpp
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -107,3 +107,183 @@ void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register
Reg) {
S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
}
}
+
+MachineInstrBuilder AMDGPU::buildReadAnyLaneB32(MachineIRBuilder &B,
+const
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -0,0 +1,334 @@
+//===-- AMDGPURBLegalizeRules.cpp
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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@@ -54,9 +54,28 @@ const MachineBasicBlock
*MachineSSAContext::getDefBlock(Register value) const {
return F->getRegInfo().getVRegDef(value)->getParent();
}
+static bool isUndef(const MachineInstr &MI) {
+ return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+ M
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
https://github.com/petar-avramovic edited
https://github.com/llvm/llvm-project/pull/112863
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@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
petar-avramovic wrote:
Rebase for new-reg-bank-select taking over AMDGPURegBankSelect
TODO: helper changes after DstOp improvements as it accepts bank+LLT
https://github.com/llvm/llvm-project/pull/112864
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@@ -39,6 +39,8 @@ FunctionPass *createSIFoldOperandsLegacyPass();
FunctionPass *createSIPeepholeSDWALegacyPass();
FunctionPass *createSILowerI1CopiesLegacyPass();
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
+FunctionPass *createAMDGPURBSelectPass();
--
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 610eeeacfb418948bf36a8a0b4eee40c4ada24aa Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 28 Oct 2024 15:15:10 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic edited
https://github.com/llvm/llvm-project/pull/112862
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>From 619288bc69a9d1290a2a5c521582b0204e0608b6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 28 Oct 2024 15:09:50 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic edited
https://github.com/llvm/llvm-project/pull/112866
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https://github.com/llvm/llvm-project/pull/112882
>From 1f2cecde58eb1b2443b8b93d27bde2b1de0e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 28 Oct 2024 15:09:50 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 000d17beab5b20702c92c07f9a2241ac50a63629 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 28 Oct 2024 15:15:10 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic edited
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@@ -69,6 +81,241 @@ FunctionPass *llvm::createAMDGPURBLegalizePass() {
using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDens
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From b2fd498febbdd9ed4e65cb18a541aaeee85550b1 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 28 Oct 2024 15:09:50 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From f5c645d18bc3b17f92ff2ef65e1c676f0fc0dfa0 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 28 Oct 2024 15:15:10 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From a269e8da1b872b3f2390037a594757940cf8369b Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
@@ -66,9 +73,215 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From e6285ef8415e03337a080fa13456a2495023a8e6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From eb6a8fc2973ad31f607af56c61a4c6ba6f30d982 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 6ec049db2a5572c4cb0514b9ca44c7ff215b461f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
@@ -66,9 +73,215 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
@@ -66,9 +73,215 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
@@ -69,3 +72,37 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI,
Register Reg,
return std::pair(Reg, 0);
}
+
+IntrinsicLaneMaskAnalyzer::IntrinsicLaneMaskAnalyzer(MachineFunction &MF)
+: MRI(MF.getRegInfo()) {
+ initLaneMaskIntrinsics(MF);
+}
+
+bool Intr
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 3854308d10edc1329086faf26542ca469b26c589 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From c59ad6e821a49e48df70edff1fdb044eb0083b1c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
@@ -66,9 +81,208 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/110256
>From 2ea25b291ffdae0d3b9b6821199080f133de34c7 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 27 Sep 2024 13:59:31 +0200
Subject: [PATCH] AMDGPU: Fix inst-selection of large scratch offsets wi
@@ -1911,7 +1911,7 @@ bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode
*Parent, SDValue Addr,
0);
}
- Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i16);
+ Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i32);
petar
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110256?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/110256
Use i32 for offset instead of i16, this way it does not get interpreted
as negative 16 bit offset.
>From dcec93029eb0126761ed7521511294b9237591db Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/110256
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>From befab474546b9f44fa2b5d7961df8c0490aed692 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 75694f85585d7b07c17d68f32632310ba1d939a9 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
@@ -290,7 +504,86 @@ RegBankLegalizeRules::RegBankLegalizeRules(const
GCNSubtarget &_ST,
.Any({{UniS64, S32}, {{Sgpr64}, {Sgpr32}, Ext32To64}})
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}, Ext32To64}});
- addRulesForGOpcs({G_LOAD}).Any({{DivS32, DivP1}, {{Vgpr32}, {
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From b7366209b93a07f286842f31bb625ca321b47df4 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 686c0699e6653c1a11e7e911ccf4de107d390066 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
petar-avramovic wrote:
ping
https://github.com/llvm/llvm-project/pull/112863
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petar-avramovic wrote:
ping
https://github.com/llvm/llvm-project/pull/112882
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 97ce5f3295ed0f795656aed9180901c2299159f8 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 59e70ef3cb6b1e9183691782b5675a376add3fbd Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
petar-avramovic wrote:
ping
https://github.com/llvm/llvm-project/pull/112864
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 3f80c887a75708c9cf88283fde991be7221c73d9 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 18162175daa7f1627f036ecda9cbfb589b58d04a Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
@@ -40,6 +40,10 @@ template class GenericUniformityInfo {
using CycleInfoT = GenericCycleInfo;
using CycleT = typename CycleInfoT::CycleT;
+ // Use outside cycle with divergent exit
+ using UOCWDE =
petar-avramovic wrote:
My guess is that GenericUnifor
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From a5c340d0301c3b36fadd352d7ed1c332789cb73b Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 31 Jan 2025 13:04:17 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
petar-avramovic wrote:
Insert point of merging phi is changed to after Inst, not in the exiting block.
https://github.com/llvm/llvm-project/pull/124299
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@@ -395,6 +399,14 @@ template class
GenericUniformityAnalysisImpl {
}
void print(raw_ostream &out) const;
+ SmallVector UsesOutsideCycleWithDivergentExit;
+ void recordUseOutsideCycleWithDivergentExit(const InstructionT *,
petar-avramovic wrote:
I was
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 3fa31aeeb48e3b4a1dcac77d67dc6a1d205c8dce Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From ada22e8d25b8ca05c048b83307edb60fbdf6a774 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 991bdf1a6de2e91732a3b9c443786243aaa58e91 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
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