Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.td updated: 1.14 -> 1.15
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+3 -3)
AlphaRegisterInfo.td |
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.65 -> 1.66
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+13 -7)
MRegisterInfo.h | 20
Changes in directory llvm/lib/Target/Skeleton:
SkeletonRegisterInfo.td updated: 1.5 -> 1.6
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+2 -2)
SkeletonRegisterInfo.t
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.46 -> 1.47
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+1 -1)
ScheduleDAG.cpp |2
Changes in directory llvm/utils/TableGen:
CodeGenRegisters.h updated: 1.8 -> 1.9
CodeGenTarget.cpp updated: 1.45 -> 1.46
DAGISelEmitter.cpp updated: 1.80 -> 1.81
RegisterInfoEmitter.cpp updated: 1.37 -> 1.38
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vec
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.25 -> 1.26
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+8 -7)
PPCRegisterInfo.td | 15
Changes in directory llvm/lib/Target/SparcV9:
SparcV9RegisterInfo.cpp updated: 1.9 -> 1.10
SparcV9RegisterInfo.td updated: 1.5 -> 1.6
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.td updated: 1.22 -> 1.23
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+8 -7)
X86RegisterInfo.td | 15
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.td updated: 1.10 -> 1.11
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+3 -3)
IA64RegisterInfo.td |6 +
Changes in directory llvm/lib/Target/SparcV8:
SparcV8RegisterInfo.td updated: 1.22 -> 1.23
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+3 -3)
SparcV8RegisterInfo.td
Changes in directory llvm/lib/Target:
Target.td updated: 1.62 -> 1.63
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+6 -3)
Target.td |9 ++---
1 files changed
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.24 -> 1.25
---
Log message:
Cosmetic change, better reflects actual values
---
Diffs of the changes: (+5 -6)
PPCRegisterInfo.td | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
Index: llvm/lib
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.133 -> 1.134
---
Log message:
Fix a regression caused by a patch earlier today
---
Diffs of the changes: (+2 -1)
PPCISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.10 -> 1.11
---
Log message:
Flags where I think I need them, quick, before the nightly tester starts
---
Diffs of the changes: (+42 -23)
AlphaISelDAGToDAG.cpp | 65
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.5 -> 1.6
X86InstrInfo.td updated: 1.144 -> 1.145
---
Log message:
Proper support for shifts with register shift value.
---
Diffs of the changes: (+24 -44)
X86ISelDAGToDAG.cpp | 41 ++-
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.132 -> 1.133
---
Log message:
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
---
Diffs of the changes: (+2 -8)
PPCISelDAGToDAG.cpp | 10 ++
1 files changed, 2 insertions(+), 8 deletion
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.79 -> 1.80
DAGISelEmitter.h updated: 1.37 -> 1.38
---
Log message:
Teach tblgen to accept register source operands in patterns, e.g.
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $d
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.74 -> 1.75
---
Log message:
Teach tblgen to accept register source operands in patterns, e.g.
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(se
Changes in directory llvm/utils/TableGen:
CodeGenInstruction.h updated: 1.14 -> 1.15
CodeGenTarget.cpp updated: 1.44 -> 1.45
---
Log message:
Nuke CodeGenInstruction's ValueType member, it is no longer used.
---
Diffs of the changes: (+7 -18)
CodeGenInstruction.h | 12 +++-
CodeG
Changes in directory llvm/utils/TableGen:
CodeGenTarget.h updated: 1.19 -> 1.20
DAGISelEmitter.cpp updated: 1.78 -> 1.79
DAGISelEmitter.h updated: 1.36 -> 1.37
---
Log message:
Stop checking the ValueType of the CodeGenInstruction. Instead, use the
ValueType from the RegisterClass or Operands.
Changes in directory llvm/utils/TableGen:
CodeGenInstruction.h updated: 1.13 -> 1.14
---
Log message:
fit into 80 columns
---
Diffs of the changes: (+2 -2)
CodeGenInstruction.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/CodeGenInstruction.h
d
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.77 -> 1.78
---
Log message:
Make the code generated by tblgen return the result of SelectNodeTo, to
permit future changes.
---
Diffs of the changes: (+1 -2)
DAGISelEmitter.cpp |3 +--
1 files changed, 1 insertion(+
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.9 -> 1.10
---
Log message:
SelectNodeTo now returns its result, we must pay attention to it.
---
Diffs of the changes: (+29 -40)
AlphaISelDAGToDAG.cpp | 69 +-
1
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.12 -> 1.13
---
Log message:
Pay attn to the node returned by SelectNodeTo
---
Diffs of the changes: (+28 -37)
IA64ISelDAGToDAG.cpp | 65 +--
1 files changed, 28 inse
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.4 -> 1.5
---
Log message:
SelectNodeTo now returns its result, we must pay attention to it.
---
Diffs of the changes: (+18 -20)
X86ISelDAGToDAG.cpp | 38 ++
1 files changed, 18 in
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.131 -> 1.132
---
Log message:
SelectNodeTo now returns N. Use it instead of return N directly.
---
Diffs of the changes: (+81 -108)
PPCISelDAGToDAG.cpp | 189 ++--
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.219 -> 1.220
---
Log message:
Make SelectNodeTo return N
---
Diffs of the changes: (+49 -35)
SelectionDAG.cpp | 84 ---
1 files changed, 49 insertions(+), 3
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.73 -> 1.74
---
Log message:
Make SelectNodeTo return N
---
Diffs of the changes: (+30 -28)
SelectionDAG.h | 58 +
1 files changed, 30 insertions(+), 28 deleti
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.47 -> 1.48
---
Log message:
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
---
Diffs of the changes: (+6 -2)
PPCISelLowering.cpp |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Inde
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
2005-11-30-vastart-crash.ll added (r1.1)
---
Log message:
Test that crashes the ppc backend.
---
Diffs of the changes: (+17 -0)
2005-11-30-vastart-crash.ll | 17 +
1 files changed, 17 insertions(+)
Index: llvm/t
Changes in directory llvm/lib/Transforms/Scalar:
DeadStoreElimination.cpp updated: 1.12 -> 1.13
---
Log message:
Fix a bug where we didn't realize that vaarg reads memory. This fixes
Transforms/DeadStoreElimination/2005-11-30-vaarg.ll
---
Diffs of the changes: (+7 -0)
DeadStoreElimination
Changes in directory llvm/test/Regression/Transforms/DeadStoreElimination:
2005-11-30-vaarg.ll added (r1.1)
---
Log message:
new testcase dse is miscompiling
---
Diffs of the changes: (+9 -0)
2005-11-30-vaarg.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/Regressi
Changes in directory llvm/include/llvm/Analysis:
AliasSetTracker.h updated: 1.25 -> 1.26
---
Log message:
Add a simple clear() method
---
Diffs of the changes: (+5 -0)
AliasSetTracker.h |5 +
1 files changed, 5 insertions(+)
Index: llvm/include/llvm/Analysis/AliasSetTracker.h
dif
Changes in directory llvm/lib/Target/IA64:
IA64AsmPrinter.cpp updated: 1.20 -> 1.21
---
Log message:
No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
---
Diffs of the ch
Changes in directory llvm/lib/Target/X86:
X86IntelAsmPrinter.h updated: 1.3 -> 1.4
---
Log message:
Fix a typo in my latest change
---
Diffs of the changes: (+2 -2)
X86IntelAsmPrinter.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86IntelAsmPr
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.16 -> 1.17
X86ATTAsmPrinter.h updated: 1.2 -> 1.3
X86InstrInfo.td updated: 1.143 -> 1.144
X86IntelAsmPrinter.cpp updated: 1.12 -> 1.13
X86IntelAsmPrinter.h updated: 1.2 -> 1.3
---
Log message:
No longer track value types
Changes in directory llvm/utils/TableGen:
AsmWriterEmitter.cpp updated: 1.22 -> 1.23
---
Log message:
No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
---
Diffs of the c
Changes in directory llvm/lib/Target/Alpha:
AlphaAsmPrinter.cpp updated: 1.26 -> 1.27
---
Log message:
No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
---
Diffs of the
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.121 -> 1.122
---
Log message:
No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
---
Diffs of th
Changes in directory llvm/utils/TableGen:
Record.cpp updated: 1.47 -> 1.48
---
Log message:
Fix some copy and paste typos.
---
Diffs of the changes: (+2 -2)
Record.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/T
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.218 -> 1.219
---
Log message:
CALLSEQ_START/END nodes don't get memoized, do not add them in when
replaceAllUses'ing.
---
Diffs of the changes: (+4 -0)
SelectionDAG.cpp |4
1 files changed, 4 inserti
Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.191 -> 1.192
---
Log message:
remove redundant code
---
Diffs of the changes: (+2 -14)
AlphaISelPattern.cpp | 16 ++--
1 files changed, 2 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/Alpha/A
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.218 -> 1.219
---
Log message:
At long last, you can say that f32 isn't supported for setcc
---
Diffs of the changes: (+28 -1)
LegalizeDAG.cpp | 29 -
1 files changed, 28 insertions(+
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.8 -> 1.9
AlphaISelLowering.cpp updated: 1.11 -> 1.12
AlphaISelPattern.cpp updated: 1.190 -> 1.191
AlphaInstrInfo.td updated: 1.75 -> 1.76
---
Log message:
Make typesafe that which isn't: FCMOVxx
---
Diffs of the chang
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.7 -> 1.8
AlphaISelLowering.cpp updated: 1.10 -> 1.11
AlphaISelLowering.h updated: 1.4 -> 1.5
AlphaISelPattern.cpp updated: 1.189 -> 1.190
AlphaInstrInfo.td updated: 1.74 -> 1.75
---
Log message:
FPSelect and more custo
Changes in directory llvm/include/llvm/CodeGen:
ValueTypes.h updated: 1.14 -> 1.15
---
Log message:
First chunk of actually generating vector code for packed types. These
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.107 -> 1.108
---
Log message:
First chunk of actually generating vector code for packed types. These
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddf
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.130 -> 1.131
---
Log message:
First chunk of actually generating vector code for packed types. These
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v
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