[llvm-commits] CVS: llvm/include/llvm/ADT/PostOrderIterator.h

Changes in directory llvm/include/llvm/ADT: PostOrderIterator.h updated: 1.18 -> 1.19 --- Log message: Implement external storage for post-order iteration, implementing PR267: http://llvm.cs.uiuc.edu/PR267 Patch by Saem Ghani, thanks! --- Diffs of the changes: (+84 -10) PostOrderIterato

[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp

Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.29 -> 1.30 --- Log message: Teach the SelectionDAG ISel how to turn ConstantPacked values into constant nodes with vector types. Also teach the asm printer how to print ConstantPacked constant pool entries. This allows us to ge

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.80 -> 1.81 --- Log message: Teach the SelectionDAG ISel how to turn ConstantPacked values into constant nodes with vector types. Also teach the asm printer how to print ConstantPacked constant pool entries. This a

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.222 -> 1.223 SelectionDAG.cpp updated: 1.222 -> 1.223 SelectionDAGISel.cpp updated: 1.110 -> 1.111 --- Log message: Teach the SelectionDAG ISel how to turn ConstantPacked values into constant nodes with vector types

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.48 -> 1.49 PPCISelLowering.h updated: 1.10 -> 1.11 PPCInstrInfo.td updated: 1.151 -> 1.152 --- Log message: Use new PPC-specific nodes to represent shifts which require the 6-bit amount handling that PPC provides. Th

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrFormats.td AlphaInstrInfo.td

Changes in directory llvm/lib/Target/Alpha: AlphaInstrFormats.td updated: 1.16 -> 1.17 AlphaInstrInfo.td updated: 1.79 -> 1.80 --- Log message: added instructions with inverted immediates --- Diffs of the changes: (+23 -32) AlphaInstrFormats.td | 18 +- AlphaInstrInfo.td

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td

Changes in directory llvm/lib/Target/Alpha: AlphaInstrInfo.td updated: 1.78 -> 1.79 --- Log message: yea, it helps to have your path set right when testing --- Diffs of the changes: (+4 -2) AlphaInstrInfo.td |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/T

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrFormats.td AlphaInstrInfo.td

Changes in directory llvm/lib/Target/Alpha: AlphaInstrFormats.td updated: 1.15 -> 1.16 AlphaInstrInfo.td updated: 1.77 -> 1.78 --- Log message: These never trigger, but whatever --- Diffs of the changes: (+40 -9) AlphaInstrFormats.td | 18 ++ AlphaInstrInfo.td| 31 ++

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.84 -> 1.85 --- Log message: * Infer instruction property hasCtrlDep from pattern if it has one. * Fixed a bug related to hasCtrlDep property use. --- Diffs of the changes: (+50 -31) DAGISelEmitter.cpp | 81 +

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.147 -> 1.148 --- Log message: Remove unnecessary let hasCtrlDep=1 now it can be inferred. --- Diffs of the changes: (+25 -27) X86InstrInfo.td | 52 +--- 1 files changed, 2

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaInstrInfo.td

Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.12 -> 1.13 AlphaInstrInfo.td updated: 1.76 -> 1.77 --- Log message: move this over to the dag --- Diffs of the changes: (+9 -10) AlphaISelDAGToDAG.cpp |8 AlphaInstrInfo.td | 11 +-- 2 fi

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.70 -> 1.71 --- Log message: getRawValue zero extens for unsigned values, use getsextvalue so that we know that small negative values fit into the immediate field of addressing modes. --- Diffs of the changes:

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.11 -> 1.12 --- Log message: fix constant pool loads --- Diffs of the changes: (+1 -1) AlphaISelDAGToDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG