[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp SparcV8ISelSimple.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.18 - 1.19 SparcV8ISelSimple.cpp updated: 1.95 - 1.96 --- Log message: Implement the full V8 ABI for incoming arguments. --- Diffs of the changes: (+143 -28) SparcV8ISelDAGToDAG.cpp | 169

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.100 - 1.101 --- Log message: Select copytoreg and copyfromreg nodes that have flag operands correctly. --- Diffs of the changes: (+37 -9) DAGISelEmitter.cpp | 46 +- 1

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp SparcV8InstrInfo.td

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.19 - 1.20 SparcV8InstrInfo.td updated: 1.81 - 1.82 --- Log message: Implement Calls for V8. This would be completely autogenerated except for a small bug in tblgen. When that is fixed, we can remove the

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp SparcV8InstrInfo.td

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.20 - 1.21 SparcV8InstrInfo.td updated: 1.82 - 1.83 --- Log message: Change return lowering so that we can autogen the matching code. --- Diffs of the changes: (+25 -30) SparcV8ISelDAGToDAG.cpp | 49

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.142 - 1.143 --- Log message: This is handled by the autogen'd code --- Diffs of the changes: (+0 -1) PPCISelDAGToDAG.cpp |1 - 1 files changed, 1 deletion(-) Index:

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.102 - 1.103 --- Log message: Handle basic block nodes --- Diffs of the changes: (+1 -0) DAGISelEmitter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.50 - 1.51 --- Log message: Keep VC++ happy. --- Diffs of the changes: (+1 -0) ScheduleDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.23 - 1.24 --- Log message: Add support for calls to external symbols --- Diffs of the changes: (+2 -1) SparcV8ISelDAGToDAG.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/lib/Target/SparcV8/FPMover.cpp

Changes in directory llvm/lib/Target/SparcV8: FPMover.cpp updated: 1.7 - 1.8 --- Log message: Various cleanups to this pass, no functionality change --- Diffs of the changes: (+43 -46) FPMover.cpp | 89 1 files changed, 43

[llvm-commits] CVS: llvm/lib/Target/SparcV8/FPMover.cpp SparcV8InstrInfo.td

Changes in directory llvm/lib/Target/SparcV8: FPMover.cpp updated: 1.8 - 1.9 SparcV8InstrInfo.td updated: 1.87 - 1.88 --- Log message: add fneg/fabs support for doubles --- Diffs of the changes: (+37 -17) FPMover.cpp | 42 +++---

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td

Changes in directory llvm/lib/Target/SparcV8: SparcV8InstrInfo.td updated: 1.88 - 1.89 --- Log message: apparently rdy isn't actually a psuedo instruction. Use rd %y --- Diffs of the changes: (+1 -1) SparcV8InstrInfo.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.25 - 1.26 --- Log message: Keep stack frames 8-byte aligned. This fixes olden/voronoi --- Diffs of the changes: (+3 -0) SparcV8ISelDAGToDAG.cpp |3 +++ 1 files changed, 3 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.26 - 1.27 --- Log message: mark some unsupported ops as unsupported --- Diffs of the changes: (+11 -0) SparcV8ISelDAGToDAG.cpp | 11 +++ 1 files changed, 11 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td

Changes in directory llvm/lib/Target/SparcV8: SparcV8InstrInfo.td updated: 1.90 - 1.91 --- Log message: implement zextload bool --- Diffs of the changes: (+3 -0) SparcV8InstrInfo.td |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td diff -u

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td

Changes in directory llvm/lib/Target/SparcV8: SparcV8InstrInfo.td updated: 1.91 - 1.92 --- Log message: add the other bool zextload as well --- Diffs of the changes: (+1 -0) SparcV8InstrInfo.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td

Changes in directory llvm/lib/Target/SparcV8: SparcV8InstrInfo.td updated: 1.92 - 1.93 --- Log message: Correct bool truncstore operand order --- Diffs of the changes: (+2 -2) SparcV8InstrInfo.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8RegisterInfo.cpp updated: 1.29 - 1.30 --- Log message: don't emit 'add %o6, 0, %o6' instructions --- Diffs of the changes: (+6 -5) SparcV8RegisterInfo.cpp | 11 ++- 1 files changed, 6 insertions(+), 5 deletions(-) Index: