Changes in directory llvm/lib/Target/X86:
X86ISelPattern.cpp updated: 1.200 - 1.201
---
Log message:
Loosen up these checks to allow direct uses of ESP
---
Diffs of the changes: (+12 -4)
X86ISelPattern.cpp | 16
1 files changed, 12 insertions(+), 4 deletions(-)
Index:
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.54 - 1.55
---
Log message:
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
---
Diffs of the changes: (+10 -2)
X86ISelLowering.cpp | 12 ++--
1 files changed, 10 insertions(+), 2
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.34 - 1.35
---
Log message:
Add a enum to specify target scheduling preference: SchedulingForLatency or
SchedulingForRegPressure. Added corresponding methods to set / get the value.
---
Diffs of the changes: (+19 -0)
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.55 - 1.56
---
Log message:
X86 prefer scheduling for reduced register pressure.
---
Diffs of the changes: (+1 -0)
X86ISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.68 - 1.69
---
Log message:
Default scheduling preference is SchedulingForLatency.
---
Diffs of the changes: (+1 -0)
PPCISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.4 - 1.5
---
Log message:
Some minor scheduler changes.
---
Diffs of the changes: (+9 -4)
ScheduleDAG.h | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.57 - 1.58
---
Log message:
Keep track of bottom / top element of a set of flagged nodes.
---
Diffs of the changes: (+6 -1)
ScheduleDAG.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.1 - 1.2
---
Log message:
Bottom up register usage reducing list scheduler.
---
Diffs of the changes: (+451 -21)
ScheduleDAGList.cpp | 472 +---
1 files
Changes in directory llvm/lib/Bytecode/Reader:
Reader.cpp updated: 1.185 - 1.186
---
Log message:
Make it even more portable.
---
Diffs of the changes: (+1 -1)
Reader.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Bytecode/Reader/Reader.cpp
diff -u
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.16 - 1.17
---
Log message:
Make it even more portable.
---
Diffs of the changes: (+1 -1)
DwarfWriter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.2 - 1.3
---
Log message:
Fix VC++ compilation error.
---
Diffs of the changes: (+1 -1)
ScheduleDAGList.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.69 - 1.70
PPCISelLowering.h updated: 1.14 - 1.15
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.28 - 1.29
AlphaISelLowering.h updated: 1.11 - 1.12
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.56 - 1.57
X86ISelLowering.h updated: 1.15 - 1.16
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.276 - 1.277
SelectionDAG.cpp updated: 1.243 - 1.244
SelectionDAGISel.cpp updated: 1.136 - 1.137
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.35 - 1.36
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+0 -25)
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.57 - 1.58
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+18
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.26 - 1.27
IA64ISelLowering.h updated: 1.5 - 1.6
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.18 - 1.19
---
Log message:
Set SchedulingForLatency to be the default scheduling preference for all.
---
Diffs of the changes: (+1 -0)
TargetLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.27 - 1.28
---
Log message:
Set SchedulingForLatency to be the default scheduling preference for all.
---
Diffs of the changes: (+0 -1)
IA64ISelLowering.cpp |1 -
1 files changed, 1 deletion(-)
Index:
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.5 - 1.6
---
Log message:
No need to keep track of top and bottom nodes in a group since the vector is
already in order. Thanks Jim for pointing it out.
---
Diffs of the changes: (+3 -5)
ScheduleDAG.h |8 +++-
Changes in directory llvm/include/llvm:
Module.h updated: 1.68 - 1.69
---
Log message:
Change inline asms to be uniqued like constants, not embedded in a Module.
---
Diffs of the changes: (+0 -31)
Module.h | 31 ---
1 files changed, 31 deletions(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.70 - 1.71
---
Log message:
Set SchedulingForLatency to be the default scheduling preference for all.
---
Diffs of the changes: (+0 -1)
PPCISelLowering.cpp |1 -
1 files changed, 1 deletion(-)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.58 - 1.59
---
Log message:
No need to keep track of top and bottom nodes in a group since the vector is
already in order. Thanks Jim for pointing it out.
---
Diffs of the changes: (+0 -5)
ScheduleDAG.cpp |5
Changes in directory llvm-test/External/SPEC/CINT2000/252.eon:
Makefile updated: 1.12 - 1.13
---
Log message:
eon doesn't need exceptions
---
Diffs of the changes: (+2 -0)
Makefile |2 ++
1 files changed, 2 insertions(+)
Index: llvm-test/External/SPEC/CINT2000/252.eon/Makefile
diff
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.19 - 1.20
---
Log message:
initialize an instance var, apparently I forgot to commit this long ago
---
Diffs of the changes: (+1 -0)
TargetLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/VMCore:
AsmWriter.cpp updated: 1.189 - 1.190
InlineAsm.cpp updated: 1.1 - 1.2
Module.cpp updated: 1.63 - 1.64
---
Log message:
Change inline asms to be uniqued like constants, not embedded in a Module.
---
Diffs of the changes: (+6 -43)
AsmWriter.cpp |4
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.58 - 1.59
---
Log message:
Set SchedulingForLatency to be the default scheduling preference for all.
---
Diffs of the changes: (+0 -1)
SparcV8ISelDAGToDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index:
Changes in directory llvm/include/llvm:
InlineAsm.h updated: 1.3 - 1.4
---
Log message:
add some useful accessors :)
---
Diffs of the changes: (+3 -0)
InlineAsm.h |3 +++
1 files changed, 3 insertions(+)
Index: llvm/include/llvm/InlineAsm.h
diff -u llvm/include/llvm/InlineAsm.h:1.3
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.29 - 1.30
---
Log message:
make things compile again
---
Diffs of the changes: (+4 -0)
AlphaISelLowering.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff
Changes in directory llvm/include/llvm:
InlineAsm.h updated: 1.4 - 1.5
---
Log message:
add another method
---
Diffs of the changes: (+7 -0)
InlineAsm.h |7 +++
1 files changed, 7 insertions(+)
Index: llvm/include/llvm/InlineAsm.h
diff -u llvm/include/llvm/InlineAsm.h:1.4
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.30 - 1.31
---
Log message:
forgot one
---
Diffs of the changes: (+1 -0)
AlphaISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u
Changes in directory llvm/lib/VMCore:
AsmWriter.cpp updated: 1.190 - 1.191
InlineAsm.cpp updated: 1.2 - 1.3
---
Log message:
Print InlineAsm objects
---
Diffs of the changes: (+27 -9)
AsmWriter.cpp | 16
InlineAsm.cpp | 20 +++-
2 files changed, 27
Changes in directory llvm/lib/Bytecode/Writer:
SlotCalculator.cpp updated: 1.72 - 1.73
SlotCalculator.h updated: 1.22 - 1.23
Writer.cpp updated: 1.118 - 1.119
WriterInternals.h updated: 1.26 - 1.27
---
Log message:
add bc reader/writer support for inline asm
---
Diffs of the changes: (+41
Changes in directory llvm/docs:
BytecodeFormat.html updated: 1.49 - 1.50
---
Log message:
update the bytecode format guide for the encoding of inline asm.
---
Diffs of the changes: (+62 -10)
BytecodeFormat.html | 72
1 files changed,
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.31 - 1.32
---
Log message:
oops
---
Diffs of the changes: (+1 -1)
AlphaISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u
Changes in directory llvm/docs:
LangRef.html updated: 1.133 - 1.134
---
Log message:
document the syntax of inline asm
---
Diffs of the changes: (+56 -1)
LangRef.html | 57 -
1 files changed, 56 insertions(+), 1 deletion(-)
Changes in directory llvm/lib/VMCore:
Verifier.cpp updated: 1.145 - 1.146
---
Log message:
Make sure the only user of InlineAsm's are direct calls.
---
Diffs of the changes: (+4 -0)
Verifier.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/lib/VMCore/Verifier.cpp
diff -u
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.141 - 1.142
---
Log message:
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
---
Diffs of
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.6 - 1.7
---
Log message:
Duh.
---
Diffs of the changes: (+2 -2)
ScheduleDAG.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u
Changes in directory llvm/lib/VMCore:
InlineAsm.cpp updated: 1.3 - 1.4
---
Log message:
parse and verify the constraint string.
---
Diffs of the changes: (+68 -0)
InlineAsm.cpp | 68 ++
1 files changed, 68 insertions(+)
Index:
Changes in directory llvm/include/llvm:
Value.h updated: 1.82 - 1.83
---
Log message:
Allow use of isaInlineAsm(X) without #including InlineAsm.h
---
Diffs of the changes: (+4 -0)
Value.h |4
1 files changed, 4 insertions(+)
Index: llvm/include/llvm/Value.h
diff -u
Changes in directory llvm/lib/VMCore:
InlineAsm.cpp updated: 1.4 - 1.5
---
Log message:
add method for constraint parsing
---
Diffs of the changes: (+50 -29)
InlineAsm.cpp | 79 --
1 files changed, 50 insertions(+), 29 deletions(-)
Evan,
I don't know anything about this stuff, but looking at the pattern, it
seems a mistake may have been made? Consider these:
On Wed, 2006-01-25 at 20:27 -0600, Evan Cheng wrote:
void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
+ // This works
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrFormats.td updated: 1.24 - 1.25
AlphaInstrInfo.td updated: 1.108 - 1.109
---
Log message:
minor renaming
---
Diffs of the changes: (+16 -16)
AlphaInstrFormats.td |2 +-
AlphaInstrInfo.td| 30 +++---
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