Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.101 -> 1.102
---
Log message:
Lowering of sdiv X, pow2 was broken, this fixes it. This patch is written
by Nate, I'm just committing it for him.
---
Diffs of the changes: (+12 -6)
DAGCombiner.cpp | 18 +++
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.162 -> 1.163
---
Log message:
If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.157 -> 1.158
---
Log message:
If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, inver
Changes in directory llvm/lib/Target/IA64:
IA64AsmPrinter.cpp updated: 1.22 -> 1.23
---
Log message:
distinguish between objects and register names, now we can have stuff
with names like "f84", "in6" etc etc.
this should fix one or two tests
---
Diffs of the changes: (+12 -6)
IA64AsmPri
Changes in directory llvm-poolalloc/runtime/FL2Allocator:
PoolAllocator.cpp updated: 1.50 -> 1.51
---
Log message:
some programs call memalign, so there should be one
---
Diffs of the changes: (+7 -0)
PoolAllocator.cpp |7 +++
1 files changed, 7 insertions(+)
Index: llvm-poolalloc
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.25 -> 1.26
---
Log message:
Change SplitBlock to increment a BasicBlock::iterator, not an Instruction*.
Apparently they do different things :)
This fixes a testcase that nate reduced from spass.
Also included are a
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.233 -> 1.234
---
Log message:
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
---
Diffs of the changes: (+2 -2)
X86InstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib
Changes in directory llvm/tools/llc:
Makefile updated: 1.78 -> 1.79
---
Log message:
remove support for the skeleton target
---
Diffs of the changes: (+0 -5)
Makefile |5 -
1 files changed, 5 deletions(-)
Index: llvm/tools/llc/Makefile
diff -u llvm/tools/llc/Makefile:1.78 llvm/to
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.102 -> 1.103
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmark
Changes in directory llvm:
configure updated: 1.211 -> 1.212
---
Log message:
remove skeleton target
---
Diffs of the changes: (+1 -2)
configure |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/configure
diff -u llvm/configure:1.211 llvm/configure:1.212
--- llvm/co
Changes in directory llvm/autoconf:
configure.ac updated: 1.209 -> 1.210
---
Log message:
don't build the skeleton target
---
Diffs of the changes: (+1 -2)
configure.ac |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/autoconf/configure.ac
diff -u llvm/autoconf/con
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.85 -> 1.86
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.435 -> 1.436
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/ben
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.30 -> 1.31
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
-
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.49 -> 1.50
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on p
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.83 -> 1.84
X86ISelLowering.h updated: 1.25 -> 1.26
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested agai
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.122 -> 1.123
---
Log message:
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
---
Diffs of the changes: (+12 -4)
X86RegisterInfo.cpp | 16
1 files changed, 12 insertions(+), 4 deletion
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.44 -> 1.45
X86InstrInfo.td updated: 1.234 -> 1.235
X86RegisterInfo.cpp updated: 1.123 -> 1.124
---
Log message:
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
proves to be worth 20% on Ptrdist/
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.163 -> 1.164
---
Log message:
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
turns out not to point to a constant string but it forgot change the offset
back.
---
Diffs of the change
Changes in directory llvm/lib/Target/Skeleton:
Makefile (r1.4) removed
README.txt (r1.2) removed
Skeleton.h (r1.2) removed
Skeleton.td (r1.4) removed
SkeletonInstrInfo.cpp (r1.2) removed
SkeletonInstrInfo.h (r1.2) removed
SkeletonInstrInfo.td (r1.4) removed
SkeletonJITInfo.cpp (r1.3) removed
Ske
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.235 -> 1.236
---
Log message:
pxor (for FLD0SS) encoding was missing the OpSize prefix.
---
Diffs of the changes: (+1 -1)
X86InstrInfo.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.54 -> 1.55
---
Log message:
Remove the entry about using movapd for SSE reg-reg moves.
---
Diffs of the changes: (+0 -6)
README.txt |6 --
1 files changed, 6 deletions(-)
Index: llvm/lib/Target/X86/README.txt
diff -u
Changes in directory llvm/lib/Target/X86:
X86.h updated: 1.43 -> 1.44
X86ISelLowering.cpp updated: 1.84 -> 1.85
X86TargetMachine.cpp updated: 1.102 -> 1.103
X86ISelPattern.cpp (r1.204) removed
---
Log message:
Kill the x86 pattern isel. boom.
---
Diffs of the changes: (+211 -325)
X86.h
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.55 -> 1.56
---
Log message:
Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
issue. Need to do more experiments.
---
Diffs of the changes: (+6 -0)
README.txt |6 ++
1 files changed, 6 inser
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.26 -> 1.27
---
Log message:
start of some new simplification code, not thoroughly tested, use at your own
risk :)
---
Diffs of the changes: (+161 -14)
LoopUnswitch.cpp | 175 ++
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.45 -> 1.46
---
Log message:
Add a missing and useful pat frag
---
Diffs of the changes: (+9 -2)
TargetSelectionDAG.td | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/TargetS
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.46 -> 1.47
---
Log message:
Whoops, didn't mean to check this in yet.
---
Diffs of the changes: (+0 -8)
TargetSelectionDAG.td |8
1 files changed, 8 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.31 -> 1.32
---
Log message:
Fix bug noticed by VC++.
---
Diffs of the changes: (+2 -2)
TargetLowering.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llv
Changes in directory llvm/win32/x86:
x86.vcproj updated: 1.20 -> 1.21
---
Log message:
Inform Visual Studio of deleted file.
---
Diffs of the changes: (+0 -3)
x86.vcproj |3 ---
1 files changed, 3 deletions(-)
Index: llvm/win32/x86/x86.vcproj
diff -u llvm/win32/x86/x86.vcproj:1.20 llv
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.56 -> 1.57
---
Log message:
add note about div by power of 2
---
Diffs of the changes: (+32 -0)
README.txt | 32
1 files changed, 32 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.304 -> 1.305
---
Log message:
Fix another miscompilation exposed by lencode, where we lowered i64->f32
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).
---
D
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.47 -> 1.48
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Dif
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.86 -> 1.87
SparcInstrInfo.td updated: 1.121 -> 1.122
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
signi
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.85 -> 1.86
X86ISelLowering.h updated: 1.26 -> 1.27
X86InstrInfo.td updated: 1.236 -> 1.237
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose wh
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.158 -> 1.159
PPCInstrInfo.td updated: 1.176 -> 1.177
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
signi
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.103 -> 1.104
LegalizeDAG.cpp updated: 1.305 -> 1.306
SelectionDAG.cpp updated: 1.256 -> 1.257
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.101 -> 1.102
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
addc.ll added (r1.1)
subc.ll added (r1.1)
---
Log message:
A couple new regression tests to make sure we always pattern match the new
opcodes on ppc.
---
Diffs of the changes: (+51 -0)
addc.ll | 26 ++
sub
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
addc.ll updated: 1.1 -> 1.2
subc.ll updated: 1.1 -> 1.2
---
Log message:
Fix a comment sabre noticed :)
---
Diffs of the changes: (+2 -2)
addc.ll |2 +-
subc.ll |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Inde
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.27 -> 1.28
---
Log message:
Fix loops where the header has an exit, fixing a loop-unswitch crash on crafty
---
Diffs of the changes: (+15 -13)
LoopUnswitch.cpp | 28 +++-
1 files changed,
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.86 -> 1.87
---
Log message:
Unbreak x86 be
---
Diffs of the changes: (+22 -17)
X86ISelLowering.cpp | 39 ++-
1 files changed, 22 insertions(+), 17 deletions(-)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.87 -> 1.88
---
Log message:
unbreak the build
---
Diffs of the changes: (+0 -1)
X86ISelLowering.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.104 -> 1.105
---
Log message:
Don't expand sdiv by power of two before legalize, since it will likely
generate illegal nodes.
---
Diffs of the changes: (+2 -2)
DAGCombiner.cpp |4 ++--
1 files changed, 2 ins
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