Changes in directory llvm/Xcode/LLVM.xcodeproj:
project.pbxproj updated: 1.19 - 1.20
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Log message:
Misc. project changes. html + build config changes supplied by Devang.
---
Diffs of the changes: (+109 -112)
project.pbxproj | 221
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.138 - 1.139
PPCISelLowering.h updated: 1.44 - 1.45
PPCInstrAltivec.td updated: 1.46 - 1.47
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Log message:
Change the interface to the predicate that determines if vsplti* can be used.
No functionality changes.
---
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_shuffle.ll updated: 1.5 - 1.6
vec_spat.ll updated: 1.3 - 1.4
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Log message:
add new testcase
---
Diffs of the changes: (+27 -1)
vec_shuffle.ll | 16
vec_spat.ll| 12 +++-
2 files changed, 27
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.139 - 1.140
---
Log message:
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
constant pool load.
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Diffs of the changes: (+57 -0)
PPCISelLowering.cpp | 57
Changes in directory llvm/lib/Target/Alpha:
AlphaTargetMachine.cpp updated: 1.22 - 1.23
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Log message:
Disable switch lowering for targets based on the selection dag isel,
letting the code generator handle them directly.
---
Diffs of the changes: (+0 -6)
AlphaTargetMachine.cpp |6
Changes in directory llvm/lib/Target/Sparc:
SparcTargetMachine.cpp updated: 1.43 - 1.44
---
Log message:
Disable switch lowering for targets based on the selection dag isel,
letting the code generator handle them directly.
---
Diffs of the changes: (+0 -3)
SparcTargetMachine.cpp |3
Changes in directory llvm/lib/Target/IA64:
IA64TargetMachine.cpp updated: 1.13 - 1.14
---
Log message:
Disable switch lowering for targets based on the selection dag isel,
letting the code generator handle them directly.
---
Diffs of the changes: (+0 -3)
IA64TargetMachine.cpp |3 ---
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.cpp updated: 1.111 - 1.112
---
Log message:
Disable switch lowering for targets based on the selection dag isel,
letting the code generator handle them directly.
---
Diffs of the changes: (+0 -10)
X86TargetMachine.cpp | 10
Changes in directory llvm-test:
Makefile.programs updated: 1.202 - 1.203
---
Log message:
switch back to fastcc for x86 llcbeta
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Diffs of the changes: (+1 -1)
Makefile.programs |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm-test/Makefile.programs
diff -u
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.126 - 1.127
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Log message:
Add a new VSELECT node.
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Diffs of the changes: (+5 -0)
SelectionDAGNodes.h |5 +
1 files changed, 5 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.356 - 1.357
SelectionDAG.cpp updated: 1.296 - 1.297
SelectionDAGISel.cpp updated: 1.220 - 1.221
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Log message:
Add code generator support for VSELECT
---
Diffs of the changes: (+22 -10)
LegalizeDAG.cpp |
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.178 - 1.179
PPCISelLowering.cpp updated: 1.140 - 1.141
PPCInstrInfo.td updated: 1.214 - 1.215
---
Log message:
Add VRRC select support
---
Diffs of the changes: (+8 -2)
PPCISelDAGToDAG.cpp |5 -
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.141 - 1.142
---
Log message:
properly mark vector selects as expanded to select_cc
---
Diffs of the changes: (+4 -0)
PPCISelLowering.cpp |4
1 files changed, 4 insertions(+)
Index:
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