Re: [llvm-commits] Workaround for PR1508

On Jun 13, 2007, at 10:51 PM, Duncan Sands wrote: > Hi Chris, > >> + // Inform the MachineModuleInfo of the personality for this >> landing pad. >> + ConstantExpr *CE = dyn_cast(I.getOperand(2)); >> + assert(CE && CE->getOpcode() == Instruction::BitCast && >> >> Please just use cast<> instead

Re: [llvm-commits] Workaround for PR1508

Hi Chris, > + // Inform the MachineModuleInfo of the personality for this > landing pad. > + ConstantExpr *CE = dyn_cast(I.getOperand(2)); > + assert(CE && CE->getOpcode() == Instruction::BitCast && > > Please just use cast<> instead of dyn_cast, which guarantees no null > return. but the

[llvm-commits] CVS: llvm-www/pubs/2005-09-PASTE-GreedySuiteMinimization.html 2005-09-PASTE-GreedySuiteMinimization.pdf index.html

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[llvm-commits] CVS: llvm-www/pubs/2006-10-CASES-IncreaseMem.html

Changes in directory llvm-www/pubs: 2006-10-CASES-IncreaseMem.html updated: 1.1 -> 1.2 --- Log message: fix a unicode character --- Diffs of the changes: (+1 -1) 2006-10-CASES-IncreaseMem.html |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/pubs/2006-10-CASES-In

Re: [llvm-commits] CVS: llvm-www/pubs/2006-10-CASES-IncreaseMem.html 2006-10-CASES-IncreaseMem.pdf index.html

Chris Lattner wrote: > have only 4Ð10 KB of RAM and – ? Nick ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm-www/pubs/2006-10-CASES-IncreaseMem.html 2006-10-CASES-IncreaseMem.pdf index.html

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[llvm-commits] CVS: llvm-www/pubs/2005-07-ZimmermanMSThesis.html 2005-07-ZimmermanMSThesis.pdf index.html

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[llvm-commits] CVS: llvm-www/pubs/2006-09-SOC-Synthesis.html 2006-09-SOC-Synthesis.pdf index.html

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[llvm-commits] CVS: llvm-www/pubs/2006-01-LabrecqueMSThesis.html 2006-01-LabrecqueMSThesis.pdf index.html

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[llvm-commits] CVS: llvm-www/pubs/2006-10-ICNPC-ScalingTaskGraphs.html 2006-10-ICNPC-ScalingTaskGraphs.pdf index.html

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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h

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[llvm-commits] CVS: llvm/lib/Target/Target.td

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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp CodeGenTarget.cpp CodeGenRegisters.h

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Re: [llvm-commits] Workaround for PR1508

On Jun 13, 2007, at 10:55 AM, Duncan Sands wrote: > Look for eh.filter and eh.selector intrinsics in the > successor to an empty (exception for a branch) landing pad. > The big FIXME comment explains more. Testcase included, > along with an XFAIL for a test which uses eh.selector in a > routine

Re: [llvm-commits] proposed patch: shift when shift amount >= bit width

On Jun 13, 2007, at 12:06 PM, Lauro Ramos Venancio wrote: >> I don't think this is appropriate Lauro. The program needs to be >> fixed, it's not just a codegen or optimizer issue, everything in the >> compiler assumes that these shifts are undefined. Programs cannot >> reliably expect a compile

Re: [llvm-commits] proposed patch: shift when shift amount >= bit width

> I don't think this is appropriate Lauro. The program needs to be > fixed, it's not just a codegen or optimizer issue, everything in the > compiler assumes that these shifts are undefined. Programs cannot > reliably expect a compiler to do the right thing here, and your patch > isn't a fix. Now

Re: [llvm-commits] proposed patch: shift when shift amount >= bit width

On Jun 13, 2007, at 11:34 AM, Lauro Ramos Venancio wrote: >> >> This is not enough to make a compiler handle shifts by greater >> than the >> word size consistently; in both gcc and llvm-gcc, for example, the >> result of >> >> int y=32; >> x>>y >> >> depends on optimization level. > >

Re: [llvm-commits] proposed patch: shift when shift amount >= bit width

> > This is not enough to make a compiler handle shifts by greater than the > word size consistently; in both gcc and llvm-gcc, for example, the > result of > > int y=32; > x>>y > > depends on optimization level. I know. On x86, the result of int n = 32; 1

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.cpp updated: 1.40 -> 1.41 --- Log message: Handle blocks with 2 unconditional branches in AnalyzeBranch. --- Diffs of the changes: (+10 -0) PPCInstrInfo.cpp | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/lib/Tar

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp

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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp

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[llvm-commits] Workaround for PR1508

Look for eh.filter and eh.selector intrinsics in the successor to an empty (exception for a branch) landing pad. The big FIXME comment explains more. Testcase included, along with an XFAIL for a test which uses eh.selector in a routine with no landing pads (not possible in llvm-gcc generated code)

Re: [llvm-commits] proposed patch: shift when shift amount >= bit width

On Jun 12, 2007, at 1:19 PM, Lauro Ramos Venancio wrote: The attached patch unify the handle of shifts when the shift amount is greater or equal the bit width. Nowadays, LLVM evaluates shl(i32 X,32) to 0 in some places and to undef in other places. For compatibility purpose, this patch impleme

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.459 -> 1.460 --- Log message: When creating CopyFromReg nodes, always use legal types. And use the correct types for the result vector, even though it is currently bitcasted to a different type immediately. --

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.461 -> 1.462 --- Log message: Only correctly lower exception handing intrinsics if exception handling is turned on. Likewise for scanning of invokes to mark landing pads. --- Diffs of the changes: (+7 -8)

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.495 -> 1.496 SelectionDAG.cpp updated: 1.405 -> 1.406 SelectionDAGISel.cpp updated: 1.460 -> 1.461 --- Log message: Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and VCONCAT_VECTORS. Use these for CopyTo

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.191 -> 1.192 --- Log message: Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in the case that the full register is to be split into