Author: clamb
Date: Thu Jan 31 01:27:46 2008
New Revision: 46606
URL: http://llvm.org/viewvc/llvm-project?rev=46606&view=rev
Log:
Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex!
ComplexExpressions can now have attributes which affect how TableGen interprets
the patt
Author: clamb
Date: Thu Jan 31 01:09:08 2008
New Revision: 46605
URL: http://llvm.org/viewvc/llvm-project?rev=46605&view=rev
Log:
Add more thorough error checking for NULL register classes.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Modified: llvm/trunk/lib/CodeGen/Selecti
where this is already being done?
--
Chris
On Jan 2, 2008, at 12:55 PM, Chris Lattner wrote:
On Dec 28, 2007, at 11:56 PM, Christopher Lamb wrote:
URL: http://llvm.org/viewvc/llvm-project?rev=45403&view=rev
Log:
Disable null pointer folding transforms for non-generic address
spaces. Th
Author: clamb
Date: Sat Dec 29 01:56:53 2007
New Revision: 45403
URL: http://llvm.org/viewvc/llvm-project?rev=45403&view=rev
Log:
Disable null pointer folding transforms for non-generic address spaces. This
should probably be a target-specific predicate based on address space. That way
for targe
Author: clamb
Date: Thu Dec 20 01:21:11 2007
New Revision: 45256
URL: http://llvm.org/viewvc/llvm-project?rev=45256&view=rev
Log:
Implement review feedback, including additional transforms
(icmp slt (sub A B) 1) -> (icmp sle A B)
icmp sgt (sub A B) -1) -> (icmp sge A B)
and add testcase.
Added
f producing these. I agree
they're worth having.
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Author: clamb
Date: Tue Dec 18 15:32:20 2007
New Revision: 45173
URL: http://llvm.org/viewvc/llvm-project?rev=45173&view=rev
Log:
Fold subtracts into integer compares vs. zero. This improves generate code for
this case on X86
from
_foo:
movl$99, %ecx
movl4(%esp), %eax
Author: clamb
Date: Tue Dec 18 14:33:11 2007
New Revision: 45170
URL: http://llvm.org/viewvc/llvm-project?rev=45170&view=rev
Log:
Fix comments
Modified:
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL:
http://
Author: clamb
Date: Tue Dec 18 14:30:28 2007
New Revision: 45169
URL: http://llvm.org/viewvc/llvm-project?rev=45169&view=rev
Log:
Remove an orthogonal transformation of the selection condition from my most
recent submission.
Modified:
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
On Dec 18, 2007, at 10:55 AM, Chris Lattner wrote:
On Dec 18, 2007, at 1:34 AM, Christopher Lamb wrote:
Author: clamb
Date: Tue Dec 18 03:34:41 2007
New Revision: 45158
URL: http://llvm.org/viewvc/llvm-project?rev=45158&view=rev
Log:
Fold certain additions through selects (and t
Author: clamb
Date: Tue Dec 18 03:45:40 2007
New Revision: 45159
URL: http://llvm.org/viewvc/llvm-project?rev=45159&view=rev
Log:
Fix typos.
Modified:
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
llvm/trunk/test/Transforms/InstCombine/2007-12-18-AddSelCmpSub.ll
Modified: llv
t
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Author: clamb
Date: Tue Dec 18 03:34:41 2007
New Revision: 45158
URL: http://llvm.org/viewvc/llvm-project?rev=45158&view=rev
Log:
Fold certain additions through selects (and their compares) so as to eliminate
subtractions. This code is often produced by the SMAX expansion in SCEV.
This implement
Author: clamb
Date: Mon Dec 17 21:49:35 2007
New Revision: 45147
URL: http://llvm.org/viewvc/llvm-project?rev=45147&view=rev
Log:
Don't forget to print address space qualifiers when printing out the type
table! Thanks to Gordon Henriksen for pointing this out.
Modified:
llvm/trunk/lib/VMCore
Author: clamb
Date: Sun Dec 16 19:16:41 2007
New Revision: 45084
URL: http://llvm.org/viewvc/llvm-project?rev=45084&view=rev
Log:
Update to use new PointerType::getUnqual() api.
Modified:
llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp
llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp
Author: clamb
Date: Sun Dec 16 19:15:41 2007
New Revision: 45083
URL: http://llvm.org/viewvc/llvm-project?rev=45083&view=rev
Log:
Update to use new PointerType::getUnqual() api.
Modified:
llvm-gcc-4.0/trunk/gcc/config/i386/llvm-i386.cpp
llvm-gcc-4.0/trunk/gcc/config/rs6000/llvm-rs6000.cpp
Author: clamb
Date: Sun Dec 16 19:00:21 2007
New Revision: 45080
URL: http://llvm.org/viewvc/llvm-project?rev=45080&view=rev
Log:
Make it clear in the LangRef that allocation instructions only operated on the
generic address space. Implement support in the verifier for ensuring this is
true.
Mo
fault. Perhaps the key
here is whether the un-modeled effects of the instruction affect
correct program behavior?
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lt values. This should at least make it
explicit in the code which clients do not pass in an address space.
There are currently many clients, so this should help make the work
incremental.
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llvm
Author: clamb
Date: Wed Dec 12 02:44:39 2007
New Revision: 44933
URL: http://llvm.org/viewvc/llvm-project?rev=44933&view=rev
Log:
Implement part of review feedback for address spaces.
Modified:
llvm/trunk/docs/LangRef.html
llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
llvm/trunk/lib/
nk this precludes the compiler from placing all functions
in a non-default address space, however I'm not sure what that would
get you other than a different way to handle function pointers. I
assume you don't need address spaces to deal specially with function
pointers in the
ied to do this though. Also
there are nasty side affects of allowing addrspace() on types in
ConstVals in the parser as it allows addrspace() then on types used
in constant expressions. I think the current way really is best right
now.
--
Christopher Lamb
_
27;Types' rather than 'ConstVal', so it works just
fine.
Please verify that the number of shift/reduce and reduce/reduce
conflicts doesn't go up.
They don't.
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On Dec 11, 2007, at 10:12 PM, Christopher Lamb wrote:
On Dec 11, 2007, at 9:16 PM, Chris Lattner wrote:
On Dec 11, 2007, at 9:08 PM, Christopher Lamb wrote:
On Dec 11, 2007, at 8:50 PM, Chris Lattner wrote:
That is a very strong argument to me, but it seems to argue even
more
strongly
On Dec 11, 2007, at 9:16 PM, Chris Lattner wrote:
>
> On Dec 11, 2007, at 9:08 PM, Christopher Lamb wrote:
>
>>
>> On Dec 11, 2007, at 8:50 PM, Chris Lattner wrote:
>>
>>>>> That is a very strong argument to me, but it seems to argue even
>>>&g
On Dec 11, 2007, at 4:12 PM, Chris Lattner wrote:
On Dec 11, 2007, at 12:59 AM, Christopher Lamb wrote:
=
=
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer
, I think bison will get extremely grumpy about this.
I feared.
Quick question, what is the syntax for an external GV with an ASI?
Sticky wicket, that. It should be:
@foo = external global i32 addrspace(1)
But that's not working right now....
s good, but I'm not sure about
the comma. The addrspace() qualifier can not be positionally
permuted with other attributes, the comma gives the impression that
it can be.
Good point, but I don't think lack of comma really makes it clear
either...
I agree. No compro
On Dec 11, 2007, at 8:34 PM, Chris Lattner wrote:
On Dec 11, 2007, at 5:56 PM, Christopher Lamb wrote:
On Dec 11, 2007, at 3:54 PM, Chris Lattner wrote:
On Dec 11, 2007, at 1:31 AM, Christopher Lamb wrote:
Add information on address space qualifiers for pointer types and
global
On Dec 11, 2007, at 4:12 PM, Chris Lattner wrote:
On Dec 11, 2007, at 12:59 AM, Christopher Lamb wrote:
URL: http://llvm.org/viewvc/llvm-project?rev=44858&view=rev
Log:
Implement address space attribute for LLVM pointer types. Address
spaces are
regions of memory that have a target spec
On Dec 11, 2007, at 3:54 PM, Chris Lattner wrote:
On Dec 11, 2007, at 1:31 AM, Christopher Lamb wrote:
Add information on address space qualifiers for pointer types and
global
declarations to the LangRef.
Nice!
[EMAIL PROTECTED] = constant float 1.0 addrspace(5), section "foo&qu
Author: clamb
Date: Tue Dec 11 03:32:07 2007
New Revision: 44861
URL: http://llvm.org/viewvc/llvm-project?rev=44861&view=rev
Log:
Update credits.
Modified:
llvm/trunk/CREDITS.TXT
Modified: llvm/trunk/CREDITS.TXT
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=44861&r1=44
Author: clamb
Date: Tue Dec 11 03:31:00 2007
New Revision: 44860
URL: http://llvm.org/viewvc/llvm-project?rev=44860&view=rev
Log:
Add information on address space qualifiers for pointer types and global
declarations to the LangRef.
Modified:
llvm/trunk/docs/LangRef.html
Modified: llvm/trunk
Author: clamb
Date: Tue Dec 11 02:59:05 2007
New Revision: 44858
URL: http://llvm.org/viewvc/llvm-project?rev=44858&view=rev
Log:
Implement address space attribute for LLVM pointer types. Address spaces are
regions of memory that have a target specific relationship, as described in the
Embedded
Author: clamb
Date: Mon Dec 10 01:24:06 2007
New Revision: 44785
URL: http://llvm.org/viewvc/llvm-project?rev=44785&view=rev
Log:
Improve branch folding by recgonizing that explict successor relationships
impact the value of fall-through choices.
Modified:
llvm/trunk/lib/CodeGen/BranchFoldin
Author: clamb
Date: Thu Oct 18 14:31:38 2007
New Revision: 43146
URL: http://llvm.org/viewvc/llvm-project?rev=43146&view=rev
Log:
Add an uppercase conversion utility function.
Modified:
llvm/trunk/include/llvm/ADT/StringExtras.h
Modified: llvm/trunk/include/llvm/ADT/StringExtras.h
URL:
http
Author: clamb
Date: Thu Oct 18 14:29:45 2007
New Revision: 43145
URL: http://llvm.org/viewvc/llvm-project?rev=43145&view=rev
Log:
Fix a misnamed parameter.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-
Author: clamb
Date: Thu Oct 18 14:28:55 2007
New Revision: 43144
URL: http://llvm.org/viewvc/llvm-project?rev=43144&view=rev
Log:
Fix a typo
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL:
http://llvm.org/viewvc/llvm-project/l
)
+++ llvm/trunk/CREDITS.TXT Fri Aug 10 17:22:41 2007
@@ -135,7 +135,8 @@
N: Christopher Lamb
E: [EMAIL PROTECTED]
-D: aligned load/store support
+D: aligned load/store support, parts of noalias and restrict support
+D: vreg subreg infrastructure, X86 codegen improvements based on subregs
Author: clamb
Date: Fri Aug 10 17:20:57 2007
New Revision: 41012
URL: http://llvm.org/viewvc/llvm-project?rev=41012&view=rev
Log:
Fix test so it passes.
Modified:
llvm/trunk/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
Modified: llvm/trunk/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
URL:
h
Author: clamb
Date: Fri Aug 10 16:48:46 2007
New Revision: 41010
URL: http://llvm.org/viewvc/llvm-project?rev=41010&view=rev
Log:
Increase efficiency of sign_extend_inreg by using subregisters for truncation.
As the README suggests sign_extend_subreg is selected to (sext(trunc)).
Added:
llvm
Author: clamb
Date: Fri Aug 10 16:29:05 2007
New Revision: 41009
URL: http://llvm.org/viewvc/llvm-project?rev=41009&view=rev
Log:
Edit README in light of previous LEA16 commit.
Modified:
llvm/trunk/lib/Target/X86/README.txt
Modified: llvm/trunk/lib/Target/X86/README.txt
URL:
http://llvm.org
Author: clamb
Date: Fri Aug 10 16:18:25 2007
New Revision: 41007
URL: http://llvm.org/viewvc/llvm-project?rev=41007&view=rev
Log:
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via
subregisters when 16-bit LEA is disabled.
Added:
llvm/trunk/test/CodeGen/X86/2007-08-10-
Author: clamb
Date: Fri Aug 10 16:11:55 2007
New Revision: 41005
URL: http://llvm.org/viewvc/llvm-project?rev=41005&view=rev
Log:
Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in
LowerSubregs and add more debugging output there.
Modified:
llvm/trunk/include/llvm/Target/MR
On Aug 9, 2007, at 3:20 PM, Evan Cheng wrote:
On Aug 9, 2007, at 2:45 PM, Christopher Lamb wrote:
Evan,
I don't think that this change is working quite correctly, and may
not be needed, given the way that the subreg code uses those
values. This is currently causing regressio
assList = [GR8_, GR16_];
}
// Scalar SSE2 floating point registers.
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Author: clamb
Date: Mon Aug 6 11:33:56 2007
New Revision: 40863
URL: http://llvm.org/viewvc/llvm-project?rev=40863&view=rev
Log:
Implement review feedback. No functionality change.
Modified:
llvm/trunk/include/llvm/CodeGen/Passes.h
llvm/trunk/lib/CodeGen/LowerSubregs.cpp
Modified: llvm/
Author: clamb
Date: Thu Aug 2 12:52:00 2007
New Revision: 40745
URL: http://llvm.org/viewvc/llvm-project?rev=40745&view=rev
Log:
Implement review feedback.
Modified:
llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL:
http://llvm.org
Author: clamb
Date: Wed Aug 1 20:18:14 2007
New Revision: 40711
URL: http://llvm.org/viewvc/llvm-project?rev=40711&view=rev
Log:
Teach BasicAA about noalias parameter attributes, but do it correctly this time.
Added:
llvm/trunk/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll
llvm/tru
Author: clamb
Date: Wed Aug 1 13:48:29 2007
New Revision: 40681
URL: http://llvm.org/viewvc/llvm-project?rev=40681&view=rev
Log:
Clean up C++ restrict test cases and add a test for restrict qualified methods.
Added:
llvm/trunk/test/C++Frontend/2007-08-01-RestrictMethod.cpp
Added: llvm/trunk
Author: clamb
Date: Wed Aug 1 13:19:14 2007
New Revision: 40679
URL: http://llvm.org/viewvc/llvm-project?rev=40679&view=rev
Log:
Bring across restrict handling from llvm-gcc-4.0. This should fix PR1582 on
both llvm-gcc projects.
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
llvm-gcc
Author: clamb
Date: Wed Aug 1 13:16:29 2007
New Revision: 40678
URL: http://llvm.org/viewvc/llvm-project?rev=40678&view=rev
Log:
Clean up comments and 80 col violations.
Modified:
llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
Modified: llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
URL:
http://llvm.org/vie
Author: clamb
Date: Tue Jul 31 23:17:42 2007
New Revision: 40664
URL: http://llvm.org/viewvc/llvm-project?rev=40664&view=rev
Log:
Clean up restrict handling per feedback.
Modified:
llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
Modified: llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
URL:
http://llvm.org/vie
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On Jul 31, 2007, at 3:02 PM, Christopher Lamb wrote:
>
>
> On Jul 31, 2007, at 1:59 PM, Anton Korobeynikov wrote:
>
>> Hello, Christopher.
>>
>>> -return TypeDB.setType(type, ConvertFunctionType(type, NULL,
>>> CallingConv));
>>> +r
be "declaration" tree, not
"type" tree. This was caused build error on darwin (reported by
Tanya):
Right. It seems that getting the declaration tree at that point is
rather difficult. Any suggestions?
--
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have a suggestion on a more proper way to consistently get the
restrict qualifier I'm all ears. =)
What was the function decl in that case?
How can I find/dump that? My GCC fu is weak.
--
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Author: clamb
Date: Tue Jul 31 11:18:07 2007
New Revision: 40635
URL: http://llvm.org/viewvc/llvm-project?rev=40635&view=rev
Log:
Revert overly aggressive interpretation of noalias
Removed:
llvm/trunk/test/Analysis/BasicAA/2007-07-31-NoAliasTest.ll
Modified:
llvm/trunk/lib/Analysis/BasicA
have a suggestion on a more proper way to consistently get the
restrict qualifier I'm all ears. =)
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Author: clamb
Date: Tue Jul 31 02:04:51 2007
New Revision: 40624
URL: http://llvm.org/viewvc/llvm-project?rev=40624&view=rev
Log:
Teach BasicAA about noalias function parameters. Passes all of DejaGNU and
test-suite.
Added:
llvm/trunk/test/Analysis/BasicAA/2007-07-31-NoAliasTest.ll
Modified:
Author: clamb
Date: Tue Jul 31 02:03:24 2007
New Revision: 40623
URL: http://llvm.org/viewvc/llvm-project?rev=40623&view=rev
Log:
Un-XFAIL these tests after r40622 fixed them.
Modified:
llvm/trunk/test/C++Frontend/2007-07-29-RestrictPtrArg.cpp
llvm/trunk/test/C++Frontend/2007-07-29-Restri
Author: clamb
Date: Tue Jul 31 01:50:25 2007
New Revision: 40622
URL: http://llvm.org/viewvc/llvm-project?rev=40622&view=rev
Log:
Add support for scraping the function decl for restrict qualifiers to handle
restrict function parameters for both C/C++. Thanks to Sheng Zhou for pointing
the way...
7;s doable...
There is an internal architecture here that it would be interesting
to target with LLVM, but it happens to have a highly constrained
register file, requiring many of these currently un-coalesced moves
between register sub classes and their parent. Do you think I
On Jul 30, 2007, at 11:06 AM, Evan Cheng wrote:
On Jul 30, 2007, at 12:02 AM, Christopher Lamb wrote:
On Jul 29, 2007, at 10:20 PM, Evan Cheng wrote:
On Jul 29, 2007, at 9:37 PM, Christopher Lamb wrote:
On Jul 29, 2007, at 6:20 PM, Evan Cheng wrote:
Sent from my iPhone
On Jul 28
On Jul 29, 2007, at 10:20 PM, Evan Cheng wrote:
On Jul 29, 2007, at 9:37 PM, Christopher Lamb wrote:
On Jul 29, 2007, at 6:20 PM, Evan Cheng wrote:
Sent from my iPhone
On Jul 28, 2007, at 4:36 PM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul 28, 2007, at 2:26 PM, Evan
On Jul 29, 2007, at 6:20 PM, Evan Cheng wrote:
Sent from my iPhone
On Jul 28, 2007, at 4:36 PM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul 28, 2007, at 2:26 PM, Evan Cheng wrote:
On Jul 28, 2007, at 11:52 AM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul
Author: clamb
Date: Sun Jul 29 18:29:16 2007
New Revision: 40583
URL: http://llvm.org/viewvc/llvm-project?rev=40583&view=rev
Log:
Add tests for generating noalias parameter attribute from __restrict qualified
function parameters. C++ tests are currently XFAILing see PR1582.
Added:
llvm/trunk
Author: clamb
Date: Sun Jul 29 18:25:53 2007
New Revision: 40582
URL: http://llvm.org/viewvc/llvm-project?rev=40582&view=rev
Log:
Add support to emit noalias attribute on function parameters when the
__restrict qualifier is used.
Modified:
llvm-gcc-4.0/trunk/gcc/llvm-types.cpp
Modified: llv
This patch causes anyext and zext to be code generated as insert_subreg on x86-64. It passes all tests on my system, but my system isn't x86-64. If someone would give it a run that'd be appreciated.Thanks --Christopher Lamb
x86_64_zext_subreg.patch
Description: B
Author: clamb
Date: Sat Jul 28 20:24:57 2007
New Revision: 40578
URL: http://llvm.org/viewvc/llvm-project?rev=40578&view=rev
Log:
Change the x86 backend to use extract_subreg for truncation operations. Passes
DejaGnu, SingleSource and MultiSource.
Modified:
llvm/trunk/lib/Target/X86/X86ATTAs
On Jul 28, 2007, at 2:26 PM, Evan Cheng wrote:
On Jul 28, 2007, at 11:52 AM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul 28, 2007, at 1:48 AM, Evan Cheng wrote:
Very cool! I need to read it more carefully.
But I see you are lowering zext to a single insert_subreg. Is
On Jul 28, 2007, at 11:55 AM, Christopher Lamb wrote:
On Jul 28, 2007, at 2:08 AM, Evan Cheng wrote:
On Jul 28, 2007, at 12:17 AM, Christopher Lamb wrote:
This patch changes the X86 back end to use the new subreg
operations for appropriate truncate and extend operations. This
should
Author: clamb
Date: Sat Jul 28 14:03:30 2007
New Revision: 40572
URL: http://llvm.org/viewvc/llvm-project?rev=40572&view=rev
Log:
Add register info needed to use subreg sets on X86.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
On Jul 28, 2007, at 2:08 AM, Evan Cheng wrote:
On Jul 28, 2007, at 12:17 AM, Christopher Lamb wrote:
This patch changes the X86 back end to use the new subreg
operations for appropriate truncate and extend operations. This
should allow regression testing of the subreg feature going
all writes to 32-bit registers implicitly zero-extend into the
upper 32-bits.
--
Chris
Sent from my iPhone
On Jul 28, 2007, at 12:17 AM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
This patch changes the X86 back end to use the new subreg
operations for appropriate truncate and e
, but there are changes for x86-64 as well which I haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated.Thanks --Christopher Lamb
x86_subregs.patch
Desc
On Jul 27, 2007, at 12:07 PM, Evan Cheng wrote:
On Jul 26, 2007, at 11:52 PM, Christopher Lamb wrote:
On Jul 26, 2007, at 10:28 PM, Evan Cheng wrote:
I don't think they are target opcodes.
Is that a suggestion? In the implementation they are:
--- llvm/trunk/include/llvm/T
Author: clamb
Date: Fri Jul 27 02:36:14 2007
New Revision: 40548
URL: http://llvm.org/viewvc/llvm-project?rev=40548&view=rev
Log:
Move subreg lowering pass to be right after regalloc, per feedback.
Modified:
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
Modified: llvm/trunk/lib/CodeGen/LLVMTa
On Jul 26, 2007, at 10:47 PM, Evan Cheng wrote:
Sent from my iPhone
On Jul 26, 2007, at 8:41 PM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul 26, 2007, at 6:30 PM, Evan Cheng wrote:
Should this be right after register allocation? Any reason to
keep the pseudo instru
'd in ScheduleDAG to the TargetInstrInfo types.
Target opcodes are those that are target specific, I.e. not shared
between targets.
They're part of the low instruction numbers for all targets.
--
Chris
On Jul 26, 2007, at 8:36 PM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul
d be OK to put it
before them. Thoughts?
Evan
On Jul 26, 2007, at 1:18 AM, Christopher Lamb wrote:
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
+
+ PM.add(createLowerSubregsPass());
__
On Jul 26, 2007, at 6:27 PM, Evan Cheng wrote:
On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
/// EmitNode - Generate machine code for an node and needed
dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
@@ -436,6 +578,14 @@
// If machine instruction
if (Node
Author: clamb
Date: Thu Jul 26 03:12:07 2007
New Revision: 40520
URL: http://llvm.org/viewvc/llvm-project?rev=40520&view=rev
Log:
Teach DAG scheduling how to properly emit subreg insert/extract machine
instructions. PR1350
Modified:
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
llvm/trun
erSubregs.cpp - Subregister Lowering instruction pass
--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by Christopher Lamb and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===
Author: clamb
Date: Thu Jul 26 03:01:58 2007
New Revision: 40519
URL: http://llvm.org/viewvc/llvm-project?rev=40519&view=rev
Log:
Have register info provide the inverse mapping of register->superregisters.
PR1350
Modified:
llvm/trunk/include/llvm/Target/MRegisterInfo.h
llvm/trunk/utils/T
Author: clamb
Date: Thu Jul 26 02:48:21 2007
New Revision: 40518
URL: http://llvm.org/viewvc/llvm-project?rev=40518&view=rev
Log:
Add target independent MachineInstr's to represent subreg insert/extract in
MBB's. PR1350
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trun
Author: clamb
Date: Thu Jul 26 02:34:40 2007
New Revision: 40516
URL: http://llvm.org/viewvc/llvm-project?rev=40516&view=rev
Log:
Add selection DAG nodes for subreg insert/extract. PR1350
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/lib/CodeGen/SelectionDAG/Leg
Author: clamb
Date: Thu Jul 26 02:03:08 2007
New Revision: 40515
URL: http://llvm.org/viewvc/llvm-project?rev=40515&view=rev
Log:
Fix 80 col violation.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
URL:
http:/
Author: clamb
Date: Thu Jul 26 02:00:46 2007
New Revision: 40514
URL: http://llvm.org/viewvc/llvm-project?rev=40514&view=rev
Log:
Remove subreg index from MachineInstr's and also keep vregs as unsigned when
adding operands.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/tr
27;d missed the file. Thanks!
--
Chris
On Jul 25, 2007, at 6:46 PM, Christopher Lamb
<[EMAIL PROTECTED]
wrote:
Author: clamb
Date: Wed Jul 25 20:46:52 2007
New Revision: 40506
URL: http://llvm.org/viewvc/llvm-project?rev=40506&view=rev
Log:
Add support for 3 element 32-bit vector Val
Author: clamb
Date: Thu Jul 26 01:41:18 2007
New Revision: 40513
URL: http://llvm.org/viewvc/llvm-project?rev=40513&view=rev
Log:
Teach TableGen about the new vector types.
Modified:
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL:
http:
On Jul 25, 2007, at 11:02 PM, Christopher Lamb wrote:
On Jul 25, 2007, at 10:50 PM, Evan Cheng wrote:
Hi Chris,
Can codegen handle non-pow 2 vector types? Are you planning to add it
soon? :-)
On my local copy codegen appears to be able to handle non-pow 2
vector types, but still can&#
'm
away from my Mac so I can't check.
I think the ValueTypes.td changes cover that. I've been using these
types in our target's .td files for quite a while now.
Sent from my iPhone
Rub it in, eh? =)
--
Chris
On Jul 25, 2007, at 6:46 PM, Christopher Lamb
<[EMAIL PR
Author: clamb
Date: Wed Jul 25 22:33:13 2007
New Revision: 40510
URL: http://llvm.org/viewvc/llvm-project?rev=40510&view=rev
Log:
Fix infinite recursion for when extract_vector_elt is legal. Unfortunately no
public targets use this code-path, so no test.
Modified:
llvm/trunk/lib/CodeGen/Sele
Author: clamb
Date: Wed Jul 25 20:48:57 2007
New Revision: 40507
URL: http://llvm.org/viewvc/llvm-project?rev=40507&view=rev
Log:
Fix comments for new types.
Modified:
llvm/trunk/include/llvm/CodeGen/ValueTypes.td
Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td
URL:
http://llvm.org/
Author: clamb
Date: Wed Jul 25 20:46:52 2007
New Revision: 40506
URL: http://llvm.org/viewvc/llvm-project?rev=40506&view=rev
Log:
Add support for 3 element 32-bit vector ValueTypes.
Modified:
llvm/trunk/include/llvm/CodeGen/ValueTypes.h
llvm/trunk/include/llvm/CodeGen/ValueTypes.td
ll
stores that are not side affecting as well. It would be good to have
this be open to customization.
--
Christopher Lamb
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Whoops! Omitted a hunk.On Jun 16, 2007, at 9:14 PM, Christopher Lamb wrote:This actually adds some new SDNodes, and I want to make sure I've done it right. After this patch the SDNodes are there, but ScheduleDAG will assert out if they're used. No dg regressions that I can tell from
Whoops! Omitted a hunk.
On Jun 16, 2007, at 9:14 PM, Christopher Lamb wrote:
This actually adds some new SDNodes, and I want to make sure I've
done it right. After this patch the SDNodes are there, but
ScheduleDAG will assert out if they're used. No dg regressions that
I can
citly). Give me the thumbs up and I'll commit it. --Christopher Lamb
PR1350_2.patch
Description: Binary data
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