Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.124 -> 1.125
---
Log message:
Fix some VC++ warnings.
---
Diffs of the changes: (+1 -0)
ScheduleDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llv
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.123 -> 1.124
---
Log message:
Code clean up.
---
Diffs of the changes: (+20 -23)
ScheduleDAG.cpp | 43 ---
1 files changed, 20 insertions(+), 23 deletions(-)
Index: ll
Thanks. But please factor out the code that looks for the register
class into a function so it can be shared between CopyToReg and
CopyFromReg.
Evan
On Mar 20, 2007, at 9:47 AM, Lauro Ramos Venancio wrote:
>
>
> Changes in directory llvm/lib/CodeGen/SelectionDAG:
>
> ScheduleDAG.cpp updated:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.122 -> 1.123
---
Log message:
CopyToReg source operand can be a physical register.
---
Diffs of the changes: (+19 -3)
ScheduleDAG.cpp | 22 +++---
1 files changed, 19 insertions(+), 3 deletions
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.121 -> 1.122
---
Log message:
print target nodes nicely
---
Diffs of the changes: (+1 -1)
ScheduleDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/Schedule
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.120 -> 1.121
---
Log message:
fix indentation
---
Diffs of the changes: (+2 -2)
ScheduleDAG.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.119 -> 1.120
---
Log message:
Apply B Scott Michel's patch for PR1184: http://llvm.org/PR1184 , which
improves diagnostics in an
abort case.
---
Diffs of the changes: (+16 -2)
ScheduleDAG.cpp | 18 +++
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.117 -> 1.118
ScheduleDAGSimple.cpp updated: 1.24 -> 1.25
---
Log message:
switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.115 -> 1.116
---
Log message:
Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().
---
Diffs of the changes: (+1 -1)
ScheduleDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Ind
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.114 -> 1.115
---
Log message:
Remove the DoubleTy special case.
---
Diffs of the changes: (+5 -9)
ScheduleDAG.cpp | 14 +-
1 files changed, 5 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.113 -> 1.114
---
Log message:
Compensate for loss of DerivedTypes.h in TargetLowering.h
---
Diffs of the changes: (+1 -0)
ScheduleDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/Selec
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.112 -> 1.113
---
Log message:
CopyToReg source operand can be a register as well. e.g. Copy from
GlobalBaseReg.
---
Diffs of the changes: (+6 -2)
ScheduleDAG.cpp |8 ++--
1 files changed, 6 insertions(+)
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.110 -> 1.111
ScheduleDAGRRList.cpp updated: 1.21 -> 1.22
---
Log message:
Match TargetInstrInfo changes.
---
Diffs of the changes: (+5 -10)
ScheduleDAG.cpp |3 +--
ScheduleDAGRRList.cpp | 12 -
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.109 -> 1.110
SelectionDAGISel.cpp updated: 1.320 -> 1.321
---
Log message:
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
---
Diffs of the changes: (+
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.108 -> 1.109
---
Log message:
Matches MachineInstr changes.
---
Diffs of the changes: (+1 -4)
ScheduleDAG.cpp |5 +
1 files changed, 1 insertion(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/S
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.107 -> 1.108
---
Log message:
Add methods to add implicit def use operands to a MI.
---
Diffs of the changes: (+1 -10)
ScheduleDAG.cpp | 11 +--
1 files changed, 1 insertion(+), 10 deletions(-)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.106 -> 1.107
---
Log message:
Add implicit def / use operands to MachineInstr.
---
Diffs of the changes: (+12 -0)
ScheduleDAG.cpp | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/CodeGen/S
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.105 -> 1.106
ScheduleDAGList.cpp updated: 1.67 -> 1.68
ScheduleDAGRRList.cpp updated: 1.19 -> 1.20
---
Log message:
Changes to use operand constraints to process two-address instructions.
---
Diffs of the changes:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.104 -> 1.105
---
Log message:
handle global address constant sdnodes
---
Diffs of the changes: (+7 -2)
ScheduleDAG.cpp |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.103 -> 1.104
ScheduleDAGRRList.cpp updated: 1.14 -> 1.15
---
Log message:
Debug tweak.
---
Diffs of the changes: (+4 -4)
ScheduleDAG.cpp |4 ++--
ScheduleDAGRRList.cpp |4 ++--
2 files changed, 4 in
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.102 -> 1.103
SelectionDAG.cpp updated: 1.337 -> 1.338
SelectionDAGCSEMap.cpp updated: 1.8 -> 1.9
SelectionDAGPrinter.cpp updated: 1.33 -> 1.34
---
Log message:
Added support for machine specific constantpool values.
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.101 -> 1.102
SelectionDAGISel.cpp updated: 1.271 -> 1.272
---
Log message:
Completely eliminate def&use operands. Now a register operand is EITHER a
def operand or a use operand.
---
Diffs of the changes: (+12 -1
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.100 -> 1.101
ScheduleDAGList.cpp updated: 1.65 -> 1.66
ScheduleDAGRRList.cpp updated: 1.12 -> 1.13
---
Log message:
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
This reduces selectionda
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.99 -> 1.100
---
Log message:
Reverse the FlaggedNodes after scanning up for flagged preds or else the order
would be reversed.
---
Diffs of the changes: (+10 -5)
ScheduleDAG.cpp | 15 ++-
1 files c
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.98 -> 1.99
ScheduleDAGRRList.cpp updated: 1.8 -> 1.9
---
Log message:
Use an enumeration to eliminate data relocations.
---
Diffs of the changes: (+24 -7)
ScheduleDAG.cpp | 29 +++
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.97 -> 1.98
---
Log message:
It was pointed out that DEBUG() is only available with -debug.
---
Diffs of the changes: (+3 -1)
ScheduleDAG.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.95 -> 1.96
---
Log message:
Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.94 -> 1.95
---
Log message:
commuteInstruction() does not always create a new MI!
---
Diffs of the changes: (+4 -2)
ScheduleDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/l
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.93 -> 1.94
---
Log message:
Eliminate a memory leak.
---
Diffs of the changes: (+1 -0)
ScheduleDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.92 -> 1.93
---
Log message:
lib/Target/Target.td
---
Diffs of the changes: (+13 -12)
ScheduleDAG.cpp | 25 +
1 files changed, 13 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.91 -> 1.92
SelectionDAGISel.cpp updated: 1.240 -> 1.241
---
Log message:
Move function-live-in-handling code from the sdisel code to the scheduler.
This code should be emitted after legalize, so it can't be in sdisel
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.90 -> 1.91
ScheduleDAGRRList.cpp updated: 1.3 -> 1.4
---
Log message:
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
---
Diffs of the changes: (+69 -15)
ScheduleDAG.cpp | 12
ScheduleDAGR
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.89 -> 1.90
ScheduleDAGList.cpp updated: 1.58 -> 1.59
ScheduleDAGRRList.cpp updated: 1.2 -> 1.3
ScheduleDAGSimple.cpp updated: 1.11 -> 1.12
---
Log message:
Refactor a bunch of includes so that TargetMachine.h doesn't
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.88 -> 1.89
---
Log message:
Duh. That could take a long time.
---
Diffs of the changes: (+15 -11)
ScheduleDAG.cpp | 26 +++---
1 files changed, 15 insertions(+), 11 deletions(-)
Index: llv
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.87 -> 1.88
ScheduleDAGRRList.cpp updated: 1.1 -> 1.2
---
Log message:
Add capability to scheduler to commute nodes for profit.
If a two-address code whose first operand has uses below, it should be commuted
when pos
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.85 -> 1.86
---
Log message:
Remove and simplify some more machineinstr/machineoperand stuff.
---
Diffs of the changes: (+1 -1)
ScheduleDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: l
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.84 -> 1.85
---
Log message:
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
---
Diffs of the changes: (+3 -3)
ScheduleDAG.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.83 -> 1.84
---
Log message:
Remove a bunch more SparcV9 specific stuff
---
Diffs of the changes: (+5 -5)
ScheduleDAG.cpp | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Code
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.80 -> 1.81
---
Log message:
fix spello
---
Diffs of the changes: (+1 -1)
ScheduleDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u l
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.79 -> 1.80
---
Log message:
TargetData doesn't know the alignment of vectors :(
---
Diffs of the changes: (+8 -1)
ScheduleDAG.cpp |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/l
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.78 -> 1.79
ScheduleDAGList.cpp updated: 1.40 -> 1.41
ScheduleDAGSimple.cpp updated: 1.8 -> 1.9
---
Log message:
Move some simple-sched-specific instance vars to the simple scheduler.
---
Diffs of the changes: (+30
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.77 -> 1.78
---
Log message:
prune #includes
---
Diffs of the changes: (+0 -5)
ScheduleDAG.cpp |5 -
1 files changed, 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.76 -> 1.77
ScheduleDAGSimple.cpp updated: 1.7 -> 1.8
---
Log message:
move some simple scheduler methods into the simple scheduler
---
Diffs of the changes: (+266 -235)
ScheduleDAG.cpp | 235 -
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.75 -> 1.76
ScheduleDAGList.cpp updated: 1.39 -> 1.40
---
Log message:
Make EmitNode take a SDNode instead of a NodeInfo*
---
Diffs of the changes: (+6 -12)
ScheduleDAG.cpp |7 +++
ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.74 -> 1.75
ScheduleDAGList.cpp updated: 1.38 -> 1.39
---
Log message:
Move the VRBase field from NodeInfo to being a separate, explicit, map.
---
Diffs of the changes: (+27 -13)
ScheduleDAG.cpp | 35 ++
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.73 -> 1.74
ScheduleDAGList.cpp updated: 1.35 -> 1.36
ScheduleDAGSimple.cpp updated: 1.6 -> 1.7
---
Log message:
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
---
Diffs of the changes: (+10 -4)
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.72 -> 1.73
ScheduleDAGList.cpp updated: 1.20 -> 1.21
SelectionDAGISel.cpp updated: 1.181 -> 1.182
---
Log message:
Change the interface for getting a target HazardRecognizer to be more clean.
---
Diffs of the chang
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.71 -> 1.72
ScheduleDAGList.cpp updated: 1.13 -> 1.14
---
Log message:
When a hazard recognizer needs noops to be inserted, do so. This represents
noops as null pointers in the instruction sequence.
---
Diffs of th
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.70 -> 1.71
SelectionDAG.cpp updated: 1.259 -> 1.260
---
Log message:
Added an offset field to ConstantPoolSDNode.
---
Diffs of the changes: (+14 -9)
ScheduleDAG.cpp |3 ++-
SelectionDAG.cpp | 20 ++
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.69 -> 1.70
---
Log message:
Pass all the flags to the asm printer, not just the # operands.
---
Diffs of the changes: (+1 -1)
ScheduleDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: ll
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.68 -> 1.69
---
Log message:
rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
Add support for addressing modes.
---
Diffs of the changes: (+11 -5)
ScheduleDAG.cpp | 16 +++---
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.67 -> 1.68
---
Log message:
Refactor operand adding out to a new AddOperand method
---
Diffs of the changes: (+81 -66)
ScheduleDAG.cpp | 147 ++--
1 files cha
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.66 -> 1.67
SelectionDAGISel.cpp updated: 1.168 -> 1.169
---
Log message:
Record all of the expanded registers in the DAG and machine instr, fixing
several bugs in inline asm expanded operands.
---
Diffs of the chan
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.65 -> 1.66
---
Log message:
Make MachineConstantPool entries alignments explicit
---
Diffs of the changes: (+12 -2)
ScheduleDAG.cpp | 14 --
1 files changed, 12 insertions(+), 2 deletions(-)
Inde
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.64 -> 1.65
---
Log message:
Fix VC++ warning.
---
Diffs of the changes: (+0 -1)
ScheduleDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/Cod
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.63 -> 1.64
SelectionDAGISel.cpp updated: 1.149 -> 1.150
---
Log message:
Get rid of some memory leaks identified by Valgrind
---
Diffs of the changes: (+9 -2)
ScheduleDAG.cpp | 10 --
SelectionDAGI
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.62 -> 1.63
SelectionDAGISel.cpp updated: 1.148 -> 1.149
---
Log message:
Add initial support for immediates. This allows us to compile this:
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.61 -> 1.62
SelectionDAG.cpp updated: 1.250 -> 1.251
---
Log message:
Allow the specification of explicit alignments for constant pool entries.
---
Diffs of the changes: (+16 -9)
ScheduleDAG.cpp |3 ++-
Sele
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.60 -> 1.61
SelectionDAGISel.cpp updated: 1.142 -> 1.143
---
Log message:
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = al
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.59 -> 1.60
---
Log message:
Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
ISD::INLINEASM node.
---
Diffs of the changes: (+29 -0)
ScheduleDAG.cpp | 29 +
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.58 -> 1.59
---
Log message:
No need to keep track of top and bottom nodes in a group since the vector is
already in order. Thanks Jim for pointing it out.
---
Diffs of the changes: (+0 -5)
ScheduleDAG.cpp |5
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.57 -> 1.58
---
Log message:
Keep track of bottom / top element of a set of flagged nodes.
---
Diffs of the changes: (+6 -1)
ScheduleDAG.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.56 -> 1.57
ScheduleDAGSimple.cpp updated: 1.1 -> 1.2
SelectionDAGISel.cpp updated: 1.132 -> 1.133
---
Log message:
Factor out more instruction scheduler code to the base class.
---
Diffs of the changes: (+306 -333
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.54 -> 1.55
---
Log message:
purity++
---
Diffs of the changes: (+1 -0)
ScheduleDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/S
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.52 -> 1.53
---
Log message:
Amend comment.
---
Diffs of the changes: (+2 -1)
ScheduleDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
dif
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.51 -> 1.52
---
Log message:
Create a strong dependency for loads following stores. This will leave a
latency period between the two.
---
Diffs of the changes: (+6 -2)
ScheduleDAG.cpp |8 ++--
1 files ch
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.50 -> 1.51
---
Log message:
Keep VC++ happy.
---
Diffs of the changes: (+1 -0)
ScheduleDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/Cod
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.49 -> 1.50
---
Log message:
Fix a bug Sabre was having where the DAG root was a group. The group dominator
needed to be added to the ordering list, not the first member of the group.
---
Diffs of the changes: (+6
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.48 -> 1.49
---
Log message:
Groups were not emitted if the dominator node and the node in the ordering list
were not the same node. Ultimately the test was bogus.
---
Diffs of the changes: (+6 -10)
ScheduleDAG
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.47 -> 1.48
---
Log message:
Simplify code
---
Diffs of the changes: (+2 -7)
ScheduleDAG.cpp |9 ++---
1 files changed, 2 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.c
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.46 -> 1.47
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+1 -1)
ScheduleDAG.cpp |2
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.45 -> 1.46
SelectionDAG.cpp updated: 1.216 -> 1.217
SelectionDAGPrinter.cpp updated: 1.29 -> 1.30
---
Log message:
Added an index field to GlobalAddressSDNode so it can represent X+12, etc.
---
Diffs of the changes
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.43 -> 1.44
---
Log message:
Explicitly initialize some instance vars
---
Diffs of the changes: (+5 -4)
ScheduleDAG.cpp |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.42 -> 1.43
---
Log message:
Let's try ignoring resource utilization on the backward pass.
---
Diffs of the changes: (+2 -0)
ScheduleDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/CodeGen/S
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.41 -> 1.42
---
Log message:
Fix logic bug in finding retry slot in tally.
---
Diffs of the changes: (+33 -15)
ScheduleDAG.cpp | 48 +---
1 files changed, 33 insertio
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.40 -> 1.41
---
Log message:
Fix a warning
---
Diffs of the changes: (+1 -0)
ScheduleDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGe
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.39 -> 1.40
---
Log message:
Scheduling now uses itinerary data.
---
Diffs of the changes: (+202 -167)
ScheduleDAG.cpp | 369 ++--
1 files changed, 202 insertio
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.38 -> 1.39
---
Log message:
1. Embed and not inherit vector for NodeGroup.
2. Iterate operands and not uses (performance.)
3. Some long pending comment changes.
---
Diffs of the changes: (+39 -20)
ScheduleDAG
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.37 -> 1.38
---
Log message:
Reduce the number of copies emitted as machine instructions by
generating results in vregs that will need them. In the case of something
like this: CopyToReg((add X, Y), reg1024), we no
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