Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.cpp updated: 1.14 -> 1.15 AlphaLLRP.cpp updated: 1.3 -> 1.4 AlphaRegisterInfo.cpp updated: 1.52 -> 1.53 AlphaRegisterInfo.h updated: 1.14 -> 1.15 --- Log message: Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead of opcode and number of operands. --- Diffs of the changes: (+46 -41) AlphaInstrInfo.cpp | 14 ++++++------ AlphaLLRP.cpp | 17 +++++++++------ AlphaRegisterInfo.cpp | 55 +++++++++++++++++++++++++------------------------- AlphaRegisterInfo.h | 1 4 files changed, 46 insertions(+), 41 deletions(-) Index: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.14 llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.15 --- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.14 Mon Nov 13 17:36:35 2006 +++ llvm/lib/Target/Alpha/AlphaInstrInfo.cpp Mon Nov 27 17:37:22 2006 @@ -110,25 +110,25 @@ // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB); + BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB); else // Conditional branch if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, Alpha::COND_BRANCH_I, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, Alpha::COND_BRANCH_F, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return; } // Two-way Conditional Branch. if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, Alpha::COND_BRANCH_I, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, Alpha::COND_BRANCH_F, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, Alpha::BR, 1).addMBB(FBB); + BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB); } static unsigned AlphaRevCondCode(unsigned Opcode) { @@ -230,7 +230,7 @@ void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); } Index: llvm/lib/Target/Alpha/AlphaLLRP.cpp diff -u llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.3 llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.4 --- llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.3 Tue Oct 31 17:46:56 2006 +++ llvm/lib/Target/Alpha/AlphaLLRP.cpp Mon Nov 27 17:37:22 2006 @@ -15,6 +15,8 @@ #include "Alpha.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/ADT/SetOperations.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/CommandLine.h" @@ -42,6 +44,7 @@ } bool runOnMachineFunction(MachineFunction &F) { + const TargetInstrInfo *TII = F.getTarget().getInstrInfo(); bool Changed = false; MachineInstr* prev[3] = {0,0,0}; unsigned count = 0; @@ -70,7 +73,7 @@ prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; count += 1; @@ -81,9 +84,9 @@ MI->getOperand(1).getImmedValue()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; count += 2; @@ -93,11 +96,11 @@ && prev[2]->getOperand(1).getImmedValue() == MI->getOperand(1).getImmedValue()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; @@ -130,7 +133,7 @@ if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31) + BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign; Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.52 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.53 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.52 Wed Nov 15 14:58:11 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon Nov 27 17:37:22 2006 @@ -25,6 +25,7 @@ #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/ADT/STLExtras.h" @@ -66,13 +67,13 @@ //<< FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, Alpha::STS, 3) + BuildMI(MBB, MI, TII.get(Alpha::STS)) .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, Alpha::STT, 3) + BuildMI(MBB, MI, TII.get(Alpha::STT)) .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, Alpha::STQ, 3) + BuildMI(MBB, MI, TII.get(Alpha::STQ)) .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); @@ -86,13 +87,13 @@ //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " //<< FrameIdx << "\n"; if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, Alpha::LDS, 2, DestReg) + BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, Alpha::LDT, 2, DestReg) + BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg) + BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); @@ -116,13 +117,13 @@ unsigned InReg = MI->getOperand(1).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) + NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move unsigned OutReg = MI->getOperand(0).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - NewMI = BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex) + NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } } @@ -140,11 +141,11 @@ const TargetRegisterClass *RC) const { // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; if (RC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, Alpha::BISr, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (RC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); } else if (RC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); } else { std::cerr << "Attempt to copy register that is not GPR or FPR"; abort(); @@ -209,11 +210,11 @@ MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30) + New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30) + New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -270,7 +271,7 @@ MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28) + MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { @@ -288,15 +289,15 @@ static int curgpdist = 0; //handle GOP offset - BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29) + BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29) .addGlobalAddress(const_cast<Function*>(MF.getFunction())) .addReg(Alpha::R27).addImm(++curgpdist); - BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29) + BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29) .addGlobalAddress(const_cast<Function*>(MF.getFunction())) .addReg(Alpha::R29).addImm(curgpdist); //evil const_cast until MO stuff setup to handle const - BuildMI(MBB, MBBI, Alpha::ALTENT, 1) + BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT)) .addGlobalAddress(const_cast<Function*>(MF.getFunction())); // Get the number of bytes to allocate from the FrameInfo @@ -327,12 +328,12 @@ // adjust stack pointer: r30 -= numbytes NumBytes = -NumBytes; if (NumBytes >= IMM_LOW) { - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) >= IMM_LOW) { - BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes)) + BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes)) .addReg(Alpha::R30); - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes)) + BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes)) .addReg(Alpha::R30); } else { std::cerr << "Too big a stack frame at " << NumBytes << "\n"; @@ -342,10 +343,10 @@ //now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, Alpha::STQ, 3) + BuildMI(MBB, MBBI, TII.get(Alpha::STQ)) .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); //this must be the last instr in the prolog - BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R15) + BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15) .addReg(Alpha::R30).addReg(Alpha::R30); } @@ -368,21 +369,21 @@ if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R30).addReg(Alpha::R15) + BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) .addReg(Alpha::R15); //restore the FP - BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15); + BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15); } if (NumBytes != 0) { if (NumBytes <= IMM_HIGH) { - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) <= IMM_HIGH) { - BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30) + BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30) .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30) + BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30) .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { std::cerr << "Too big a stack frame at " << NumBytes << "\n"; Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.14 llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.15 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.14 Mon Nov 13 17:36:35 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h Mon Nov 27 17:37:22 2006 @@ -19,6 +19,7 @@ namespace llvm { +class TargetInstrInfo; class Type; struct AlphaRegisterInfo : public AlphaGenRegisterInfo { _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits