Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.178 -> 1.179 PPCInstr64Bit.td updated: 1.9 -> 1.10 PPCInstrFormats.td updated: 1.75 -> 1.76 PPCInstrInfo.cpp updated: 1.21 -> 1.22 PPCInstrInfo.td updated: 1.230 -> 1.231 PPCRegisterInfo.cpp updated: 1.69 -> 1.70 --- Log message: Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file --- Diffs of the changes: (+28 -28) PPCAsmPrinter.cpp | 2 +- PPCInstr64Bit.td | 33 ++++++++++++++++++++++----------- PPCInstrFormats.td | 1 - PPCInstrInfo.cpp | 2 +- PPCInstrInfo.td | 12 +----------- PPCRegisterInfo.cpp | 6 +++--- 6 files changed, 28 insertions(+), 28 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.178 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.179 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.178 Thu Jun 15 15:51:43 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Jun 20 18:18:58 2006 @@ -465,7 +465,7 @@ O << ", " << (unsigned int)SH << "\n"; return; } - } else if (MI->getOpcode() == PPC::OR4 || MI->getOpcode() == PPC::OR8) { + } else if (MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) { if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { O << "mr "; printOperand(MI, 0); Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.9 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.10 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.9 Tue Jun 20 18:11:59 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td Tue Jun 20 18:18:58 2006 @@ -22,7 +22,29 @@ let PrintMethod = "printSymbolLo"; } +//===----------------------------------------------------------------------===// +// 64-bit transformation functions. +// + +def SHL64 : SDNodeXForm<imm, [{ + // Transformation function: 63 - imm + return getI32Imm(63 - N->getValue()); +}]>; +def SRL64 : SDNodeXForm<imm, [{ + // Transformation function: 64 - imm + return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0); +}]>; + +def HI32_48 : SDNodeXForm<imm, [{ + // Transformation function: shift the immediate value down into the low bits. + return getI32Imm((unsigned short)(N->getValue() >> 32)); +}]>; + +def HI48_64 : SDNodeXForm<imm, [{ + // Transformation function: shift the immediate value down into the low bits. + return getI32Imm((unsigned short)(N->getValue() >> 48)); +}]>; //===----------------------------------------------------------------------===// @@ -238,17 +260,6 @@ // Instruction Patterns // -def HI32_48 : SDNodeXForm<imm, [{ - // Transformation function: shift the immediate value down into the low bits. - return getI32Imm((unsigned short)(N->getValue() >> 32)); -}]>; - -def HI48_64 : SDNodeXForm<imm, [{ - // Transformation function: shift the immediate value down into the low bits. - return getI32Imm((unsigned short)(N->getValue() >> 48)); -}]>; - - // Immediate support. // Handled above: // sext(0x0000_0000_0000_FFFF, i8) -> li imm Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.75 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.76 --- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.75 Tue Jun 20 18:15:07 2006 +++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Jun 20 18:18:58 2006 @@ -785,7 +785,6 @@ class Pseudo<dag OL, string asmstr, list<dag> pattern> : I<0, OL, asmstr, NoItinerary> { let PPC64 = 0; - let VMX = 0; let Pattern = pattern; let Inst{31-0} = 0; } Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.21 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.22 --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.21 Fri Jun 16 19:01:04 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Jun 20 18:18:58 2006 @@ -35,7 +35,7 @@ unsigned& sourceReg, unsigned& destReg) const { MachineOpCode oc = MI.getOpcode(); - if (oc == PPC::OR4 || oc == PPC::OR8 || oc == PPC::VOR || + if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.230 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.231 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.230 Tue Jun 20 18:15:07 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Jun 20 18:18:58 2006 @@ -97,21 +97,11 @@ return getI32Imm(31 - N->getValue()); }]>; -def SHL64 : SDNodeXForm<imm, [{ - // Transformation function: 63 - imm - return getI32Imm(63 - N->getValue()); -}]>; - def SRL32 : SDNodeXForm<imm, [{ // Transformation function: 32 - imm return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0); }]>; -def SRL64 : SDNodeXForm<imm, [{ - // Transformation function: 64 - imm - return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0); -}]>; - def LO16 : SDNodeXForm<imm, [{ // Transformation function: get the low 16 bits. return getI32Imm((unsigned short)N->getValue()); @@ -485,7 +475,7 @@ def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), "andc $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; -def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), "or $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.69 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.70 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.69 Mon Jun 12 18:59:16 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jun 20 18:18:58 2006 @@ -189,7 +189,7 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { if (RC == PPC::GPRCRegisterClass) { - BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); } else if (RC == PPC::G8RCRegisterClass) { BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); } else if (RC == PPC::F4RCRegisterClass) { @@ -282,7 +282,7 @@ // it takes more than one instruction to store it. unsigned Opc = MI->getOpcode(); - if ((Opc == PPC::OR4 && + if ((Opc == PPC::OR && MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); @@ -631,7 +631,7 @@ if (HasFP) { BuildMI(MBB, MBBI, PPC::STW, 3) .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1); - BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); + BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); } } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits