To GNU as, register classes are determined by context. This patch
changes the asm printed to print just the register number alone on
non-Darwin platforms.
The "getRegisterPrefix" function might be a little too magical. I'd be
happy to hear any suggestions.
Nick Lewycky
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp,v
retrieving revision 1.221
diff -u -r1.221 PPCAsmPrinter.cpp
--- lib/Target/PowerPC/PPCAsmPrinter.cpp 12 Dec 2006 20:57:08 -0000 1.221
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp 18 Dec 2006 00:36:48 -0000
@@ -90,10 +90,19 @@
void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO);
+ static std::string getRegisterPrefix(unsigned regno) {
+ if (regno > 76) return "v";
+ if (regno > 67) return "cr";
+ if (regno > 31) return "f";
+ return "r";
+ }
+
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isRegister()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
+ if (Subtarget.isDarwin())
+ O << getRegisterPrefix(MO.getReg());
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
O << MO.getImmedValue();
Index: lib/Target/PowerPC/PPCRegisterInfo.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/PowerPC/PPCRegisterInfo.td,v
retrieving revision 1.42
diff -u -r1.42 PPCRegisterInfo.td
--- lib/Target/PowerPC/PPCRegisterInfo.td 20 Nov 2006 20:48:05 -0000 1.42
+++ lib/Target/PowerPC/PPCRegisterInfo.td 18 Dec 2006 00:36:49 -0000
@@ -48,38 +48,38 @@
}
// General-purpose registers
-def R0 : GPR< 0, "r0">, DwarfRegNum<0>;
-def R1 : GPR< 1, "r1">, DwarfRegNum<1>;
-def R2 : GPR< 2, "r2">, DwarfRegNum<2>;
-def R3 : GPR< 3, "r3">, DwarfRegNum<3>;
-def R4 : GPR< 4, "r4">, DwarfRegNum<4>;
-def R5 : GPR< 5, "r5">, DwarfRegNum<5>;
-def R6 : GPR< 6, "r6">, DwarfRegNum<6>;
-def R7 : GPR< 7, "r7">, DwarfRegNum<7>;
-def R8 : GPR< 8, "r8">, DwarfRegNum<8>;
-def R9 : GPR< 9, "r9">, DwarfRegNum<9>;
-def R10 : GPR<10, "r10">, DwarfRegNum<10>;
-def R11 : GPR<11, "r11">, DwarfRegNum<11>;
-def R12 : GPR<12, "r12">, DwarfRegNum<12>;
-def R13 : GPR<13, "r13">, DwarfRegNum<13>;
-def R14 : GPR<14, "r14">, DwarfRegNum<14>;
-def R15 : GPR<15, "r15">, DwarfRegNum<15>;
-def R16 : GPR<16, "r16">, DwarfRegNum<16>;
-def R17 : GPR<17, "r17">, DwarfRegNum<17>;
-def R18 : GPR<18, "r18">, DwarfRegNum<18>;
-def R19 : GPR<19, "r19">, DwarfRegNum<19>;
-def R20 : GPR<20, "r20">, DwarfRegNum<20>;
-def R21 : GPR<21, "r21">, DwarfRegNum<21>;
-def R22 : GPR<22, "r22">, DwarfRegNum<22>;
-def R23 : GPR<23, "r23">, DwarfRegNum<23>;
-def R24 : GPR<24, "r24">, DwarfRegNum<24>;
-def R25 : GPR<25, "r25">, DwarfRegNum<25>;
-def R26 : GPR<26, "r26">, DwarfRegNum<26>;
-def R27 : GPR<27, "r27">, DwarfRegNum<27>;
-def R28 : GPR<28, "r28">, DwarfRegNum<28>;
-def R29 : GPR<29, "r29">, DwarfRegNum<29>;
-def R30 : GPR<30, "r30">, DwarfRegNum<30>;
-def R31 : GPR<31, "r31">, DwarfRegNum<31>;
+def R0 : GPR< 0, "0">, DwarfRegNum<0>;
+def R1 : GPR< 1, "1">, DwarfRegNum<1>;
+def R2 : GPR< 2, "2">, DwarfRegNum<2>;
+def R3 : GPR< 3, "3">, DwarfRegNum<3>;
+def R4 : GPR< 4, "4">, DwarfRegNum<4>;
+def R5 : GPR< 5, "5">, DwarfRegNum<5>;
+def R6 : GPR< 6, "6">, DwarfRegNum<6>;
+def R7 : GPR< 7, "7">, DwarfRegNum<7>;
+def R8 : GPR< 8, "8">, DwarfRegNum<8>;
+def R9 : GPR< 9, "9">, DwarfRegNum<9>;
+def R10 : GPR<10, "10">, DwarfRegNum<10>;
+def R11 : GPR<11, "11">, DwarfRegNum<11>;
+def R12 : GPR<12, "12">, DwarfRegNum<12>;
+def R13 : GPR<13, "13">, DwarfRegNum<13>;
+def R14 : GPR<14, "14">, DwarfRegNum<14>;
+def R15 : GPR<15, "15">, DwarfRegNum<15>;
+def R16 : GPR<16, "16">, DwarfRegNum<16>;
+def R17 : GPR<17, "17">, DwarfRegNum<17>;
+def R18 : GPR<18, "18">, DwarfRegNum<18>;
+def R19 : GPR<19, "19">, DwarfRegNum<19>;
+def R20 : GPR<20, "20">, DwarfRegNum<20>;
+def R21 : GPR<21, "21">, DwarfRegNum<21>;
+def R22 : GPR<22, "22">, DwarfRegNum<22>;
+def R23 : GPR<23, "23">, DwarfRegNum<23>;
+def R24 : GPR<24, "24">, DwarfRegNum<24>;
+def R25 : GPR<25, "25">, DwarfRegNum<25>;
+def R26 : GPR<26, "26">, DwarfRegNum<26>;
+def R27 : GPR<27, "27">, DwarfRegNum<27>;
+def R28 : GPR<28, "28">, DwarfRegNum<28>;
+def R29 : GPR<29, "29">, DwarfRegNum<29>;
+def R30 : GPR<30, "30">, DwarfRegNum<30>;
+def R31 : GPR<31, "31">, DwarfRegNum<31>;
// 64-bit General-purpose registers
def X0 : GP8< R0>, DwarfRegNum<0>;
@@ -116,82 +116,82 @@
def X31 : GP8<R31>, DwarfRegNum<31>;
// Floating-point registers
-def F0 : FPR< 0, "f0">, DwarfRegNum<32>;
-def F1 : FPR< 1, "f1">, DwarfRegNum<33>;
-def F2 : FPR< 2, "f2">, DwarfRegNum<34>;
-def F3 : FPR< 3, "f3">, DwarfRegNum<35>;
-def F4 : FPR< 4, "f4">, DwarfRegNum<36>;
-def F5 : FPR< 5, "f5">, DwarfRegNum<37>;
-def F6 : FPR< 6, "f6">, DwarfRegNum<38>;
-def F7 : FPR< 7, "f7">, DwarfRegNum<39>;
-def F8 : FPR< 8, "f8">, DwarfRegNum<40>;
-def F9 : FPR< 9, "f9">, DwarfRegNum<41>;
-def F10 : FPR<10, "f10">, DwarfRegNum<42>;
-def F11 : FPR<11, "f11">, DwarfRegNum<43>;
-def F12 : FPR<12, "f12">, DwarfRegNum<44>;
-def F13 : FPR<13, "f13">, DwarfRegNum<45>;
-def F14 : FPR<14, "f14">, DwarfRegNum<46>;
-def F15 : FPR<15, "f15">, DwarfRegNum<47>;
-def F16 : FPR<16, "f16">, DwarfRegNum<48>;
-def F17 : FPR<17, "f17">, DwarfRegNum<49>;
-def F18 : FPR<18, "f18">, DwarfRegNum<50>;
-def F19 : FPR<19, "f19">, DwarfRegNum<51>;
-def F20 : FPR<20, "f20">, DwarfRegNum<52>;
-def F21 : FPR<21, "f21">, DwarfRegNum<53>;
-def F22 : FPR<22, "f22">, DwarfRegNum<54>;
-def F23 : FPR<23, "f23">, DwarfRegNum<55>;
-def F24 : FPR<24, "f24">, DwarfRegNum<56>;
-def F25 : FPR<25, "f25">, DwarfRegNum<57>;
-def F26 : FPR<26, "f26">, DwarfRegNum<58>;
-def F27 : FPR<27, "f27">, DwarfRegNum<59>;
-def F28 : FPR<28, "f28">, DwarfRegNum<60>;
-def F29 : FPR<29, "f29">, DwarfRegNum<61>;
-def F30 : FPR<30, "f30">, DwarfRegNum<62>;
-def F31 : FPR<31, "f31">, DwarfRegNum<63>;
+def F0 : FPR< 0, "0">, DwarfRegNum<32>;
+def F1 : FPR< 1, "1">, DwarfRegNum<33>;
+def F2 : FPR< 2, "2">, DwarfRegNum<34>;
+def F3 : FPR< 3, "3">, DwarfRegNum<35>;
+def F4 : FPR< 4, "4">, DwarfRegNum<36>;
+def F5 : FPR< 5, "5">, DwarfRegNum<37>;
+def F6 : FPR< 6, "6">, DwarfRegNum<38>;
+def F7 : FPR< 7, "7">, DwarfRegNum<39>;
+def F8 : FPR< 8, "8">, DwarfRegNum<40>;
+def F9 : FPR< 9, "9">, DwarfRegNum<41>;
+def F10 : FPR<10, "10">, DwarfRegNum<42>;
+def F11 : FPR<11, "11">, DwarfRegNum<43>;
+def F12 : FPR<12, "12">, DwarfRegNum<44>;
+def F13 : FPR<13, "13">, DwarfRegNum<45>;
+def F14 : FPR<14, "14">, DwarfRegNum<46>;
+def F15 : FPR<15, "15">, DwarfRegNum<47>;
+def F16 : FPR<16, "16">, DwarfRegNum<48>;
+def F17 : FPR<17, "17">, DwarfRegNum<49>;
+def F18 : FPR<18, "18">, DwarfRegNum<50>;
+def F19 : FPR<19, "19">, DwarfRegNum<51>;
+def F20 : FPR<20, "20">, DwarfRegNum<52>;
+def F21 : FPR<21, "21">, DwarfRegNum<53>;
+def F22 : FPR<22, "22">, DwarfRegNum<54>;
+def F23 : FPR<23, "23">, DwarfRegNum<55>;
+def F24 : FPR<24, "24">, DwarfRegNum<56>;
+def F25 : FPR<25, "25">, DwarfRegNum<57>;
+def F26 : FPR<26, "26">, DwarfRegNum<58>;
+def F27 : FPR<27, "27">, DwarfRegNum<59>;
+def F28 : FPR<28, "28">, DwarfRegNum<60>;
+def F29 : FPR<29, "29">, DwarfRegNum<61>;
+def F30 : FPR<30, "30">, DwarfRegNum<62>;
+def F31 : FPR<31, "31">, DwarfRegNum<63>;
// Vector registers
-def V0 : VR< 0, "v0">, DwarfRegNum<77>;
-def V1 : VR< 1, "v1">, DwarfRegNum<78>;
-def V2 : VR< 2, "v2">, DwarfRegNum<79>;
-def V3 : VR< 3, "v3">, DwarfRegNum<80>;
-def V4 : VR< 4, "v4">, DwarfRegNum<81>;
-def V5 : VR< 5, "v5">, DwarfRegNum<82>;
-def V6 : VR< 6, "v6">, DwarfRegNum<83>;
-def V7 : VR< 7, "v7">, DwarfRegNum<84>;
-def V8 : VR< 8, "v8">, DwarfRegNum<85>;
-def V9 : VR< 9, "v9">, DwarfRegNum<86>;
-def V10 : VR<10, "v10">, DwarfRegNum<87>;
-def V11 : VR<11, "v11">, DwarfRegNum<88>;
-def V12 : VR<12, "v12">, DwarfRegNum<89>;
-def V13 : VR<13, "v13">, DwarfRegNum<90>;
-def V14 : VR<14, "v14">, DwarfRegNum<91>;
-def V15 : VR<15, "v15">, DwarfRegNum<92>;
-def V16 : VR<16, "v16">, DwarfRegNum<93>;
-def V17 : VR<17, "v17">, DwarfRegNum<94>;
-def V18 : VR<18, "v18">, DwarfRegNum<95>;
-def V19 : VR<19, "v19">, DwarfRegNum<96>;
-def V20 : VR<20, "v20">, DwarfRegNum<97>;
-def V21 : VR<21, "v21">, DwarfRegNum<98>;
-def V22 : VR<22, "v22">, DwarfRegNum<99>;
-def V23 : VR<23, "v23">, DwarfRegNum<100>;
-def V24 : VR<24, "v24">, DwarfRegNum<101>;
-def V25 : VR<25, "v25">, DwarfRegNum<102>;
-def V26 : VR<26, "v26">, DwarfRegNum<103>;
-def V27 : VR<27, "v27">, DwarfRegNum<104>;
-def V28 : VR<28, "v28">, DwarfRegNum<105>;
-def V29 : VR<29, "v29">, DwarfRegNum<106>;
-def V30 : VR<30, "v30">, DwarfRegNum<107>;
-def V31 : VR<31, "v31">, DwarfRegNum<108>;
+def V0 : VR< 0, "0">, DwarfRegNum<77>;
+def V1 : VR< 1, "1">, DwarfRegNum<78>;
+def V2 : VR< 2, "2">, DwarfRegNum<79>;
+def V3 : VR< 3, "3">, DwarfRegNum<80>;
+def V4 : VR< 4, "4">, DwarfRegNum<81>;
+def V5 : VR< 5, "5">, DwarfRegNum<82>;
+def V6 : VR< 6, "6">, DwarfRegNum<83>;
+def V7 : VR< 7, "7">, DwarfRegNum<84>;
+def V8 : VR< 8, "8">, DwarfRegNum<85>;
+def V9 : VR< 9, "9">, DwarfRegNum<86>;
+def V10 : VR<10, "10">, DwarfRegNum<87>;
+def V11 : VR<11, "11">, DwarfRegNum<88>;
+def V12 : VR<12, "12">, DwarfRegNum<89>;
+def V13 : VR<13, "13">, DwarfRegNum<90>;
+def V14 : VR<14, "14">, DwarfRegNum<91>;
+def V15 : VR<15, "15">, DwarfRegNum<92>;
+def V16 : VR<16, "16">, DwarfRegNum<93>;
+def V17 : VR<17, "17">, DwarfRegNum<94>;
+def V18 : VR<18, "18">, DwarfRegNum<95>;
+def V19 : VR<19, "19">, DwarfRegNum<96>;
+def V20 : VR<20, "20">, DwarfRegNum<97>;
+def V21 : VR<21, "21">, DwarfRegNum<98>;
+def V22 : VR<22, "22">, DwarfRegNum<99>;
+def V23 : VR<23, "23">, DwarfRegNum<100>;
+def V24 : VR<24, "24">, DwarfRegNum<101>;
+def V25 : VR<25, "25">, DwarfRegNum<102>;
+def V26 : VR<26, "26">, DwarfRegNum<103>;
+def V27 : VR<27, "27">, DwarfRegNum<104>;
+def V28 : VR<28, "28">, DwarfRegNum<105>;
+def V29 : VR<29, "29">, DwarfRegNum<106>;
+def V30 : VR<30, "30">, DwarfRegNum<107>;
+def V31 : VR<31, "31">, DwarfRegNum<108>;
// Condition registers
-def CR0 : CR<0, "cr0">, DwarfRegNum<68>;
-def CR1 : CR<1, "cr1">, DwarfRegNum<69>;
-def CR2 : CR<2, "cr2">, DwarfRegNum<70>;
-def CR3 : CR<3, "cr3">, DwarfRegNum<71>;
-def CR4 : CR<4, "cr4">, DwarfRegNum<72>;
-def CR5 : CR<5, "cr5">, DwarfRegNum<73>;
-def CR6 : CR<6, "cr6">, DwarfRegNum<74>;
-def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
+def CR0 : CR<0, "0">, DwarfRegNum<68>;
+def CR1 : CR<1, "1">, DwarfRegNum<69>;
+def CR2 : CR<2, "2">, DwarfRegNum<70>;
+def CR3 : CR<3, "3">, DwarfRegNum<71>;
+def CR4 : CR<4, "4">, DwarfRegNum<72>;
+def CR5 : CR<5, "5">, DwarfRegNum<73>;
+def CR6 : CR<6, "6">, DwarfRegNum<74>;
+def CR7 : CR<7, "7">, DwarfRegNum<75>;
// Link register
def LR : SPR<8, "lr">, DwarfRegNum<65>;
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