Module: Mesa
Branch: master
Commit: f187a493225e33c5ce514c731a0a140d61dacb0b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f187a493225e33c5ce514c731a0a140d61dacb0b
Author: Nicolai Hähnle <nicolai.haeh...@amd.com>
Date: Wed May 10 17:35:25 2017 +0200
ac/radeonsi: move amdgpu_addr_create to ac_surface
v2:
- update Android.common.mk (Emil)
- rebase on top of Raven support
Reviewed-by: Marek Olšák <marek.ol...@amd.com> (v1)
---
src/amd/Android.common.mk | 1 +
src/amd/Makefile.common.am | 2 +
src/amd/Makefile.sources | 4 +
src/amd/common/ac_surface.c | 202 +++++++++++++++++++++++++
src/amd/common/ac_surface.h | 10 ++
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 74 ---------
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 89 +----------
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 3 -
8 files changed, 220 insertions(+), 165 deletions(-)
diff --git a/src/amd/Android.common.mk b/src/amd/Android.common.mk
index 62d4df1511..3eb9618bb9 100644
--- a/src/amd/Android.common.mk
+++ b/src/amd/Android.common.mk
@@ -30,6 +30,7 @@ LOCAL_MODULE := libmesa_amd_common
LOCAL_SRC_FILES := \
$(AMD_COMPILER_FILES) \
+ $(AMD_SURFACE_FILES) \
$(AMD_DEBUG_FILES)
LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU # instructs LLVM to declare
LLVMInitializeAMDGPU* functions
diff --git a/src/amd/Makefile.common.am b/src/amd/Makefile.common.am
index 83f148b805..21d56f19ba 100644
--- a/src/amd/Makefile.common.am
+++ b/src/amd/Makefile.common.am
@@ -25,6 +25,7 @@ COMMON_LIBS = common/libamd_common.la
# TODO cleanup these
common_libamd_common_la_CPPFLAGS = \
+ $(AMDGPU_CFLAGS) \
$(VALGRIND_CFLAGS) \
$(DEFINES) \
-I$(top_srcdir)/include \
@@ -55,6 +56,7 @@ noinst_LTLIBRARIES += $(COMMON_LIBS)
common_libamd_common_la_SOURCES = \
$(AMD_COMPILER_FILES) \
+ $(AMD_SURFACE_FILES) \
$(AMD_DEBUG_FILES) \
$(AMD_GENERATED_FILES)
diff --git a/src/amd/Makefile.sources b/src/amd/Makefile.sources
index 3673cf40dd..a7ce3fcf02 100644
--- a/src/amd/Makefile.sources
+++ b/src/amd/Makefile.sources
@@ -55,6 +55,10 @@ AMD_NIR_FILES = \
common/ac_nir_to_llvm.c \
common/ac_nir_to_llvm.h
+AMD_SURFACE_FILES = \
+ common/ac_surface.c \
+ common/ac_surface.h
+
AMD_DEBUG_FILES = \
common/ac_debug.c \
common/ac_debug.h
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
new file mode 100644
index 0000000000..6cfa99625e
--- /dev/null
+++ b/src/amd/common/ac_surface.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright © 2011 Red Hat All Rights Reserved.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+
+#include "ac_surface.h"
+#include "amdgpu_id.h"
+#include "util/macros.h"
+#include "util/u_math.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <amdgpu.h>
+
+#include "addrlib/addrinterface.h"
+
+#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
+#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
+#endif
+
+#ifndef CIASICIDGFXENGINE_ARCTICISLAND
+#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
+#endif
+
+static void addrlib_family_rev_id(enum radeon_family family,
+ unsigned *addrlib_family,
+ unsigned *addrlib_revid)
+{
+ switch (family) {
+ case CHIP_TAHITI:
+ *addrlib_family = FAMILY_SI;
+ *addrlib_revid = SI_TAHITI_P_A0;
+ break;
+ case CHIP_PITCAIRN:
+ *addrlib_family = FAMILY_SI;
+ *addrlib_revid = SI_PITCAIRN_PM_A0;
+ break;
+ case CHIP_VERDE:
+ *addrlib_family = FAMILY_SI;
+ *addrlib_revid = SI_CAPEVERDE_M_A0;
+ break;
+ case CHIP_OLAND:
+ *addrlib_family = FAMILY_SI;
+ *addrlib_revid = SI_OLAND_M_A0;
+ break;
+ case CHIP_HAINAN:
+ *addrlib_family = FAMILY_SI;
+ *addrlib_revid = SI_HAINAN_V_A0;
+ break;
+ case CHIP_BONAIRE:
+ *addrlib_family = FAMILY_CI;
+ *addrlib_revid = CI_BONAIRE_M_A0;
+ break;
+ case CHIP_KAVERI:
+ *addrlib_family = FAMILY_KV;
+ *addrlib_revid = KV_SPECTRE_A0;
+ break;
+ case CHIP_KABINI:
+ *addrlib_family = FAMILY_KV;
+ *addrlib_revid = KB_KALINDI_A0;
+ break;
+ case CHIP_HAWAII:
+ *addrlib_family = FAMILY_CI;
+ *addrlib_revid = CI_HAWAII_P_A0;
+ break;
+ case CHIP_MULLINS:
+ *addrlib_family = FAMILY_KV;
+ *addrlib_revid = ML_GODAVARI_A0;
+ break;
+ case CHIP_TONGA:
+ *addrlib_family = FAMILY_VI;
+ *addrlib_revid = VI_TONGA_P_A0;
+ break;
+ case CHIP_ICELAND:
+ *addrlib_family = FAMILY_VI;
+ *addrlib_revid = VI_ICELAND_M_A0;
+ break;
+ case CHIP_CARRIZO:
+ *addrlib_family = FAMILY_CZ;
+ *addrlib_revid = CARRIZO_A0;
+ break;
+ case CHIP_STONEY:
+ *addrlib_family = FAMILY_CZ;
+ *addrlib_revid = STONEY_A0;
+ break;
+ case CHIP_FIJI:
+ *addrlib_family = FAMILY_VI;
+ *addrlib_revid = VI_FIJI_P_A0;
+ break;
+ case CHIP_POLARIS10:
+ *addrlib_family = FAMILY_VI;
+ *addrlib_revid = VI_POLARIS10_P_A0;
+ break;
+ case CHIP_POLARIS11:
+ *addrlib_family = FAMILY_VI;
+ *addrlib_revid = VI_POLARIS11_M_A0;
+ break;
+ case CHIP_POLARIS12:
+ *addrlib_family = FAMILY_VI;
+ *addrlib_revid = VI_POLARIS12_V_A0;
+ break;
+ case CHIP_VEGA10:
+ *addrlib_family = FAMILY_AI;
+ *addrlib_revid = AI_VEGA10_P_A0;
+ break;
+ case CHIP_RAVEN:
+ *addrlib_family = FAMILY_RV;
+ *addrlib_revid = RAVEN_A0;
+ break;
+ default:
+ fprintf(stderr, "amdgpu: Unknown family.\n");
+ }
+}
+
+static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
+{
+ return malloc(pInput->sizeInBytes);
+}
+
+static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT *
pInput)
+{
+ free(pInput->pVirtAddr);
+ return ADDR_OK;
+}
+
+ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
+ const struct amdgpu_gpu_info *info)
+{
+ ADDR_CREATE_INPUT addrCreateInput = {0};
+ ADDR_CREATE_OUTPUT addrCreateOutput = {0};
+ ADDR_REGISTER_VALUE regValue = {0};
+ ADDR_CREATE_FLAGS createFlags = {{0}};
+ ADDR_E_RETURNCODE addrRet;
+
+ addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
+ addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
+
+ regValue.gbAddrConfig = info->gb_addr_cfg;
+ createFlags.value = 0;
+
+ addrlib_family_rev_id(family, &addrCreateInput.chipFamily,
&addrCreateInput.chipRevision);
+ if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
+ return NULL;
+
+ if (addrCreateInput.chipFamily >= FAMILY_AI) {
+ addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
+ regValue.blockVarSizeLog2 = 0;
+ } else {
+ regValue.noOfBanks = info->mc_arb_ramcfg & 0x3;
+ regValue.noOfRanks = (info->mc_arb_ramcfg & 0x4) >> 2;
+
+ regValue.backendDisables = info->enabled_rb_pipes_mask;
+ regValue.pTileConfig = info->gb_tile_mode;
+ regValue.noOfEntries = ARRAY_SIZE(info->gb_tile_mode);
+ if (addrCreateInput.chipFamily == FAMILY_SI) {
+ regValue.pMacroTileConfig = NULL;
+ regValue.noOfMacroEntries = 0;
+ } else {
+ regValue.pMacroTileConfig = info->gb_macro_tile_mode;
+ regValue.noOfMacroEntries =
ARRAY_SIZE(info->gb_macro_tile_mode);
+ }
+
+ createFlags.useTileIndex = 1;
+ createFlags.useHtileSliceAlign = 1;
+
+ addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
+ }
+
+ addrCreateInput.callbacks.allocSysMem = allocSysMem;
+ addrCreateInput.callbacks.freeSysMem = freeSysMem;
+ addrCreateInput.callbacks.debugPrint = 0;
+ addrCreateInput.createFlags = createFlags;
+ addrCreateInput.regValue = regValue;
+
+ addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
+ if (addrRet != ADDR_OK)
+ return NULL;
+
+ return addrCreateOutput.hLib;
+}
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 37beb8cc70..d648e88ae2 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -28,6 +28,13 @@
#include <stdint.h>
+#include "amd_family.h"
+
+/* Forward declarations. */
+typedef void* ADDR_HANDLE;
+
+struct amdgpu_gpu_info;
+
#define RADEON_SURF_MAX_LEVELS 15
enum radeon_surf_mode {
@@ -175,4 +182,7 @@ struct radeon_surf {
} u;
};
+ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
+ const struct amdgpu_gpu_info *info);
+
#endif /* AC_SURFACE_H */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 4d532e397d..7480a432af 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -32,14 +32,6 @@
#include "amdgpu_winsys.h"
#include "util/u_format.h"
-#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
-#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
-#endif
-
-#ifndef CIASICIDGFXENGINE_ARCTICISLAND
-#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
-#endif
-
static int amdgpu_surface_sanity(const struct pipe_resource *tex)
{
/* all dimension must be at least 1 ! */
@@ -88,72 +80,6 @@ static int amdgpu_surface_sanity(const struct pipe_resource
*tex)
return 0;
}
-static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
-{
- return malloc(pInput->sizeInBytes);
-}
-
-static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT *
pInput)
-{
- free(pInput->pVirtAddr);
- return ADDR_OK;
-}
-
-ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
-{
- ADDR_CREATE_INPUT addrCreateInput = {0};
- ADDR_CREATE_OUTPUT addrCreateOutput = {0};
- ADDR_REGISTER_VALUE regValue = {0};
- ADDR_CREATE_FLAGS createFlags = {{0}};
- ADDR_E_RETURNCODE addrRet;
-
- addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
- addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
-
- regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
- createFlags.value = 0;
-
- if (ws->info.chip_class >= GFX9) {
- addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
- regValue.blockVarSizeLog2 = 0;
- } else {
- regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
- regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
-
- regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask;
- regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
- regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
- if (ws->info.chip_class == SI) {
- regValue.pMacroTileConfig = NULL;
- regValue.noOfMacroEntries = 0;
- } else {
- regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
- regValue.noOfMacroEntries =
ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
- }
-
- createFlags.useTileIndex = 1;
- createFlags.useHtileSliceAlign = 1;
-
- addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
- addrCreateInput.chipFamily = ws->family;
- addrCreateInput.chipRevision = ws->rev_id;
- }
-
- addrCreateInput.chipFamily = ws->family;
- addrCreateInput.chipRevision = ws->rev_id;
- addrCreateInput.callbacks.allocSysMem = allocSysMem;
- addrCreateInput.callbacks.freeSysMem = freeSysMem;
- addrCreateInput.callbacks.debugPrint = 0;
- addrCreateInput.createFlags = createFlags;
- addrCreateInput.regValue = regValue;
-
- addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
- if (addrRet != ADDR_OK)
- return NULL;
-
- return addrCreateOutput.hLib;
-}
-
static int gfx6_compute_level(struct amdgpu_winsys *ws,
const struct pipe_resource *tex,
struct radeon_surf *surf, bool is_stencil,
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 70319db80d..a9c5c01c95 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -237,94 +237,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int
fd)
goto fail;
}
- /* family and rev_id are for addrlib */
- switch (ws->info.family) {
- case CHIP_TAHITI:
- ws->family = FAMILY_SI;
- ws->rev_id = SI_TAHITI_P_A0;
- break;
- case CHIP_PITCAIRN:
- ws->family = FAMILY_SI;
- ws->rev_id = SI_PITCAIRN_PM_A0;
- break;
- case CHIP_VERDE:
- ws->family = FAMILY_SI;
- ws->rev_id = SI_CAPEVERDE_M_A0;
- break;
- case CHIP_OLAND:
- ws->family = FAMILY_SI;
- ws->rev_id = SI_OLAND_M_A0;
- break;
- case CHIP_HAINAN:
- ws->family = FAMILY_SI;
- ws->rev_id = SI_HAINAN_V_A0;
- break;
- case CHIP_BONAIRE:
- ws->family = FAMILY_CI;
- ws->rev_id = CI_BONAIRE_M_A0;
- break;
- case CHIP_KAVERI:
- ws->family = FAMILY_KV;
- ws->rev_id = KV_SPECTRE_A0;
- break;
- case CHIP_KABINI:
- ws->family = FAMILY_KV;
- ws->rev_id = KB_KALINDI_A0;
- break;
- case CHIP_HAWAII:
- ws->family = FAMILY_CI;
- ws->rev_id = CI_HAWAII_P_A0;
- break;
- case CHIP_MULLINS:
- ws->family = FAMILY_KV;
- ws->rev_id = ML_GODAVARI_A0;
- break;
- case CHIP_TONGA:
- ws->family = FAMILY_VI;
- ws->rev_id = VI_TONGA_P_A0;
- break;
- case CHIP_ICELAND:
- ws->family = FAMILY_VI;
- ws->rev_id = VI_ICELAND_M_A0;
- break;
- case CHIP_CARRIZO:
- ws->family = FAMILY_CZ;
- ws->rev_id = CARRIZO_A0;
- break;
- case CHIP_STONEY:
- ws->family = FAMILY_CZ;
- ws->rev_id = STONEY_A0;
- break;
- case CHIP_FIJI:
- ws->family = FAMILY_VI;
- ws->rev_id = VI_FIJI_P_A0;
- break;
- case CHIP_POLARIS10:
- ws->family = FAMILY_VI;
- ws->rev_id = VI_POLARIS10_P_A0;
- break;
- case CHIP_POLARIS11:
- ws->family = FAMILY_VI;
- ws->rev_id = VI_POLARIS11_M_A0;
- break;
- case CHIP_POLARIS12:
- ws->family = FAMILY_VI;
- ws->rev_id = VI_POLARIS12_V_A0;
- break;
- case CHIP_VEGA10:
- ws->family = FAMILY_AI;
- ws->rev_id = AI_VEGA10_P_A0;
- break;
- case CHIP_RAVEN:
- ws->family = FAMILY_RV;
- ws->rev_id = RAVEN_A0;
- break;
- default:
- fprintf(stderr, "amdgpu: Unknown family.\n");
- goto fail;
- }
-
- ws->addrlib = amdgpu_addr_create(ws);
+ ws->addrlib = amdgpu_addr_create(ws->info.family, &ws->amdinfo);
if (!ws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
goto fail;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index a5154ffe7b..896a463ee6 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -73,8 +73,6 @@ struct amdgpu_winsys {
struct amdgpu_gpu_info amdinfo;
ADDR_HANDLE addrlib;
- uint32_t rev_id;
- unsigned family;
bool check_vm;
@@ -91,6 +89,5 @@ amdgpu_winsys(struct radeon_winsys *base)
}
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws);
-ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws);
#endif
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