Module: Mesa
Branch: master
Commit: 8ee31828c656d456bfe067cfae512b1fbbd0bbd6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ee31828c656d456bfe067cfae512b1fbbd0bbd6
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Apr 2 13:44:55 2016 -0700
anv: Keep track of whether the data cache should be enabled in L3
If images or shader buffers are used, we will enable the data cache in
the the L3 config.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/vulkan/anv_pipeline.c | 9 ++++++++-
src/intel/vulkan/anv_private.h | 1 +
src/intel/vulkan/genX_pipeline.c | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 7d265d8..a17a1bb 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -332,8 +332,13 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,
if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
- if (nir->info.num_images > 0)
+ if (nir->info.num_images > 0) {
prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
+ pipeline->needs_data_cache = true;
+ }
+
+ if (nir->info.num_ssbos > 0)
+ pipeline->needs_data_cache = true;
if (prog_data->nr_params > 0) {
/* XXX: I think we're leaking this */
@@ -1113,6 +1118,8 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
pipeline->use_repclear = extra && extra->use_repclear;
+ pipeline->needs_data_cache = false;
+
/* When we free the pipeline, we detect stages based on the NULL status
* of various prog_data pointers. Make them NULL by default.
*/
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 9943677..8afd47f 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1403,6 +1403,7 @@ struct anv_pipeline {
struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES];
bool use_repclear;
+ bool needs_data_cache;
const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
uint32_t
scratch_start[MESA_SHADER_STAGES];
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2328920..2a41b2d 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -74,6 +74,8 @@ genX(compute_pipeline_create)(
pipeline->active_stages = 0;
pipeline->total_scratch = 0;
+ pipeline->needs_data_cache = false;
+
assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
anv_pipeline_compile_cs(pipeline, cache, pCreateInfo, module,
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