Module: Mesa
Branch: master
Commit: 3fcb0212018e52c374f937e806abeca07e938d28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fcb0212018e52c374f937e806abeca07e938d28
Author: Rob Clark <robcl...@freedesktop.org>
Date: Sat Oct 18 16:52:44 2014 -0400
freedreno/a3xx: disable early-z when we have kill's
Signed-off-by: Rob Clark <robcl...@freedesktop.org>
---
src/gallium/drivers/freedreno/a3xx/fd3_emit.c | 3 +++
src/gallium/drivers/freedreno/ir3/ir3_compiler.c | 4 ++++
src/gallium/drivers/freedreno/ir3/ir3_shader.h | 3 +++
3 files changed, 10 insertions(+)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 8300a55..5bf41b1 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -454,6 +454,9 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer
*ring,
val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
+ if (fp->has_kill) {
+ val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
+ }
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, val);
}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
index 8c4ec88..dc4f985 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -2047,6 +2047,8 @@ trans_kill(const struct instr_translater *t,
ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = cond;
ctx->kill[ctx->kill_count++] = instr;
+
+ ctx->so->has_kill = true;
}
/*
@@ -2081,6 +2083,8 @@ trans_killif(const struct instr_translater *t,
ctx->kill[ctx->kill_count++] = instr;
+ ctx->so->has_kill = true;
+
}
/*
* I2F / U2F / F2I / F2U
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 628c09e..a26dab2 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -171,6 +171,9 @@ struct ir3_shader_variant {
/* do we have one or more texture sample instructions: */
bool has_samp;
+ /* do we have kill instructions: */
+ bool has_kill;
+
/* const reg # of first immediate, ie. 1 == c1
* (not regid, because TGSI thinks in terms of vec4 registers,
* not scalar registers)
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