Module: Mesa
Branch: master
Commit: ccfe25f7583dd8d0ff0609de3728c8b15fb0f8fb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccfe25f7583dd8d0ff0609de3728c8b15fb0f8fb
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Thu Mar 31 11:49:53 2016 +0100
i965/fs: shuffle 32bits into 64bits for doubles
VS Thread Payload handles attributes in URB as vec4, no matter if they
are actually single or double precision.
So with double-precision types, value ends up in the registers split in
32bits chunks, in different positions.
We need to shuffle the chunks to get the doubles correctly.
v2:
* Extra blank line. Add { } on if body (Ian Romanick)
* Use dest directly (Kenneth Graunke)
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 59a7a56..ad20dc8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -3711,6 +3711,14 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
nir_intrinsic_instr *instr
for (unsigned j = 0; j < instr->num_components; j++) {
bld.MOV(offset(dest, bld, j), offset(src, bld, j));
}
+
+ if (type_sz(src.type) == 8) {
+ shuffle_32bit_load_result_to_64bit_data(bld,
+ dest,
+ retype(dest,
BRW_REGISTER_TYPE_F),
+ instr->num_components);
+ }
+
break;
}
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