Module: Mesa
Branch: master
Commit: 5bad948fa8a4fe812d254b6251e5e5dbd8a64e1c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5bad948fa8a4fe812d254b6251e5e5dbd8a64e1c
Author: Damien Lespiau <damien.lesp...@intel.com>
Date: Wed Feb 27 15:05:24 2013 +0000
i965/skl: Emit depth stall workaround for gen9 as well
The docs say that we shouldn't need this workaround for gen8+, but just
removing it, causes gpu hangs. We'll revisit this, but for now, just
extend the workaround to gen9.
Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Kristian Høgsberg <k...@bitplanet.net>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index cd45af6..2bd11d7 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -535,7 +535,7 @@ brw_emit_pipe_control_write(struct brw_context *brw,
uint32_t flags,
void
intel_emit_depth_stall_flushes(struct brw_context *brw)
{
- assert(brw->gen >= 6 && brw->gen <= 8);
+ assert(brw->gen >= 6 && brw->gen <= 9);
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
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