Module: Mesa Branch: master Commit: 1737e75bfb85eb22a30e4f1c69a825b3abd946f6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1737e75bfb85eb22a30e4f1c69a825b3abd946f6
Author: Iago Toral Quiroga <ito...@igalia.com> Date: Fri Jul 15 10:48:03 2016 +0200 i965/tcs/scalar: only update imm_offset for second message in 64bit input loads Our indirect URB read messages take both a direct and an indirect offset so when we emit the second message for a 64-bit input load we can just always incremement the immediate offset, even for the indirect case. Reviewed-by: Timothy Arceri <timothy.arc...@collabora.com> --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 5442b73..f3c8430 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -2509,13 +2509,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld, */ if (num_iterations > 1) { num_components = instr->num_components - 2; - if (indirect_offset.file == BAD_FILE) { - imm_offset++; - } else { - fs_reg new_indirect = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u)); - indirect_offset = new_indirect; - } + imm_offset++; } } break; _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit