Module: Mesa Branch: master Commit: 55e2b3424decf9f0240bb6fe0fd521e775d28d66 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55e2b3424decf9f0240bb6fe0fd521e775d28d66
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Date: Tue Sep 29 18:41:31 2020 +0200 radeonsi: Fix imports with displayable DCC. Otherwise we reset the displayable DCC on import. Fixes: c6c1fa9a263 "radeonsi: Put retile map in separate buffers." Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-pra...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3577 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6918> --- src/gallium/drivers/radeonsi/si_texture.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 68d8e2c1f4e..93e52e75c8d 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -1152,10 +1152,12 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, /* Initialize displayable DCC that requires the retile blit. */ if (tex->surface.display_dcc_offset) { - /* Uninitialized DCC can hang the display hw. - * Clear to white to indicate that. */ - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.display_dcc_offset, - tex->surface.u.gfx9.display_dcc_size, DCC_CLEAR_COLOR_1111); + if (!(surface->flags & RADEON_SURF_IMPORTED)) { + /* Uninitialized DCC can hang the display hw. + * Clear to white to indicate that. */ + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.display_dcc_offset, + tex->surface.u.gfx9.display_dcc_size, DCC_CLEAR_COLOR_1111); + } /* Upload the DCC retile map. * Use a staging buffer for the upload, because _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit