Module: Mesa
Branch: master
Commit: de7d3825a0a2e4144e0b38a0d8fef759819af64a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de7d3825a0a2e4144e0b38a0d8fef759819af64a
Author: Christian König <deathsim...@vodafone.de>
Date: Fri Aug 31 13:59:14 2012 +0200
radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTS
So it matches what we really can do.
Signed-off-by: Christian König <deathsim...@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 4 ++--
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 3 ---
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 48b9a3e..f3914d7 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -450,9 +450,9 @@ static int r600_get_shader_param(struct pipe_screen*
pscreen, unsigned shader, e
/* FIXME Isn't this equal to TEMPS? */
return 1; /* Max native address registers */
case PIPE_SHADER_CAP_MAX_CONSTS:
- return R600_MAX_CONST_BUFFER_SIZE;
+ return 64;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return R600_MAX_CONST_BUFFERS;
+ return 1;
case PIPE_SHADER_CAP_MAX_PREDS:
return 0; /* FIXME */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index 099b509..a23f34f 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -41,9 +41,6 @@
#include "r600_resource.h"
#include "sid.h"
-#define R600_MAX_CONST_BUFFERS 1
-#define R600_MAX_CONST_BUFFER_SIZE 4096
-
#ifdef PIPE_ARCH_BIG_ENDIAN
#define R600_BIG_ENDIAN 1
#else
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