Module: Mesa
Branch: master
Commit: a81e99f50a718790de379087c9f5a636e32b2a28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a81e99f50a718790de379087c9f5a636e32b2a28
Author: Dave Airlie <airl...@redhat.com>
Date: Wed Jul 26 02:32:39 2017 +0100
radv/ac: realign SI workaround with radeonsi.
This ports: da7453666ae
radeonsi: don't apply the Z export bug workaround to Hainan
to radv.
Just noticed in passing.
Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/common/ac_nir_to_llvm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 9a69066afa..a427f484b5 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5815,10 +5815,11 @@ si_export_mrt_z(struct nir_to_llvm_context *ctx,
args.enabled_channels |= 0x4;
}
- /* SI (except OLAND) has a bug that it only looks
+ /* SI (except OLAND and HAINAN) has a bug that it only looks
* at the X writemask component. */
if (ctx->options->chip_class == SI &&
- ctx->options->family != CHIP_OLAND)
+ ctx->options->family != CHIP_OLAND &&
+ ctx->options->family != CHIP_HAINAN)
args.enabled_channels |= 0x1;
ac_build_export(&ctx->ac, &args);
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