On Die, 2013-02-12 at 15:22 +0100, Tom Stellard wrote:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Thanks, committed as revision 175138. Unfortunately, I only noticed
afterwards that the new SI test failed an assertion on trunk, see below.
I committed revision 175139 to fix that, but it
Am 14.02.2013 09:20, schrieb Michel Dänzer:
On Die, 2013-02-12 at 15:22 +0100, Tom Stellard wrote:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Thanks, committed as revision 175138. Unfortunately, I only noticed
afterwards that the new SI test failed an assertion on trunk, see below.
I
Am 13.02.2013 18:22, schrieb Michel Dänzer:
On Mit, 2013-02-13 at 18:17 +0100, Christian König wrote:
Am 13.02.2013 18:11, schrieb Michel Dänzer:
On Mit, 2013-02-13 at 11:34 -0500, Tom Stellard wrote:
There's just the one cleanup on patch 10 that you mentioned, but
otherwise the series looks
On Don, 2013-02-14 at 11:32 +0100, Christian König wrote:
Am 13.02.2013 18:22, schrieb Michel Dänzer:
On Mit, 2013-02-13 at 18:17 +0100, Christian König wrote:
Am 13.02.2013 18:11, schrieb Michel Dänzer:
On Mit, 2013-02-13 at 11:34 -0500, Tom Stellard wrote:
There's just the one cleanup
Hi Vadim,
nice work, I think you've made quite a progress here, but on the other
hand it should be clear that the LLVM backend is the future and we
should concentrate on that.
To sum it up I'm not sure what we should do with this branch :)
As Dragomir already wrote even if the code won't be
From: Christian König christian.koe...@amd.com
Using the new NearestCommonDominator class.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp |6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/Target/R600/AMDGPUStructurizeCFG.cpp
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 66 ++
1 file changed, 66 insertions(+)
diff --git a/lib/Target/R600/AMDGPUStructurizeCFG.cpp
From: Christian König christian.koe...@amd.com
Using the new NearestCommonDominator class.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 31 +-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git
From: Christian König christian.koe...@amd.com
Generate more than one loop if it seems to make sense.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 344 +-
1 file changed, 148 insertions(+), 196 deletions(-)
From: Christian König christian.koe...@amd.com
Stop adding more instructions than necessary.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUCodeEmitter.h| 45
lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h |7 ---
2 files changed, 52 deletions(-)
delete mode
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 66 +
lib/Target/R600/SIInstrInfo.td| 66 -
2 files changed, 66
From: Christian König christian.koe...@amd.com
Previously it only worked because of coincident.
v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
for the unused SRC2
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 53
From: Christian König christian.koe...@amd.com
Mark all the operands that can also have an immediate.
v2: SOFFSET is also an SSrc_32 operand
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 36 +--
lib/Target/R600/SIInstructions.td |
From: Christian König christian.koe...@amd.com
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
Signed-off-by:
From: Christian König christian.koe...@amd.com
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
Signed-off-by: Christian
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrInfo.td|4
lib/Target/R600/SIInstructions.td |5 +
2 files changed, 9 insertions(+)
diff --git a/lib/Target/R600/SIInstrInfo.td
On 14 February 2013 11:42, Christian König deathsim...@vodafone.de wrote:
nice work, I think you've made quite a progress here, but on the other hand
it should be clear that the LLVM backend is the future and we should
concentrate on that.
I'm not sure that's really true. My impression is that
Am 14.02.2013 12:05, schrieb Henri Verbeet:
On 14 February 2013 11:42, Christian König deathsim...@vodafone.de wrote:
nice work, I think you've made quite a progress here, but on the other hand
it should be clear that the LLVM backend is the future and we should
concentrate on that.
I'm not
On 14 February 2013 12:28, Christian König deathsim...@vodafone.de wrote:
Well apart from a bit strange coding style and the use of SVN, I can't
really see any problems that are related to using LLVM as it is.
Well, for one, I don't think LLVM believes in stable APIs or shared
libraries, and I
Dear developers and testers of Mesa (oh, that would included myself a bit:),
thank you for working on this great piece of software!
I love it!
Special thanks to Kenneth Graunke for bettering my Planeshift gaming
experience to such a huge extent.
Best,
--
Martin
Please ignore this version of the patchset, it was send accidentally
from the wrong machine and so doesn't contain the correct patches.
Christian.
Am 14.02.2013 11:42, schrieb Christian König:
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König
On Don, 2013-02-14 at 11:43 +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler
On Wed, Feb 13, 2013 at 06:54:45PM +0100, Michel Dänzer wrote:
From: Michel Dänzer michel.daen...@amd.com
16 more little piglits with radeonsi.
NOTE: This is a candidate for the Mesa stable branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
It would be great if you could add
On Don, 2013-02-14 at 14:35 +0100, Michel Dänzer wrote:
On Don, 2013-02-14 at 11:43 +0100, Christian König wrote:
+// Only one literal allowed
+break;
The same literal could be used for several operands though. :)
Basically, it seems like we're pretty close to allowing VSrc
On Don, 2013-02-14 at 15:14 +0100, Michel Dänzer wrote:
On Don, 2013-02-14 at 14:35 +0100, Michel Dänzer wrote:
On Don, 2013-02-14 at 11:43 +0100, Christian König wrote:
+// Only one literal allowed
+break;
The same literal could be used for several operands though. :)
I'll need this later.
---
src/mesa/state_tracker/st_cb_texture.c | 108 +++-
1 file changed, 66 insertions(+), 42 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index f8ff024..5b3d2ab 100644
---
BTW, we have 0 tests for glGetTexImage(format=GL_DEPTH*).
---
src/mesa/state_tracker/st_cb_texture.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index 5b3d2ab..b0d4ea5 100644
---
This is not easy to hit, because we have 3 code paths now
(tried in this order):
- memcpy-based (skips the blit) - _mesa_tex_getimage
- blit-based
- slow pixel packing - _mesa_tex_getimage
The main difference later in the code is the parameters of
_mesa_image_address3d.
---
A temporary texture is created such that it matches the format and type
combination and pixels are copied to it using memcpy. Then the blit is used to
copy the temporary texture to the texture image being modified by TexImage or
TexSubImage. The blit takes care of the format and type conversion
Assuming I understand EXT_texture_sRGB correctly.
NOTE: This is a candidate for the stable branches.
---
src/mesa/state_tracker/st_cb_texture.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
It has become a bit messy.
Changes:
- finally correct checking for transfer ops depending on the base format
- making sure the base internal format and the texture format match
(we were ignoring it, but it's important for correctness)
- the way-too-strict rule that both src and dst base
---
src/mesa/state_tracker/st_cb_blit.c| 16
src/mesa/state_tracker/st_cb_blit.h|7 ---
src/mesa/state_tracker/st_cb_flush.c |1 -
src/mesa/state_tracker/st_cb_texture.c |1 -
src/mesa/state_tracker/st_context.c|2 --
On 13 February 2013 21:11, Eric Anholt e...@anholt.net wrote:
Kenneth Graunke kenn...@whitecape.org writes:
On 02/13/2013 06:31 PM, Eric Anholt wrote:
Kenneth Graunke kenn...@whitecape.org writes:
Meta-instructions that implicitly write then read/consume a MRF value
don't pose
Am 14.02.2013 15:14, schrieb Michel Dänzer:
On Don, 2013-02-14 at 14:35 +0100, Michel Dänzer wrote:
On Don, 2013-02-14 at 11:43 +0100, Christian König wrote:
+// Only one literal allowed
+break;
The same literal could be used for several operands though. :)
Basically, it seems like
On Don, 2013-02-14 at 16:20 +0100, Christian König wrote:
Am 14.02.2013 15:14, schrieb Michel Dänzer:
On Don, 2013-02-14 at 14:35 +0100, Michel Dänzer wrote:
On Don, 2013-02-14 at 11:43 +0100, Christian König wrote:
+// Only one literal allowed
+break;
The same literal could be
---
lib/Target/R600/R600RegisterInfo.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/Target/R600/R600RegisterInfo.td
b/lib/Target/R600/R600RegisterInfo.td
index 3812eb7..0718854 100644
--- a/lib/Target/R600/R600RegisterInfo.td
+++
NOTE: This is a candidate for the Mesa stable branch.
---
lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 3 +-
lib/Target/R600/R600Instructions.td| 54 ++
lib/Target/R600/R600Intrinsics.td | 2 +
3 files changed, 58 insertions(+), 1
NOTE: This is a candidate for the Mesa stable branch.
---
src/gallium/drivers/r600/r600_llvm.c| 6 +-
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 17 +
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git
---
src/gallium/drivers/r600/r600_llvm.c | 2 ++
src/gallium/drivers/r600/r600_shader.c | 1 +
src/gallium/drivers/radeon/radeon_llvm.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_llvm.c
b/src/gallium/drivers/r600/r600_llvm.c
index 7a41688..59047e7
---
src/gallium/drivers/radeon/radeon_llvm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h
b/src/gallium/drivers/radeon/radeon_llvm.h
index bfeacb5..b1e025b 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++
---
src/gallium/drivers/r600/r600_llvm.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_llvm.c
b/src/gallium/drivers/r600/r600_llvm.c
index 59047e7..89bcb79 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++
Kenneth Graunke kenn...@whitecape.org writes:
On 02/06/2013 05:29 PM, Eric Anholt wrote:
We'd been ad-hoc inserting instructions in some SEND messages with no
knowledge of when it was required (so extra instructions), but not all SENDs
(so not often enough). This should do much better than
Hi!
Amazing work! I see some 50 % speed ups in FlightGear and even more. While
normally 3D clouds tear performance down to an unflyable stutter, with your
branch I can fly in densly clouded conditions at usable framerates. I can now
turn all shaders to maximum and enjoy the view. This makes a
On Mit, 2013-02-13 at 17:51 +0100, Christian König wrote:
Am 13.02.2013 17:07, schrieb Michel Dänzer:
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, pass the
In GLSL, sampler indices are allocated contiguously from 0. But in the case
of ARB_fragment_program (and possibly fixed function), an app that uses
texture 0 and 2 will use sampler indices 0 and 2, so we were only allocating
space for samplers 0 and 1 and setting up sampler 0. We would read
On Thu, Feb 14, 2013 at 06:07:16PM +0100, Michel Dänzer wrote:
On Mit, 2013-02-13 at 17:51 +0100, Christian König wrote:
Am 13.02.2013 17:07, schrieb Michel Dänzer:
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in
From: Christian König christian.koe...@amd.com
Using the new NearestCommonDominator class.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 31 +-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git
From: Christian König christian.koe...@amd.com
Using the new NearestCommonDominator class.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp |6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/Target/R600/AMDGPUStructurizeCFG.cpp
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 66 ++
1 file changed, 66 insertions(+)
diff --git a/lib/Target/R600/AMDGPUStructurizeCFG.cpp
From: Christian König christian.koe...@amd.com
Generate more than one loop if it seems to make sense.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 344 +-
1 file changed, 148 insertions(+), 196 deletions(-)
From: Christian König christian.koe...@amd.com
Stop adding more instructions than necessary.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUStructurizeCFG.cpp | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/AMDGPUCodeEmitter.h| 45
lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h |7 ---
2 files changed, 52 deletions(-)
delete mode
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 66 +
lib/Target/R600/SIInstrInfo.td| 66 -
2 files changed, 66
From: Christian König christian.koe...@amd.com
Previously it only worked because of coincident.
v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
for the unused SRC2
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 53
From: Christian König christian.koe...@amd.com
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
v3: correctly use
From: Christian König christian.koe...@amd.com
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrInfo.td|4
lib/Target/R600/SIInstructions.td |5 +
2 files changed, 9 insertions(+)
diff --git a/lib/Target/R600/SIInstrInfo.td
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an operand to V_INTERP_MOV_F32 instead of
Am 14.02.2013 19:30, schrieb Michel Dänzer:
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an
On Thu, Feb 14, 2013 at 05:47:11PM +0100, Vincent Lejeune wrote:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/R600RegisterInfo.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/Target/R600/R600RegisterInfo.td
On Thu, Feb 14, 2013 at 05:47:12PM +0100, Vincent Lejeune wrote:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
NOTE: This is a candidate for the Mesa stable branch.
---
lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 3 +-
lib/Target/R600/R600Instructions.td| 54
On Thu, Feb 14, 2013 at 07:38:04PM +0100, Christian König wrote:
Am 14.02.2013 19:30, schrieb Michel Dänzer:
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition,
On Thu, Feb 14, 2013 at 06:34:14PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
For the series:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Don't forget to mark these as candidates for the stable
On Thu, Feb 14, 2013 at 05:48:33PM +0100, Vincent Lejeune wrote:
For the series:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
NOTE: This is a candidate for the Mesa stable branch.
---
src/gallium/drivers/r600/r600_llvm.c| 6 +-
https://bugs.freedesktop.org/show_bug.cgi?id=60737
Paul Berry stereotype...@gmail.com changed:
What|Removed |Added
Priority|medium |low
--- Comment #2
The GL_ARB_texture_rg spec says that we need to support both texturing
and rendering for the GL_RED and GL_RG formats. So move the format
check up into the rendertarget_mapping[] list. Also, add
PIPE_FORMAT_R8_UNORM to the list of formats required.
Note: This is a candidate for the stable
On 02/14/2013 08:53 PM, Stefan Seifert wrote:
Hi!
Amazing work! I see some 50 % speed ups in FlightGear and even more. While
normally 3D clouds tear performance down to an unflyable stutter, with your
branch I can fly in densly clouded conditions at usable framerates. I can now
turn all shaders
On 02/14/2013 07:53 AM, Marek Olšák wrote:
I'll need this later.
---
src/mesa/state_tracker/st_cb_texture.c | 108 +++-
1 file changed, 66 insertions(+), 42 deletions(-)
The series looks good to me.
Regarding patch 4 (the blit-based Tex[Sub]Image change),
Hi,
noticed when polishing up my build-scripts fot libdrm | mesa |
xf86-video-intel (last one requires gl.h).
/*
* Mesa 3-D graphics library
* Version: 7.6 --- ???
*
* Copyright (C) 1999-2006 Brian Paul All Rights Reserved. --- ???
* Copyright (C) 2009 VMware, Inc. All Rights
On 02/14/2013 01:10 PM, Sedat Dilek wrote:
Hi,
noticed when polishing up my build-scripts fot libdrm | mesa |
xf86-video-intel (last one requires gl.h).
/*
* Mesa 3-D graphics library
* Version: 7.6--- ???
I could remove that obsolete line.
*
* Copyright (C) 1999-2006 Brian Paul
On 02/14/2013 09:08 AM, Eric Anholt wrote:
In GLSL, sampler indices are allocated contiguously from 0. But in the case
of ARB_fragment_program (and possibly fixed function), an app that uses
texture 0 and 2 will use sampler indices 0 and 2, so we were only allocating
space for samplers 0 and 1
On 02/14/2013 12:29 PM, Sedat Dilek wrote:
On Thu, Feb 14, 2013 at 9:26 PM, Brian Paul bri...@vmware.com wrote:
On 02/14/2013 01:10 PM, Sedat Dilek wrote:
Hi,
noticed when polishing up my build-scripts fot libdrm | mesa |
xf86-video-intel (last one requires gl.h).
/*
* Mesa 3-D graphics
On 02/13/2013 07:07 PM, Kenneth Graunke wrote:
On 02/06/2013 05:29 PM, Eric Anholt wrote:
We'd been ad-hoc inserting instructions in some SEND messages with no
knowledge of when it was required (so extra instructions), but not all
SENDs
(so not often enough). This should do much better than
On 02/14/2013 08:53 PM, Stefan Seifert wrote:
Hi!
Amazing work! I see some 50 % speed ups in FlightGear and even more. While
normally 3D clouds tear performance down to an unflyable stutter, with your
branch I can fly in densly clouded conditions at usable framerates. I can now
turn all shaders
On Thu, Feb 14, 2013 at 9:26 PM, Brian Paul bri...@vmware.com wrote:
On 02/14/2013 01:10 PM, Sedat Dilek wrote:
Hi,
noticed when polishing up my build-scripts fot libdrm | mesa |
xf86-video-intel (last one requires gl.h).
/*
* Mesa 3-D graphics library
* Version: 7.6--- ???
I
On Thu, Feb 14, 2013 at 9:23 PM, Brian Paul bri...@vmware.com wrote:
On 02/14/2013 07:53 AM, Marek Olšák wrote:
I'll need this later.
---
src/mesa/state_tracker/st_cb_texture.c | 108
+++-
1 file changed, 66 insertions(+), 42 deletions(-)
The series looks
Reviewed-by: Marek Olšák mar...@gmail.com
Marek
On Thu, Feb 14, 2013 at 8:26 PM, Brian Paul bri...@vmware.com wrote:
The GL_ARB_texture_rg spec says that we need to support both texturing
and rendering for the GL_RED and GL_RG formats. So move the format
check up into the
https://bugs.freedesktop.org/show_bug.cgi?id=59187
Benjamin Berg benja...@sipsolutions.net changed:
What|Removed |Added
CC|
From: Roland Scheidegger srol...@vmware.com
(Though it looks glsl won't emit it.)
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c |1 -
1 file changed, 1 deletion(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index
From: Roland Scheidegger srol...@vmware.com
Need to take the type into account. Also, if we want to allow
mov's with modifiers we need to pick a type (assume float).
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 54 ++-
1 file changed, 52 insertions(+), 2
From: Roland Scheidegger srol...@vmware.com
We need to encode them as Texture instructions since the NumOffsets field
is encoded there. However, we don't encode the actual target in there, this
is derived from the sampler view src later.
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h |
This is actually really a RFC.
Another solution would be to also encode the target (either with or
without shadow information) in the instruction too though it seems a bit
unnatural for these instructions.
Or to not encode them as Texture instructions (so as before) but then
some other method is
From: Roland Scheidegger srol...@vmware.com
Need to take the type into account. Also, if we want to allow
mov's with modifiers we need to pick a type (assume float).
Just FYI, the r600g hw all ignores modifiers on non-floating types from memory.
Dave.
Am 15.02.2013 04:41, schrieb Dave Airlie:
From: Roland Scheidegger srol...@vmware.com
Need to take the type into account. Also, if we want to allow
mov's with modifiers we need to pick a type (assume float).
Just FYI, the r600g hw all ignores modifiers on non-floating types from
memory.
GLX_INTEL_swap_event is broken on the server side, where it's
currently unconditionally enabled. This completely breaks
systems running on drivers which don't support that extension.
There's no way to test for its presence on this side, so instead
of disabling it uncondtionally, just disable it
https://bugs.freedesktop.org/show_bug.cgi?id=57121
Markus Wick wickmar...@web.de changed:
What|Removed |Added
Assignee|mesa-dev@lists.freedesktop. |i...@freedesktop.org
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