On Sun, Mar 31, 2013 at 1:08 AM, Vadim Girlin wrote:
> On 03/30/2013 05:35 AM, Martin Andersson wrote:
>>
>> I found an issue with the shader compiler for Cayman when I looked
>> into why the ext_transform_feedback/order test case caused a GPU stall.
>> It turned out the stall was an infinite loop
This series implements ARB_texture_gather in core mesa, and the
driver side for Gen7 i965.
Not quite baked -- green/blue/alpha texture swizzles with VS don't
work yet. Everything else works, though (R/0/1 swizzles in VS; all
swizzles in FS; textureGather and textureGatherOffset).
The first two pa
From: Maxence Le Dore
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 14 ++
src/mapi/glapi/gen/gl_API.xml | 2 +-
src/mesa/main/context.c | 4
src/mesa/main/extensions.c| 1 +
src/mesa/main/get.c | 1 +
src
From: Maxence Le Dore
From: Maxence Le Dore
V2 [Chris Forbes]:
- Add new pattern, fixup parameter reading.
---
src/glsl/builtins/profiles/ARB_texture_gather.glsl | 27 ++
src/glsl/builtins/tools/generate_builtins.py | 1 +
src/glsl/builtins/tools/texture_builtins.
Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
src/mesa/drivers/dri/i965/brw_fs.cpp| 4 +++-
src/mesa/drivers/dri/i965/brw_fs_emit
Lowers ir_tg4 (from textureGather and textureGatherOffset builtins) to
SHADER_OPCODE_TG4.
The usual post-sampling swizzle workaround can't work for ir_tg4,
so avoid doing that:
* For R/G/B/A swizzles use the hardware channel select (lives in the
same dword in the header as the texel offset), a
Pretty much the same as the FS case. Channel select goes in the header,
post-sampling swizzle only does the 0/1 cases.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp| 2 +-
src/mesa/drivers/dri/i965/brw_vec4
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/drivers/dri/intel/intel_extensions.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index ceaf325..e8f9c60 100
Build tested only.
---
src/gallium/state_trackers/clover/llvm/invocation.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index 2785d10..7971bd9 100644
--- a/src/
I've already posted this
Clover seems to be working as well as it normally does
On 31 March 2013 11:00, Armin K wrote:
> Build tested only.
> ---
> src/gallium/state_trackers/clover/llvm/invocation.cpp | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/stat
Dana 31.3.2013 14:21, Mike Lothian je napisao:
I've already posted this
Clover seems to be working as well as it normally does
Doh, and I thought I looked at mesa-dev for a patch. It's hard to find
it on such high traffic mailing list.
___
mesa-
Hi,
I think have found a bug in the r600g shader compiler. I have a AMD 6950
and I'm running mesa from git.
The bug is exercised by the the vertex shader program in piglit
ext_transform_feedback/order.c
I have simplified the shader program so the compiled shader is easier to read:
#version 130
On Sun, Mar 31, 2013 at 2:51 PM, Martin Andersson wrote:
>
> It compiles to, http://pastebin.com/cQ8rbKCv.
There should not be a dot at the end, the correct address is:
http://pastebin.com/cQ8rbKCv
I also configure mesa with --disable-gallium-llvm
//Martin
__
On 03/31/2013 01:01 PM, Martin Andersson wrote:
On Sun, Mar 31, 2013 at 1:08 AM, Vadim Girlin wrote:
On 03/30/2013 05:35 AM, Martin Andersson wrote:
I found an issue with the shader compiler for Cayman when I looked
into why the ext_transform_feedback/order test case caused a GPU stall.
It tu
Hi Vadim,
Does this patch work ? (It's still not pushed)
I'm working on doing native control flow for llvm and intend to port your patch
on the control flow reservation.
Vincent
- Mail original -
> De : Vadim Girlin
> À : Alex Deucher
> Cc : mesa-dev@lists.freedesktop.org
> Envoyé
On 04/01/2013 12:00 AM, Vincent Lejeune wrote:
Hi Vadim,
Does this patch work ? (It's still not pushed)
It works for me on evergreen, but I'm not sure about other chip
generations. I wanted to ask somebody to test it, but the problem is
that the piglit coverage for this is not enough (e.g. i
On 03/31/2013 04:51 PM, Martin Andersson wrote:
Hi,
I think have found a bug in the r600g shader compiler. I have a AMD 6950
and I'm running mesa from git.
The bug is exercised by the the vertex shader program in piglit
ext_transform_feedback/order.c
I have simplified the shader program so the
On Sun, Mar 31, 2013 at 2:10 AM, Chris Forbes wrote:
> Signed-off-by: Chris Forbes
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 1 +
> src/mesa/drivers/dri/intel/intel_extensions.c | 4
> 2 files changed, 5 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
>
Thanks, will do.
On Mon, Apr 1, 2013 at 12:01 PM, Matt Turner wrote:
> On Sun, Mar 31, 2013 at 2:10 AM, Chris Forbes wrote:
>> Signed-off-by: Chris Forbes
>> ---
>> src/mesa/drivers/dri/i965/brw_context.c | 1 +
>> src/mesa/drivers/dri/intel/intel_extensions.c | 4
>> 2 files change
Reported-by: `per` in #intel-gfx
The size of the cache key varies, so store the actual size as well as
the key blob itself, rather than just assuming it's the same as the size
passed in.
NOTE: This is a candidate for stable branches.
Signed-off-by: Chris Forbes
---
src/mesa/program/prog_cache.
On 03/20/2013 05:36 PM, Eric Anholt wrote:
This happens quite a bit with varying-index uniform loads. We could also
do better by avoiding the MACH entirely, but there's no reason not to at
least take this step.
---
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp |6 --
1 file ch
On 03/20/2013 05:36 PM, Eric Anholt wrote:
I think this makes it much more obvious what's going on here.
NOTE: This is a candidate for the 9.1 branch.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mesa/driv
On 03/20/2013 05:36 PM, Eric Anholt wrote:
For sampler messages, it depends on the target gen, and on gen4
SIMD16-sampler-on-SIMD8-execution we were returning 4 instead of 8 like we
should.
NOTE: This is a candidate for the 9.1 branch.
---
src/mesa/drivers/dri/i965/brw_fs.cpp |
On 03/20/2013 05:37 PM, Eric Anholt wrote:
This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on
my GM45 forced to load all uniforms through the varying-index path), but we
get a whole vec4 at a time to reuse in the next commit.
NOTE: This is a candidate for the 9.1 branc
On 03/20/2013 05:36 PM, Eric Anholt wrote:
https://bugs.freedesktop.org/show_bug.cgi?id=61554
It's had more "me too"s than I would have expected, so I've marked all but
2 incidental patches as a candidate for 9.1. It's also fairly invasive,
so I'm quite uncomfortable doing so. I've tested on g
On 03/22/2013 05:40 PM, Eric Anholt wrote:
We dump shader source in ir_to_mesa.cpp, and we dump linked programs here,
but we had no reference from the linked programs to their source. This
was preventing improvement of shader-db to use linked shader programs
instead of individual shader files (w
On 03/12/2013 12:25 PM, Eric Anholt wrote:
This is a more aggressive version of the old brw_optimize() path.
Reduces cycles spent in the vertex shader on minecraft by 18.6% +/- 10.0%
(n=15).
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 109 +++
src/mesa/drivers/dr
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