Re: [Mesa-dev] [PATCH] glsl/opt_algebraic: recognize lrp pattern

On Fri, Nov 15, 2013 at 7:47 PM, Eric Anholt wrote: > Jordan Justen writes: > >> This algebraic optimization recognizes an series of adds and >> multiplies with a particular pattern within the ir which is >> equivalent to a lrp. >> >> shader-db results: >> total instructions in shared programs: 1

Re: [Mesa-dev] [PATCH V3 05/13] mesa: Add validation helpers for new indirect draws

Ken, I don't have access to another implementation at the moment -- can you test? -- Chris On Wed, Nov 13, 2013 at 9:57 AM, Kenneth Graunke wrote: > On 11/12/2013 12:35 PM, Paul Berry wrote: >> On 12 November 2013 12:13, Kenneth Graunke > > wrote: >> >> It woul

Re: [Mesa-dev] [PATCH] glsl/opt_algebraic: recognize lrp pattern

Jordan Justen writes: > This algebraic optimization recognizes an series of adds and > multiplies with a particular pattern within the ir which is > equivalent to a lrp. > > shader-db results: > total instructions in shared programs: 1729161 -> 1718321 (-0.63%) > instructions in affected programs

Re: [Mesa-dev] [PATCH 1/2] i965/gen7: Prefer vertical alignment of 4 when possible.

On 11/15/2013 01:18 PM, Paul Berry wrote: > Gen6+ allows for color buffers to use a vertical alignment of either 4 > or 2. Previously we defaulted to 2. This may have caused problems on > Gen7 because Y-tiled render targets are not allowed to use a vertical > alignment of 2. > > This patch chang

[Mesa-dev] [Bug 71543] [mesa] Source-based games segfault

https://bugs.freedesktop.org/show_bug.cgi?id=71543 Kenneth Graunke changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|NOTOURBUG

[Mesa-dev] [PATCH] radeon/compute: Unconditionally inline all functions v2

From: Tom Stellard We need to do this until function calls are supported. v2: - Fix loop conditional https://bugs.freedesktop.org/show_bug.cgi?id=64225 CC: "10.0" --- src/gallium/drivers/radeon/radeon_llvm_util.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-)

Re: [Mesa-dev] [PATCH] i965/vec4: Fix broken IR annotation in debug output.

Paul Berry writes: > Commit 70953b5 (i965: Initialize all member variables of > vec4_instruction on construction) inadvertently added a line to the > vec4_instruction constructor setting this->ir to NULL, wiping out the > previously set value. As a result, ever since then, the output of > INTEL_

[Mesa-dev] [Bug 71665] New: glu.pc.in missing -I for glu itself

https://bugs.freedesktop.org/show_bug.cgi?id=71665 Priority: medium Bug ID: 71665 Assignee: mesa-dev@lists.freedesktop.org Summary: glu.pc.in missing -I for glu itself Severity: normal Classification: Unclassified OS: All

[Mesa-dev] [Bug 71665] glu.pc.in missing -I for glu itself

https://bugs.freedesktop.org/show_bug.cgi?id=71665 John Hein <5qgu8gv...@snkmail.com> changed: What|Removed |Added CC||5qgu8gv...@snkmail.co

Re: [Mesa-dev] [PATCH] clover: Optionally return context's devices from clGetProgramInfo()

Tom Stellard writes: > From: Tom Stellard > > The spec allows clGetProgramInfo() to return information about either > the devices associated with the program or the devices associated > with the context. If there are no devices associated with the program, > then we return devices associated wi

Re: [Mesa-dev] [PATCH] r600g/compute: Fix handling of global buffers in r600_resource_copy_region()

Reviewed-by: Marek Olšák Marek On Fri, Nov 15, 2013 at 8:47 PM, Tom Stellard wrote: > From: Tom Stellard > > Global buffers do not have an associate cs_buf handle, so > we can't copy them using r600_copy_buffer() > > https://bugs.freedesktop.org/show_bug.cgi?id=64226 > > CC: "10.0" > --- > s

[Mesa-dev] [PATCH] clover: Optionally return context's devices from clGetProgramInfo()

From: Tom Stellard The spec allows clGetProgramInfo() to return information about either the devices associated with the program or the devices associated with the context. If there are no devices associated with the program, then we return devices associated with the context. https://bugs.free

[Mesa-dev] [PATCH] i965/vec4: Fix broken IR annotation in debug output.

Commit 70953b5 (i965: Initialize all member variables of vec4_instruction on construction) inadvertently added a line to the vec4_instruction constructor setting this->ir to NULL, wiping out the previously set value. As a result, ever since then, the output of INTEL_DEBUG=vs and INTEL_DEBUG=gs has

[Mesa-dev] [PATCH] glsl: Fix interstage uniform interface block link error detection.

Previously, we checked for interstage uniform interface block link errors in validate_interstage_interface_blocks(), which is only called on pairs of adjacent shader stages. Therefore, we failed to detect uniform interface block mismatches between non-adjacent shader stages. Before the introducti

[Mesa-dev] Picks to 10.0 release branch

I believe that I have picked over all of the patches marked for the 10.0 release branch. I have included the full list far below. There are a few patches that were sent to the mesa-stable mailing list that do not appear to have landed on master yet. I have not picked these over. These are: rade

[Mesa-dev] [Bug 71543] [mesa] Source-based games segfault

https://bugs.freedesktop.org/show_bug.cgi?id=71543 Nikolay Amiantov changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH] i965: Add missing break in SHADER_OPCODE_GEN7_SCRATCH_READ case.

Vinson Lee writes: > Fixes "Missing break in switch" defect reported by Coverity. Accidentally falling through to the most wrong value we could. Awesome. Reviewed-by: Eric Anholt pgpyraGJqTttU.pgp Description: PGP signature ___ mesa-dev mailing li

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] docs: update 10.0 relnotes for GL_NV_vdpau_interop

This patch doesn't appear to have landed on master with the other patch. Is that intentional? On 11/12/2013 01:51 AM, Fabio Pedretti wrote: > Cc: "10.0" > --- > docs/relnotes/10.0.html | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/docs/relnotes/10.0.html b/docs/relnotes/10.0.html >

[Mesa-dev] [PATCH 1/2] i965/gen7: Prefer vertical alignment of 4 when possible.

Gen6+ allows for color buffers to use a vertical alignment of either 4 or 2. Previously we defaulted to 2. This may have caused problems on Gen7 because Y-tiled render targets are not allowed to use a vertical alignment of 2. This patch changes the vertical alignment to 4 on Gen7, except for the

[Mesa-dev] [PATCH 2/2] i965/gen7: Disallow Y tiling of renderable surfaces with valign of 2.

Gen7 does not allow render targets to have a vertical alignment of 2. So, when creating a surface, if its format is renderable, and its vertical alignment is 2, force it to use X tiling. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 + 1 file changed, 17 insertions(+) dif

[Mesa-dev] [PATCH 0/2] i965/gen7: vertical alignment fixes.

While working on patch b4c3b83 (i965: Fix vertical alignment for multisampled buffers) I noticed that we were failing to follow another alignment rule: on gen7, render targets using Y tiling must have a vertical alignment of 4. This patch series ensures that we follow that rule by preferring a ver

[Mesa-dev] [Bug 71543] [mesa] Source-based games segfault

https://bugs.freedesktop.org/show_bug.cgi?id=71543 --- Comment #7 from Nikolay Amiantov --- Thanks for the explanation, that looks like it. I've reported a bug to https://github.com/ValveSoftware/Source-1-Games/issues/1548 -- You are receiving this mail because: You are the assignee for the bug

Re: [Mesa-dev] [PATCH 1/2] mesa: Add gl_formats to cover all GLUser provided format/type combinations

On Fri, Nov 15, 2013 at 4:58 AM, Roland Scheidegger wrote: > On 11/14/2013 11:53 PM, Mark Mueller wrote: > >> This and the subsequent patch are the first steps in adding support to >> load textures >> via GPU instead of CPU. This patch expands Mesa's gl_formats such that >> all GLUser >> format/ty

[Mesa-dev] [PATCH] r600g/compute: Fix handling of global buffers in r600_resource_copy_region()

From: Tom Stellard Global buffers do not have an associate cs_buf handle, so we can't copy them using r600_copy_buffer() https://bugs.freedesktop.org/show_bug.cgi?id=64226 CC: "10.0" --- src/gallium/drivers/r600/r600_blit.c | 32 +++- 1 file changed, 31 insertions(

Re: [Mesa-dev] [PATCH] i965/gen7: Emit workaround flush when changing GS enable state.

Paul Berry writes: > v2: Don't go to extra work to avoid extraneous flushes. (Previous > experiments in the kernel have suggested that flushing the pipeline > when it is already empty is extremely cheap). Looks great. Reviewed-by: Eric Anholt pgpwq8qe55KkI.pgp Description: PGP signature ___

[Mesa-dev] [PATCH] i965: Use intel_upload_map/unmap for pull constant uploads.

No difference on GLB2.7 low resolution (n=1885/1886), but that isn't CPU bound anyway at about 20-30% load. Some quick testing of DOTA2 showed no difference (n of either 3 or 5, I forget), but it does cut a bunch of GPU stalls at the start of a match when the GTT is getting cleaned up from all the

[Mesa-dev] [Bug 37253] SIGSEGV in dri2FlushFrontBuffer/MakeContextCurrent

https://bugs.freedesktop.org/show_bug.cgi?id=37253 Bug 37253 depends on bug 33203, which changed state. Bug 33203 Summary: firefox4 segfault in swrastPutImage() (pdraw->psc==NULL) [Gallium 0.4 on llvmpipe] https://bugs.freedesktop.org/show_bug.cgi?id=33203 What|Removed

Re: [Mesa-dev] [PATCH 1/2] mesa: Add gl_formats to cover all GLUser provided format/type combinations

I don't understand this and I don't think this is the right way to implement hw-accelerated TexImage. Some of the formats are unsupported by all hardware I know, others just don't make any sense (e.g. RGBA5999_REV). I think the proper way to implement PBO unpacking is to read the PBO as a TBO. If

[Mesa-dev] [Bug 33203] firefox4 segfault in swrastPutImage() (pdraw->psc==NULL) [Gallium 0.4 on llvmpipe]

https://bugs.freedesktop.org/show_bug.cgi?id=33203 Thierry Vignaud changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [PATCH 1/4] r600g/sb: work around hw issues with stack on eg/cm

From: Vadim Girlin v2: make it actually work, improve condition Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68503 Cc: "10.0" Signed-off-by: Vadim Girlin --- src/gallium/drivers/r600/sb/sb_bc.h| 21 src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 129 +

Re: [Mesa-dev] [PATCH] dri-vmwgfx: add __driDriverGetExtensions_vmwgfx() function

- Original Message - > To resolve missing symbol since the DRI driver rearchitecting. > --- > src/gallium/targets/dri-vmwgfx/target.c | 16 > 1 file changed, 16 insertions(+) > > diff --git a/src/gallium/targets/dri-vmwgfx/target.c > b/src/gallium/targets/dri-vmwgfx/t

Re: [Mesa-dev] [PATCH 0/6 v2] radeon: Plug some memory leaks

On Wed, Nov 06, 2013 at 04:49:18PM -0600, Aaron Watry wrote: > Turns out that I don't have commit access to Mesa, just piglit. Feel > free to push if they look good. > > I decided to have some fun and hooked valgrind up to my SI while running > a few OpenCL tests in piglit. This is the first batc

Re: [Mesa-dev] [PATCH] i965: Fix vertical alignment for multisampled buffers.

On 12 November 2013 15:15, Paul Berry wrote: > On 12 November 2013 15:02, Kenneth Graunke wrote: > >> On 11/12/2013 01:29 PM, Paul Berry wrote: >> > From the Sandy Bridge PRM, Vol 1 Part 1 7.18.3.4 (Alignment Unit >> > Size): >> > >> > j [vertical alignment] = 4 for any render target surface

Re: [Mesa-dev] [PATCH] indices: add comments, assertions in u_indices.c file

On 11/13/2013 06:38 PM, Brian Paul wrote: --- src/gallium/auxiliary/indices/u_indices.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/src/gallium/auxiliary/indices/u_indices.c b/src/gallium/auxiliary/indices/u_indices.c index 30b54b9..1b33f41 100644 --- a/s

Re: [Mesa-dev] [PATCH 2/2] svga: print warning for unsupported indirect dest reg indexing

On 11/14/2013 09:33 PM, Brian Paul wrote: For DX9-level shaders, there's only limited support for indirect indexing of registers (with the loop counter register, not the general address register.) --- src/gallium/drivers/svga/svga_tgsi_insn.c |4 1 file changed, 4 insertions(+) diff

Re: [Mesa-dev] [PATCH] svga: do primitive trimming in translate_indices()

- Original Message - > The index translation code expects the number of indexes to be > consistent with the primitive type (ex: a multiple of 3 for > PIPE_PRIM_TRIANGLES). If it's not, we can write out of bounds > in the destination buffer. > > Fixes failed assertions in the pipebuffer

[Mesa-dev] [Bug 71543] [mesa] Source-based games segfault

https://bugs.freedesktop.org/show_bug.cgi?id=71543 Alexander Monakov changed: What|Removed |Added CC||amona...@gmail.com --- Comment #6 fr

Re: [Mesa-dev] [PATCH 1/2] mesa: Add gl_formats to cover all GLUser provided format/type combinations

On 11/14/2013 11:53 PM, Mark Mueller wrote: This and the subsequent patch are the first steps in adding support to load textures via GPU instead of CPU. This patch expands Mesa's gl_formats such that all GLUser format/type combinations are represented and thus can be communicated to lower leve

Re: [Mesa-dev] [PATCH] r600/llvm: Store inputs in function arguments

sorry, mailer program ate the cc list... Hi, Am Donnerstag, 14. November 2013, 10:24:52 schrieb Andy Furniss: > Vincent Lejeune wrote: > > --- > > > > src/gallium/drivers/r600/r600_llvm.c | 119 > > +++ src/gallium/drivers/r600/r600_shader.c > >| 1 + > >

[Mesa-dev] [Bug 71543] [mesa] Source-based games segfault

https://bugs.freedesktop.org/show_bug.cgi?id=71543 --- Comment #5 from Nikolay Amiantov --- Maybe I should post a bug to Valve, too, but with old revision of Mesa this do not happen. What else can I do to help identify cause of this? -- You are receiving this mail because: You are the assignee

Re: [Mesa-dev] [PATCH] r600/llvm: Store inputs in function arguments

Hi, Am Donnerstag, 14. November 2013, 10:24:52 schrieb Andy Furniss: > Vincent Lejeune wrote: > > --- > > > > src/gallium/drivers/r600/r600_llvm.c | 119 > > +++ src/gallium/drivers/r600/r600_shader.c > >| 1 + > > src/gallium/drivers/radeon/radeon_llvm.

[Mesa-dev] [Bug 71543] [mesa] Source-based games segfault

https://bugs.freedesktop.org/show_bug.cgi?id=71543 --- Comment #4 from Alexander Monakov --- As you can see in the backtrace, libudev.so.0 from Steam runtime calls into your system libudev.so.1. That definitely is not supposed to happen and can lead to a segfault. -- You are receiving this mai

[Mesa-dev] [Bug 71543] [mesa] Source-based games segfault

https://bugs.freedesktop.org/show_bug.cgi?id=71543 Nikolay Amiantov changed: What|Removed |Added Hardware|x86 (IA32) |x86-64 (AMD64) Assignee|dri

Re: [Mesa-dev] [PATCH] i965: Add missing break in SHADER_OPCODE_GEN7_SCRATCH_READ case.

On Thu, Nov 14, 2013 at 10:51 PM, Vinson Lee wrote: > Fixes "Missing break in switch" defect reported by Coverity. > > Signed-off-by: Vinson Lee > --- > src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/br