Re: [Mesa-dev] Backends and support for pow-instructions

On Fri, Jul 18, 2014 at 3:25 PM, Marek Olšák mar...@gmail.com wrote: BTW, I have just noticed r600g also lowers POW and there is no mention of POW in the SI ISA guide either, so I don't think radeons would benefit from an optimization pass that adds POW instructions. Sure. We could of course

[Mesa-dev] [PATCH] mesa: Don't use memcpy() in _mesa_texstore() for depth texture data

because depth texture data needs clamping to [0.0, 1.0]. Let the _mesa_texstore() fallback to slower path. Fixes Khronos GLES3 CTS tests: shadow_execution_vert shadow_execution_frag Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Anuj Phogat anuj.pho...@gmail.com ---

Re: [Mesa-dev] Backends and support for pow-instructions

There already is an option: gl_shader_compiler_options::EmitNoPow, but st/mesa never sets it to GL_TRUE. Marek On Sat, Jul 19, 2014 at 12:38 AM, Matt Turner matts...@gmail.com wrote: On Fri, Jul 18, 2014 at 3:25 PM, Marek Olšák mar...@gmail.com wrote: BTW, I have just noticed r600g also lowers

Re: [Mesa-dev] [PATCH 22/26] glsl: Store ir_variable::ir_type in 8 bits instead of 32

On Mon, Jul 14, 2014 at 3:48 PM, Ian Romanick i...@freedesktop.org wrote: From: Ian Romanick ian.d.roman...@intel.com No change Valgrind massif results for a trimmed apitrace of dota2. Signed-off-by: Ian Romanick ian.d.roman...@intel.com --- src/glsl/ir.h | 5 +++-- 1 file changed, 3

Re: [Mesa-dev] [PATCH 00/26] GLSL memory diet

On Tue, Jul 15, 2014 at 10:37 AM, Matt Turner matts...@gmail.com wrote: On Mon, Jul 14, 2014 at 3:48 PM, Ian Romanick i...@freedesktop.org wrote: Most of these patches have been sent to the list already in one form or another. There are a few changes, removals, and additions. The series has

Re: [Mesa-dev] [PATCH 22/26] glsl: Store ir_variable::ir_type in 8 bits instead of 32

On Fri, Jul 18, 2014 at 4:33 PM, Matt Turner matts...@gmail.com wrote: On Mon, Jul 14, 2014 at 3:48 PM, Ian Romanick i...@freedesktop.org wrote: From: Ian Romanick ian.d.roman...@intel.com No change Valgrind massif results for a trimmed apitrace of dota2. Signed-off-by: Ian Romanick

Re: [Mesa-dev] [PATCH 25/26] glsl: Keep common variable names in static storage

On Mon, Jul 14, 2014 at 3:48 PM, Ian Romanick i...@freedesktop.org wrote: From: Ian Romanick ian.d.roman...@intel.com Valgrind massif results for a trimmed apitrace of dota2: ntime(i) total(B) useful-heap(B) extra-heap(B)stacks(B) Before (32-bit): 52

[Mesa-dev] Mesa 10.2.4

Mesa 10.2.4 has been released. Mesa 10.2.4 is a bug fix release fixing bugs since the 10.2.3 release, (see below for a list of changes). The tag in the git repository for Mesa 10.2.4 is 'mesa-10.2.4'. Mesa 10.2.4 is available for download at ftp://freedesktop.org/pub/mesa/10.2.4/ SHA-256

[Mesa-dev] [Bug 81500] wrong color in flightgear for the c172p if Atmospheric light scattering is used

https://bugs.freedesktop.org/show_bug.cgi?id=81500 --- Comment #11 from Barto mister.free...@laposte.net --- I manage to find the commit who triggers the bug : it's the commit d030a3404ca0fedf365cb0fd41eaad7abc8ff132 linker: Sort shader I/O variables into a canonical order v2: Rebase on

[Mesa-dev] [Bug 81500] wrong color in flightgear for the c172p if Atmospheric light scattering is used

https://bugs.freedesktop.org/show_bug.cgi?id=81500 Barto mister.free...@laposte.net changed: What|Removed |Added Attachment #103066|0 |1 is obsolete|

Re: [Mesa-dev] [PATCH] mesa: Don't use memcpy() in _mesa_texstore() for depth texture data

Shouldn't the function return TRUE for floating-point depth textures only? Marek On Sat, Jul 19, 2014 at 12:53 AM, Anuj Phogat anuj.pho...@gmail.com wrote: because depth texture data needs clamping to [0.0, 1.0]. Let the _mesa_texstore() fallback to slower path. Fixes Khronos GLES3 CTS

Re: [Mesa-dev] [PATCH 1/3] winsys/radeon: Query the kernel for the number of SEs and SHs per SE

Reviewed-by: Marek Olšák marek.ol...@amd.com Marek On Fri, Jul 18, 2014 at 9:09 PM, Tom Stellard thomas.stell...@amd.com wrote: --- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 6 ++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 2 ++ 2 files changed, 8 insertions(+) diff

Re: [Mesa-dev] [PATCH 2/3] radeonsi/compute: Bump number of user sgprs for LLVM 3.5

Reviewed-by: Marek Olšák marek.ol...@amd.com Marek On Fri, Jul 18, 2014 at 9:09 PM, Tom Stellard thomas.stell...@amd.com wrote: --- src/gallium/drivers/radeonsi/si_compute.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c

Re: [Mesa-dev] [PATCH 2/3] radeonsi: Use util_memcpy_cpu_to_le32()

Reviewed-by: Marek Olšák marek.ol...@amd.com Marek On Fri, Jul 18, 2014 at 9:10 PM, Tom Stellard thomas.stell...@amd.com wrote: --- src/gallium/drivers/radeonsi/si_descriptors.c | 4 +--- src/gallium/drivers/radeonsi/si_shader.c | 8 +--- 2 files changed, 2 insertions(+), 10

Re: [Mesa-dev] [PATCH 0/5] radeon: Write-combined CPU mappings of BOs in GTT

On 19.07.2014 00:47, Christian König wrote: Am 18.07.2014 05:07, schrieb Michel Dänzer: [PATCH 5/5] drm/radeon: Use VRAM for indirect buffers on = SI I'm still not very keen with this change since I still don't understand the reason why it's faster than with GTT. Definitely needs more testing

Re: [Mesa-dev] [PATCH 04/12] main/formats: Add layout and swizzle information

On Fri, Jul 18, 2014 at 2:10 PM, Marek Olšák mar...@gmail.com wrote: On Thu, Jul 17, 2014 at 8:04 PM, Jason Ekstrand ja...@jlekstrand.net wrote: Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com --- src/mesa/main/format_info.py | 11 +++ src/mesa/main/formats.c | 46

[Mesa-dev] [PATCH] i965: Accelerate uploads of RGBA and BGRA GL_UNSIGNED_INT_8_8_8_8_REV textures

Since intel is always going to be little-endian, GL_UNSIGNED_INT_8_8_8_8_REV is the same as GL_BYTE for RGBA and BGRA textures, so the same acceleration code will work. We might as well use it. --- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 6 +- 1 file changed, 5 insertions(+), 1

[Mesa-dev] [Bug 81500] wrong color in flightgear for the c172p if Atmospheric light scattering is used

https://bugs.freedesktop.org/show_bug.cgi?id=81500 --- Comment #13 from Barto mister.free...@laposte.net --- Created attachment 103069 -- https://bugs.freedesktop.org/attachment.cgi?id=103069action=edit reverse the commit d030a3404ca0fedf365cb0fd41eaad7abc8ff132 this patch has been tested with

[Mesa-dev] [PATCH V2] glsl: remove unnecessary check

This code does nothing useful as the next recursive call on the array element will override any null values if the element is a record anyway. The code is also not doing what the comment says as its trying to set the record type pointer for only the first element of the array not the first leaf

Re: [Mesa-dev] Backends and support for pow-instructions

FWIW, nv50/nvc0 also don't have pow instructions (looks like the last nvidia card with a pow instruction was the GeForce FX series, first released in 2003... even nv40 doesn't have it). The nouveau codegen will happily lower pow's though. However would be nice to avoid the double-work. On Fri,

Re: [Mesa-dev] [PATCH V2] glsl: remove unnecessary check

On Sat, 2014-07-19 at 12:25 +1000, Timothy Arceri wrote: This code does nothing useful as the next recursive call on the array element will override any null values if the element is a record anyway. The code is also not doing what the comment says as its trying to set the record type pointer

[Mesa-dev] [Bug 80266] Many instances of 131, which is undefined in C99

https://bugs.freedesktop.org/show_bug.cgi?id=80266 --- Comment #16 from Vittorio zec...@gmail.com --- If comment #15 is directed to me, I believe I already did my part by exposing this issue on mesa bugzilla. The C99 standard clearly states that such shifts are undefined and then against the

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