https://bugs.freedesktop.org/show_bug.cgi?id=84145
Ilia Mirkin imir...@alum.mit.edu changed:
What|Removed |Added
Status|NEW |RESOLVED
https://bugs.freedesktop.org/show_bug.cgi?id=84355
Priority: medium
Bug ID: 84355
Assignee: mesa-dev@lists.freedesktop.org
Summary: texture2DProjLod and textureCubeLod are not supported
when using GLES.
Severity: normal
On Friday, August 29, 2014 11:10:48 PM Kenneth Graunke wrote:
This is easy: we just need to use brw_map_bo instead of mapping it
directly.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 7 ---
1 file changed, 4
https://bugs.freedesktop.org/show_bug.cgi?id=84355
kalyank kondapallykalyancontrib...@gmail.com changed:
What|Removed |Added
Hardware|Other |x86 (IA32)
https://bugs.freedesktop.org/show_bug.cgi?id=84355
Kenneth Graunke kenn...@whitecape.org changed:
What|Removed |Added
Assignee|mesa-dev@lists.freedesktop.
On Thu, Sep 25, 2014 at 12:55:40PM -0700, Tom Stellard wrote:
This is the only guaranteed way get the patch level for llvm,
since the define cannot always be found in config.h depending
on the version of llvm or the build system used.
CC: mesa-sta...@lists.freedesktop.org
Reviewed-by:
How about assuming for each CS that it can use the compute ring and as
soon as we submit a PM4 command that can only be executed on the
graphics ring note that this CS needs to be executed on the graphics ring?
Just an idea,
Christian.
Am 25.09.2014 um 21:02 schrieb Tom Stellard:
On Mon, Sep
Hi Leo,
On 25/09/14 15:21, Liu, Leo wrote:
Hi Gwenole and Emil,
[...]
the reason for $(LIBVA_LIBS) is for xcb lib, from configure.ac
+PKG_CHECK_MODULES([LIBVA], [libva = 0.35.0 x11-xcb xcb-dri2 =
$XCBDRI2_REQUIRED])
I will separate them, and remove libva for link.
I've completely
Original patch by Petri Latvala petri.latv...@intel.com:
Add an optimization pass that drops min/max expression operands that
can be proven to not contribute to the final result. The algorithm is
similar to alpha-beta pruning on a minmax search, from the field of
AI.
This optimization pass can
On Thu, Sep 25, 2014 at 3:02 PM, Tom Stellard t...@stellard.net wrote:
On Mon, Sep 22, 2014 at 09:48:43PM +0200, Marek Olšák wrote:
No, we cannot detect compute-only contexts yet. We need to add a new
parameter to pipe_context::context_create which says that a context is
compute-only. That
Okay... I screwed up this morning. I pushed a set of four patches
without adding Jordan's Reviewed-by. Realizing the error, I quickly
added the R-b to each commit and force-pushed the changes.
If you pushed something in the intervening 2 minutes, it got lost.
On 09/26/2014 08:00 AM, Ian
On Fri, Aug 29, 2014 at 11:10:48PM -0700, Kenneth Graunke wrote:
This is easy: we just need to use brw_map_bo instead of mapping it
directly.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviwed-by: Kristian Høgsberg k...@bitplanet.net
---
On Fri, Aug 29, 2014 at 11:10:49PM -0700, Kenneth Graunke wrote:
We don't really want extra buffer copying or stalls when mapping,
so it'd be nice to know when it's happening.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
On Fri, Sep 26, 2014 at 08:36:39AM -0700, Kristian Høgsberg wrote:
On Fri, Aug 29, 2014 at 11:10:49PM -0700, Kenneth Graunke wrote:
We don't really want extra buffer copying or stalls when mapping,
so it'd be nice to know when it's happening.
Signed-off-by: Kenneth Graunke
Our current atan()-approximation is pretty inaccurate at 1.0, so
let's try to improve the situation by doing a direct approximation
without going through atan.
This new implementation uses an 11th degree polynomial to approximate
atan in the [-1..1] range, and the following identitiy to reduce
On Fri, Aug 29, 2014 at 11:10:50PM -0700, Kenneth Graunke wrote:
There's no reason to stall on pwrite - the CPU always appends to the
buffer and never modifies existing contents, and the GPU never writes
it. Further, the CPU always appends new data before submitting a batch
that requires it.
On Fri, Sep 26, 2014 at 12:38 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On Friday, August 29, 2014 11:10:48 PM Kenneth Graunke wrote:
This is easy: we just need to use brw_map_bo instead of mapping it
directly.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
On Fri, Sep 26, 2014 at 9:02 AM, Iago Toral Quiroga ito...@igalia.com wrote:
Original patch by Petri Latvala petri.latv...@intel.com:
Add an optimization pass that drops min/max expression operands that
can be proven to not contribute to the final result. The algorithm is
similar to
On gen 7, the MRF was removed and we gained the ability to do send
instructions directly from the GRF. This commit enables that functinoality
for FB writes.
v2: Make handling of components more sane.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 +
src/mesa/drivers/dri/i965/brw_fs.h
This commit uses a 16-wide MRF instead of a hardware register when setting
up math instructions and properly sets the base_mrf on the second emitted
instruction.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
2 files changed, 2
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 61 ++-
1 file changed, 48 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 567f8e2..8d96906 100644
---
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 56 +++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 444cc32..4d97594 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
This commit reworks copy propagation a bit to support propagating the
copying of partial registers. This comes up every time we have pull
constants because we do a pull constant read immediately followed by a move
to splat the one component of the out to 8 or 16-wide. This allows us to
eliminate
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 15 +++
src/mesa/drivers/dri/i965/brw_fs.h | 22 +-
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 97b21e3..b43032b
Now that we have execution sizes, we can use that instead of the dispatch
width. This way it also works for 8-wide instructions in SIMD16.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_fs.h| 4 ++--
---
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 7dfed6e..6b7ec79 100644
---
v2: Renamed the array for the range mappings and added a comment.
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 34 ++-
src/mesa/drivers/dri/i965/intel_screen.h | 10 +++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git
v2: Account for register ranges due to the rebase on top of the patch to
propagate subsets of copied registers
---
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 40 ++
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git
On Tue, Sep 23, 2014 at 5:38 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
Variables are used in later patches to implement
EXT_framebuffer_multisample_blit_scaled extension.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/main/mtypes.h | 9 +
1 file changed, 9
On Fri, Sep 26, 2014 at 12:50 PM, Jordan Justen jljus...@gmail.com wrote:
On Tue, Sep 23, 2014 at 5:38 PM, Anuj Phogat anuj.pho...@gmail.com
wrote:
Variables are used in later patches to implement
EXT_framebuffer_multisample_blit_scaled extension.
Signed-off-by: Anuj Phogat
From: Christian König christian.koe...@amd.com
This patch is for application to query configuration,
such as profiles, entrypoints, and attributes
v2: fix missing profile with query
Signed-off-by: Michael Varga michael.va...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
This patch implements functions for images support,
which basically supports copy data between video
surface and user buffers, in this case supports
SW decode, and other video output
v2: fix buffer size for odd-sized image case
expose I420 format as well
Signed-off-by: Leo Liu
From: Christian König christian.koe...@amd.com
This patch adds a skeleton VA-API state tracker,
which is filled with live in the subsequent patches.
v2: fixes in configure.ac and va state_tracker Makefile.am
v3: configure.ac:
generate a marco for link to xcb
auto-dectecting VA
On Fri, Sep 26, 2014 at 4:30 PM, Leo Liu leo@amd.com wrote:
This patch implements functions for images support,
which basically supports copy data between video
surface and user buffers, in this case supports
SW decode, and other video output
v2: fix buffer size for odd-sized image case
---
src/mesa/drivers/dri/common/xmlpool/es.po | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/common/xmlpool/es.po
b/src/mesa/drivers/dri/common/xmlpool/es.po
index 1733b76..a68c329 100644
--- a/src/mesa/drivers/dri/common/xmlpool/es.po
+++
---
src/mesa/drivers/dri/common/xmlpool/ca.po | 119 --
src/mesa/drivers/dri/common/xmlpool/de.po | 118 -
src/mesa/drivers/dri/common/xmlpool/es.po | 118 -
src/mesa/drivers/dri/common/xmlpool/fr.po | 118
---
src/mesa/drivers/dri/common/xmlpool/ca.po | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/common/xmlpool/ca.po
b/src/mesa/drivers/dri/common/xmlpool/ca.po
index 1db9703..23e9f42 100644
--- a/src/mesa/drivers/dri/common/xmlpool/ca.po
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mapi/glapi/gen/gl_x86_asm.py | 2 +-
src/mesa/main/dlopen.h| 7 ---
src/mesa/main/texcompress_s3tc.c | 2 --
src/mesa/x86/assyntax.h | 6 +++---
src/mesa/x86/read_rgba_span_x86.S | 4 ++--
5 files changed, 6
Added back in 2009, with osmesa/GLU in mind. Unlikely to be working
any more since the removal of the static makefiles.
Cc: Brian Paul bri...@vmware.com
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/main/compiler.h | 2 +-
src/mesa/main/dlopen.h | 12 +++-
2 files
On Friday, September 26, 2014 09:22:31 AM Kristian Høgsberg wrote:
On Fri, Aug 29, 2014 at 11:10:50PM -0700, Kenneth Graunke wrote:
There's no reason to stall on pwrite - the CPU always appends to the
buffer and never modifies existing contents, and the GPU never writes
it. Further, the
Patches 2-4 are
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
I'll have to think more about patch 1
On Mon, Sep 8, 2014 at 12:21 PM, Matt Turner matts...@gmail.com wrote:
---
src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp | 3 +--
1 file changed, 1 insertion(+), 2
On Friday, September 26, 2014 04:41:14 PM Chris Wilson wrote:
On Fri, Sep 26, 2014 at 08:36:39AM -0700, Kristian Høgsberg wrote:
On Fri, Aug 29, 2014 at 11:10:49PM -0700, Kenneth Graunke wrote:
We don't really want extra buffer copying or stalls when mapping,
so it'd be nice to know when
And I was just going to start working on the Mesa software rasterizer
for DOS. Oh well.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 09/26/2014 02:14 PM, Emil Velikov wrote:
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mapi/glapi/gen/gl_x86_asm.py | 2 +-
On 09/26/2014 02:14 PM, Emil Velikov wrote:
Added back in 2009, with osmesa/GLU in mind. Unlikely to be working
any more since the removal of the static makefiles.
Cc: Brian Paul bri...@vmware.com
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-by: Ian Romanick
Now that the bitfield is a uint64_t, we should use 1ull. Currently, we
only have 32 entries, so 1 works fine, but it's not future-proof.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_context.h | 64 -
1 file changed, 32
This function flagged BRW_NEW_*_PROGRAM
When ctx-{Vertex,Geometry,Fragment}Program._Current changes, core Mesa
calls the BindProgram driver hook, which flagged BRW_NEW_*_PROGRAM.
However, brw_upload_state also checks for that changing, sets the same
flags, and also updates brw-fragment_program
Unused since krh rewrote fast clears to use meta.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_context.h | 2 --
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 -
2 files changed, 3 deletions(-)
diff --git
This will keep INTEL_DEBUG=state working when we add BRW_NEW_* bits
beyond 1 31. We missed doing this when widening the driver flags
from uint32_t to uint64_t.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ++--
1 file changed, 2
I had to dig a bit to figure out why this was necessary.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 5 +++--
src/mesa/drivers/dri/i965/gen7_sf_state.c | 4 ++--
src/mesa/drivers/dri/i965/gen8_sf_state.c | 4 ++--
3 files changed, 7
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ffe8ba8..95af5ab 100644
---
On Fri, Sep 26, 2014 at 2:21 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On Friday, September 26, 2014 09:22:31 AM Kristian Høgsberg wrote:
On Fri, Aug 29, 2014 at 11:10:50PM -0700, Kenneth Graunke wrote:
There's no reason to stall on pwrite - the CPU always appends to the
buffer and
Cuts the number of i965 color calculator viewport uploads by 100x
(11017983 - 113385) in 'x11perf -gc' with Glamor in Xephyr.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/main/viewport.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/main/viewport.c
I believe when I wrote this code, gen6_sf_state used CACHE_NEW_VS_PROG,
which has since been replaced by BRW_NEW_VUE_MAP_GEOM_OUT. It's not
needed here anyway - only SBE needs it. Just a copy and paste mistake.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
On Fri, Sep 26, 2014 at 2:59 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
On Fri, Sep 26, 2014 at 3:04 PM, Alex Deucher alexdeuc...@gmail.com wrote:
On Thu, Sep 25, 2014 at 3:02 PM, Tom Stellard t...@stellard.net wrote:
On Mon, Sep 22, 2014 at 09:48:43PM +0200, Marek Olšák wrote:
No, we cannot detect compute-only contexts yet. We need to add a new
parameter to
On 09/26/2014 04:13 PM, Kenneth Graunke wrote:
Cuts the number of i965 color calculator viewport uploads by 100x
(11017983 - 113385) in 'x11perf -gc' with Glamor in Xephyr.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/main/viewport.c | 6 ++
1 file changed, 6
This will keep INTEL_DEBUG=state working when we add BRW_NEW_* bits
beyond 1 31. We missed doing this when widening the driver flags
from uint32_t to uint64_t.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 23 +++
1
~0 is 0x, which only covers the first 32 bits. We need all 64.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_state_cache.c | 2 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ++--
3
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b9bd94c..97b39e1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++
On Fri, Sep 26, 2014 at 7:09 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b9bd94c..97b39e1
On Fri, Sep 26, 2014 at 4:09 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b9bd94c..97b39e1
Series is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 09/26/2014 03:13 PM, Kenneth Graunke wrote:
I believe when I wrote this code, gen6_sf_state used CACHE_NEW_VS_PROG,
which has since been replaced by BRW_NEW_VUE_MAP_GEOM_OUT. It's not
needed here anyway - only SBE needs it.
Series is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 09/26/2014 02:53 PM, Kenneth Graunke wrote:
Unused since krh rewrote fast clears to use meta.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_context.h | 2 --
On Fri, Sep 26, 2014 at 4:09 PM, Kenneth Graunke kenn...@whitecape.org wrote:
~0 is 0x, which only covers the first 32 bits. We need all 64.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
... which leads to incorrect results on 32-bit x86.
Reported-by: Mark Janes mark.a.ja...@intel.com
---
I tried writing up a nice commit message that explained what was going
on and why this worked on 64-bit, but then I realized that it was taking
orders of magnitude longer than the fix itself and
Signed-off-by: Timothy Arceri t_arc...@yahoo.com.au
---
src/glsl/ast_to_hir.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 5ec1614..1c1815b 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@
This adds support for arrays of arrays and simplifies the check for gs and ts.
Signed-off-by: Timothy Arceri t_arc...@yahoo.com.au
---
src/glsl/lower_packed_varyings.cpp | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/src/glsl/lower_packed_varyings.cpp
Signed-off-by: Timothy Arceri t_arc...@yahoo.com.au
---
src/glsl/glsl_types.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/glsl/glsl_types.h b/src/glsl/glsl_types.h
index eeb14c2..f1d578e 100644
--- a/src/glsl/glsl_types.h
+++ b/src/glsl/glsl_types.h
@@ -505,7
According to GLES (i.e. 1.0 and above) spec textureCubeLod and
texture2DProjLod are built in functions. We seem to disable support
for these functions with GLES. This patch enables the support.
Signed-off-by: Kalyan Kondapally kalyan.kondapa...@intel.com
Bugzilla:
On Fri, Sep 26, 2014 at 7:44 PM, Kalyan Kondapally
kondapallykalyancontrib...@gmail.com wrote:
According to GLES (i.e. 1.0 and above) spec textureCubeLod and
texture2DProjLod are built in functions. We seem to disable support
for these functions with GLES. This patch enables the support.
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