V2: Add some air for readability
Use the new IS_CONSTANT macro
Combine if-blocks for reduced code-duplication
Split out into separate function for reuse later
V3: Fix flawed logic (Spotted by Bruno)
---
src/glsl/opt_minmax.cpp | 45 +
1
From: Rob Clark robcl...@freedesktop.org
At least temporarily, I need to fallback to old compiler still for
relative dest (for freedreno), but I can do relative src temp. Only
a temporary situation, but seems easy/reasonable for tgsi-scan to
track this.
Signed-off-by: Rob Clark
Update the hw-generated binding table for blorp SURFACE_STATE entries.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 35
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git
The 3DSTATE_GATHER_POOL_ALLOC is used to enable or disable the gather
push constants feature within a context. This patch provides the toggle
functionality of using gather push constants to program constant data
within a batch.
In addition, using gather push constants require that a gather pool
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 1150e3d..df4a0f2 100644
---
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3f31a6f..d0b1eab 100644
---
export INTEL_RESOURCE_STREAMER={0,1} To switch on/off resource streamer.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 6 ++
src/mesa/drivers/dri/i965/brw_context.h | 1 +
2 files changed, 7 insertions(+)
diff --git
Existing state flag cannot publish additional values.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/main/dd.h | 2 +-
src/mesa/main/mtypes.h | 3 ++-
src/mesa/main/state.c | 6 +++---
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into.
Each binding table offset in the binding table pool is unique per
each shader stage that are enabled within a batch.
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 18 +-
1 file changed, 17
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 40 ++
src/mesa/drivers/dri/i965/brw_defines.h| 5
src/mesa/drivers/dri/i965/brw_state.h | 9 ++
3 files changed, 54
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 206a6ff..3d5c7df 100644
---
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.
Note that the the
Uniforms are uploaded to this buffer instead of the space allocated from
the dynamic state base address.
This buffer is sliced into eight 4k-sized banks; each accessible
by SURFACE_STATE entries. These banks are layouted in such a way that all
shader stages can upload to whatever next free bank
Programming null constants with gather constant tables seems to
be unsupported and results in a GPU lockup even with the prescribed
GPU workarounds in the bspec. I found out by trial and error that
disabling the gather constant feature for null constants is the only
way to go around the issue.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 3639ed2..0f2c2c4 100644
---
I sent previous patches enabling hardware-generated binding tables. By itself,
hw-binding tables gave no performance improvements, it is just a means to
an end. However, the real meat of the RS hardware is the optimized ability to
map constants to the GRF.
Gather push constants is basically an
Used to toggle the resource streamer within a batchbuffer
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h
b/src/mesa/drivers/dri/i965/intel_reg.h
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index c581cc0..d48128d 100644
---
Switch off gather push constants in the blorp. Blorp requires only a
a set of simple constants that there is no need for the extra complexity
to program a gather table entry into the pipeline.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
Trigger it when uniforms are updated
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/main/dd.h | 2 ++
src/mesa/main/mtypes.h | 3 +++
src/mesa/main/state.c | 10 +-
src/mesa/main/uniform_query.cpp | 6 ++
4 files
Use the gather table generated from the uniform uploads to gather
and pack the constants to the gather pool. This changes the 3DSTATE_CONSTANT_*
bits to refer to the gather pool instead of the constant buffer pointed
to by an offset of the dynamic state base address.
Signed-off-by: Abdiel
In addition, append the UBO entries to stage_state-push_const_size
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_vs_state.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
Reserve space in the gather pool where the resource streamer will flush
its gather constant data.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_vs_state.c | 8
1 file changed, 8 insertions(+)
diff --git
We set the same 16-register limitation used in assign_constant_locations()
when assigning UBOs as push constants. Otherwise, just fall-back to using
pull constant loads.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 ++-
1
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 8a03581..904c51b 100644
---
When assigning a block of register to normal uniforms, pack the ubo
uniform registers next to it.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git
And vice versa. This allows us to combine UBOs and uniform registers
as push constants.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
A gather push constant table entry is able to fetch in 128-bit
increments from the constant buffer. A channel mask is provided to
narrow down which channels are loaded in that entry. This patch
generates the mask for enabled entries only.
The ir_swizzle visitor which is run prior this function
Now that UBOs are uploaded as push constants. We need to obtain and
append the amount of push constant entries generated by the UBO entry
fetches to the 3DSTATE_CONSTANT_* packets.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 7
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 0f22829..8dee915 100644
---
At the moment, this is only possible if the const block and offset are
immediate values (constants). Otherwise just fall-back to the previous
method of uploading the UBO constant data to GRF using pull constants.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
Determine which shader stage changed their uniforms and only upload
uniforms which belong to it.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_program.c | 9 +
The resource streamer is able to gather and pack sparsely-located
constant data from any buffer object representing a UBO block.
This patch adds support for keeping track of these constant data
fetches into a gather table.
We only allocate a maximum of 128 entries. This limitation is taken
from a
Blanket the ubo blocks with a binding table. Note that the resource
streamer is able to fetch the constant buffers referred to by the gather
table only if it is referenced by the hw-binding table generator.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
Gather table entries were generated previously in the SIMD8 pass.
Just reuse those entries for SIMD16 so we don't generate a duplicate
set of registers.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 13 +
1 file
Now that we are able to use a gather table for fetching UBOs,
make a gather entry based on the table generated by the ir_binop_ubo_load
and uniform loads combined. At the moment, we separate this entry from
the previous uniform-only gather table because the current approach
to pack the uniform and
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index bd9345e..2f592c9 100644
---
Switches on push constants whenever we have UBO entries.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 09d79c8..0f22829 100644
On Sunday 04 January 2015 09:36:40 Aras Pranckevicius wrote:
Hi,
I noticed some GLSL related discussions talk My shader-db is dominated by
TF2, DOTA2, Portal, Brutal Legend and Dungeon Defenders. Maybe
non-Source-engine
games show some benefit from this series?
Now, shader-db that I can
On Sat, 2015-01-03 at 20:18 +0100, Thomas Helland wrote:
V2: Add some air for readability
Use the new IS_CONSTANT macro
Combine if-blocks for reduced code-duplication
Split out into separate function for reuse later
---
src/glsl/opt_minmax.cpp | 33
On 31/12/14 03:42, Ilia Mirkin wrote:
The headers hadn't been regenerated in a long time and had seen a number
of manual modifications. A few changes:
- remove nvc0_2d entirely, use the nv50 header which has the nvc0
values too
- remove 3ddefs, it's identical to the nv50 file
- move
https://bugs.freedesktop.org/show_bug.cgi?id=86837
--- Comment #16 from bgunte...@gmail.com ---
I can also confirm that this patch works.
Running OpenGL version:2.1 Mesa 10.4.0(git-fb3f7c0)
great work!
--
You are receiving this mail because:
You are the assignee for the bug.
Hi Alan,
On 03/01/15 22:28, Alan Coopersmith wrote:
https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.69/html_node/Limitations-of-Usual-Tools.html#index-g_t_0040command_007btr_007d-1842
Without this fix, egl fails to build on Solaris, with the error:
command-line:0:22:
On Wed, Nov 12, 2014 at 11:17:55AM -0800, Kenneth Graunke wrote:
According to the documentation, we need to do a CS stall on every fourth
PIPE_CONTROL command to avoid GPU hangs. The kernel does a CS stall
between batches, so we only need to count the PIPE_CONTROLs in our batches.
v2: Get
https://bugs.freedesktop.org/show_bug.cgi?id=86837
--- Comment #17 from bgunte...@gmail.com ---
(In reply to Andy Furniss from comment #13)
(In reply to Emil Velikov from comment #12)
Seems like Christian dropped the link with the tentative fix.
http://patchwork.freedesktop.org/patch/39400/
I just did a very cursory review. I assume someone smarter than me will do a
real review, but if not, feel free to ping me.
I think all the comments apply to both functions.
On Sat, Jan 03, 2015 at 11:54:15AM -0800, Jason Ekstrand wrote:
From: Sisinty Sasmita Patra sisinty.pa...@intel.com
On Sun, Jan 4, 2015 at 10:20 AM, Kenneth Graunke kenn...@whitecape.org
wrote:
On Sunday 04 January 2015 09:36:40 Aras Pranckevicius wrote:
Is it possible to submit more shaders into whatever shader-db is
typically
used by Mesa developers to test compiler optimizations on? I could
package
up
From: Marek Olšák marek.ol...@amd.com
From GL 4.4 Core profile:
If both PRIMITIVE_RESTART and PRIMITIVE_RESTART_FIXED_INDEX are
enabled, the index value determined by PRIMITIVE_RESTART_FIXED_INDEX is
used. If PRIMITIVE_RESTART_FIXED_INDEX is enabled, primitive restart is not
performed
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +++
src/gallium/auxiliary/tgsi/tgsi_scan.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index eb313e4..6210ebd 100644
From: Marek Olšák marek.ol...@amd.com
From GL 4.4 Core profile:
If both PRIMITIVE_RESTART and PRIMITIVE_RESTART_FIXED_INDEX are
enabled, the index value determined by PRIMITIVE_RESTART_FIXED_INDEX is
used. If PRIMITIVE_RESTART_FIXED_INDEX is enabled, primitive restart is not
performed
From: Marek Olšák marek.ol...@amd.com
Cc: 10.2 10.3 10.4 mesa-sta...@lists.freedesktop.org
---
src/mesa/state_tracker/st_draw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index 64d6ef5..b6ccdd7 100644
FWIW the piglit you posted recently
(arb_draw_indirect-draw-arrays-prim-restart) works with nvc0 with
upstream mesa as-is. (But fails on llvmpipe/softpipe.)
On Sun, Jan 4, 2015 at 4:44 PM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
From GL 4.4 Core profile:
Nice. BTW this patch is unrelated to the test. This patch tries to fix
the fixed index case, while the test only validates normal primitive
restart.
Marek
On Sun, Jan 4, 2015 at 10:54 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
FWIW the piglit you posted recently
assert's get compiled out in release builds, so they can't be relied
upon to perform logic.
Reported-by: Pierre Moreau pierre.mor...@free.fr
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Cc: 10.2 10.3 10.4 mesa-sta...@lists.freedesktop.org
---
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_state_shaders.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index de12b4e..437dd95 100644
---
From: Marek Olšák marek.ol...@amd.com
- the relocs array is unused, remove it
- ndw is at most 115 (init), set 140 as the maximum
- compute needs 4 buffers per state, graphics only needs 1; set 4 as the maximum
---
src/gallium/drivers/radeonsi/si_pm4.c | 6 +-
From: Marek Olšák marek.ol...@amd.com
It really doesn't do anything there.
---
src/gallium/drivers/radeonsi/si_hw_context.c | 3 +--
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_pm4.c| 1 -
From: Marek Olšák marek.ol...@amd.com
Only done for completeness. Not used by anything yet.
Tested by advertising PIPE_CAP_VERTEXID_NOBASE.
---
src/gallium/drivers/radeonsi/si_shader.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
From: Marek Olšák marek.ol...@amd.com
Ordered compares are what you have in C. Unordered compares are the result
of negating ordered compares (they return true if either argument is NaN).
That special NaN behavior is completely useless here, and unordered
compares produce horrible code with all
From: Marek Olšák marek.ol...@amd.com
SPI_PS_IN_CONTROL is moved into the SPI mapping state.
---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state_shaders.c | 20 ++--
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/radeon_llvm_emit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c
b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index dc871d7..e3be72c 100644
---
From: Marek Olšák marek.ol...@amd.com
This can be done using the SPI mapping only. If two_side is disabled,
VS COLOR is loaded to both PS COLOR and PS BCOLOR inputs.
The disadvantage is that the PS always chooses the color according to FACE
even though two_side is disabled.
Since PS color
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_shader.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index eb762c0..aa051cb 100644
---
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_shader.h| 1 -
src/gallium/drivers/radeonsi/si_state_shaders.c | 12 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_pipe.h | 2 --
src/gallium/drivers/radeonsi/si_state.c | 3 +--
src/gallium/drivers/radeonsi/si_state.h | 2 --
3 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
From: Marek Olšák marek.ol...@amd.com
It doesn't do anything useful. And colors are floating-point, so we can use
fs.interp, remove flatshade from the shader key, and rely on the FLAT_SHADE
state only (in the next patch).
---
src/gallium/drivers/radeonsi/si_shader.c | 17 +++--
1
From: Marek Olšák marek.ol...@amd.com
This fixes all failing piglit VertexID tests.
Cc: 10.4 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeonsi/si_shader.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
v2: Instead of telling the driver that the window system ancillaries have
been invalidated (when the driver doesn't know which of its buffers
are the window system's!), introduce a method for invalidating
specific surfaces.
---
src/gallium/include/pipe/p_context.h | 11
Improves framerate of 5 seconds of es2gears by 1.57473% +/- 0.669409%
(n=67).
---
src/gallium/drivers/vc4/vc4_context.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index 62f77b3..4c84bd3 100644
---
On Sunday, January 04, 2015 12:03:01 PM Ben Widawsky wrote:
On Wed, Nov 12, 2014 at 11:17:55AM -0800, Kenneth Graunke wrote:
According to the documentation, we need to do a CS stall on every fourth
PIPE_CONTROL command to avoid GPU hangs. The kernel does a CS stall
between batches, so we
https://bugs.freedesktop.org/show_bug.cgi?id=86837
--- Comment #18 from bgunte...@gmail.com ---
(In reply to bgunteriv from comment #17)
(In reply to Andy Furniss from comment #13)
(In reply to Emil Velikov from comment #12)
Seems like Christian dropped the link with the tentative fix.
Ok, I'm going to try reviewing this again. I'm pasting the latest version
of the file from review/nir-v1 and replying to that so that I won't get
confused between all the various changes and reorganizing things. Here we
go!
/*
* Copyright © 2014 Intel Corporation
*
* Permission is hereby
On 12/16/2014 11:22 PM, Mathias Fröhlich wrote:
Hi,
On Tuesday, December 16, 2014 19:30:04 Mario Kleiner wrote:
Hmm. For benchmarking i think i'd consider that a mild form of cheating.
You get higher fps because you skip processing like the whole gpu blit
overhead and host processing overhead
On 2014-12-29 16:55, Roland Scheidegger wrote:
Am 27.12.2014 um 18:41 schrieb Ilia Mirkin:
On Sat, Dec 27, 2014 at 1:13 AM, Alexander von Gluck IV
kallis...@unixzen.com wrote:
---
src/gallium/state_trackers/hgl/hgl.c | 48
+
1 files changed, 19
On 2014-12-27 11:41, Ilia Mirkin wrote:
On Sat, Dec 27, 2014 at 1:13 AM, Alexander von Gluck IV
kallis...@unixzen.com wrote:
---
src/gallium/state_trackers/hgl/hgl.c | 48
+
1 files changed, 19 insertions(+), 29 deletions(-)
diff --git
On 2015-01-03 10:00, Emil Velikov wrote:
On 02/01/15 04:14, Jeremy Huddleston Sequoia wrote:
This is certainly not the best solution to the problem, so I'm just
sending this patch to the list to get the discussion started on the
best way to solve this problem. Currently, any platform that
On Sunday, January 04, 2015 10:44:17 PM Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
From GL 4.4 Core profile:
If both PRIMITIVE_RESTART and PRIMITIVE_RESTART_FIXED_INDEX are
enabled, the index value determined by PRIMITIVE_RESTART_FIXED_INDEX is
used. If
On Sunday, January 04, 2015 04:04:19 PM Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into.
Each binding table offset in the binding table pool
Oh, and I forgot... can we rename this to lower_local_to_regs_scalar or at
least add a note that this won't work for vec4 backends yet due to the
different indexing?
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
---
src/glsl/Makefile.sources | 1
I'd also like to rename or at least note that this is a scalar-only thing
for now... otherwise,
Reviewed-by: Connor Abbott cwabbo...@gmail.com
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h |
I'm not so sure how I feel about checking that outputs are write-only...
eventually we'll want to do lower_input_reads in NIR itself, at which point
we'll need to remove that part from the validator. At the same time, for
now this is somewhat useful. I'm just not sure if it's worth it (making
sure
Reviewed-by: Connor Abbott cwabbo...@gmail.com
Nice job getting this variable lowering stuff all done!
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
This commit switches us over to the new variable lowering code which is
capable of properly handling lowering
Reviewed-by: Connor Abbott cwabbo...@gmail.com
Nice to see that this idea worked out well!
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
We used to have the number of components built into the intrinsic. This
meant that all of our load/store intrinsics had vec1,
Reviewed-by: Connor Abbott cwabbo...@gmail.com
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
---
src/glsl/Makefile.sources |1 -
src/glsl/nir/nir_lower_variables_scalar.c | 1249
-
2 files changed, 1250
This is a general question for the interpolation support:
Why are we using the variable-based intrinsics directly, instead of
lowering it to something index-based in the lower_io pass just like we do
for normal inputs?
On Tue, Dec 16, 2014 at 1:12 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
On Tue, Dec 16, 2014 at 1:12 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
---
src/glsl/nir/nir_intrinsics.h | 32 +++-
src/glsl/nir/nir_lower_io.c | 16 ++--
2 files changed, 21 insertions(+), 27 deletions(-)
diff --git
On Sunday, January 04, 2015 04:04:33 PM Abdiel Janulgue wrote:
Existing state flag cannot publish additional values.
That's not quite true - there are actually two available bits.
However, I don't think we should be adding _NEW_WHATEVER flags. These are
basically for Mesa internals, and we've
On Sunday, January 04, 2015 04:04:36 PM Abdiel Janulgue wrote:
Determine which shader stage changed their uniforms and only upload
uniforms which belong to it.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h| 2 +
src/glsl/nir/nir_lower_global_vars_to_local.c | 107
++
3 files changed, 110
On Sunday, January 04, 2015 04:04:20 PM Abdiel Janulgue wrote:
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
On Sunday, January 04, 2015 04:04:24 PM Abdiel Janulgue wrote:
Update the hw-generated binding table for blorp SURFACE_STATE entries.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 35
1 file
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_lower_locals_to_regs.c | 313
3 files changed, 316
Except for the minor stale comment and assuming you checked that we don't
call nir_create_local_reg() anymore,
Reviewed-by: Connor Abbott cwabbo...@gmail.com
On Tue, Dec 16, 2014 at 1:11 AM, Jason Ekstrand ja...@jlekstrand.net
wrote:
With this commit, the GLSL IR - NIR pass generates NIR in
On Sunday, January 04, 2015 04:04:37 PM Abdiel Janulgue wrote:
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
On Sunday, January 04, 2015 04:04:42 PM Abdiel Janulgue wrote:
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
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