---
src/gallium/state_trackers/clover/Makefile.sources | 1 -
src/gallium/state_trackers/clover/api/program.cpp | 14 +-
.../state_trackers/clover/core/compiler.hpp| 4 +-
src/gallium/state_trackers/clover/core/error.hpp | 2 -
src/gallium/state_trackers/clover/core/kernel.cpp
On Tue, Apr 28, 2015 at 02:45:27PM -0700, Kenneth Graunke wrote:
> On Wednesday, April 22, 2015 11:47:33 PM Topi Pohjolainen wrote:
> > Also changed a couple of direct shifts into SET_FIELD().
> >
> > Signed-off-by: Topi Pohjolainen
> > ---
> > src/mesa/drivers/dri/i965/brw_context.h |
https://bugs.freedesktop.org/show_bug.cgi?id=90207
José Fonseca changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=90207
--- Comment #16 from Tapani Pälli ---
(In reply to José Fonseca from comment #13)
> I think I figured out the problem.
>
> As commented on DECL_RESOURCE_FUNC macro, the RESOURCE_VAR inline function
> is not type safe, and stuff that's not a ir_v
Argh, this is exactly what I had in mind and I did it with
_mesa_longest_attribute_name_length but forgot it in
_mesa_count_active_attribs ... many thanks for catching this. I agree on
the assertion change, that is simple and will make these bugs much
easier to catch.
My overall plan is to
On Tue, Apr 28, 2015 at 03:01:43PM -0700, Kenneth Graunke wrote:
> On Wednesday, April 22, 2015 11:47:34 PM Topi Pohjolainen wrote:
> > Signed-off-by: Topi Pohjolainen
> > ---
> > src/mesa/drivers/dri/i965/brw_state.h | 8 +
> > src/mesa/drivers/dri/i965/gen6_wm_state.c | 56
> > +++
On Tue, Apr 28, 2015 at 03:17:30PM -0700, Kenneth Graunke wrote:
> On Thursday, April 23, 2015 09:00:28 PM Topi Pohjolainen wrote:
> > Signed-off-by: Topi Pohjolainen
> > ---
> > src/mesa/drivers/dri/i965/brw_blorp.h| 4 +++-
> > src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +--
https://bugs.freedesktop.org/show_bug.cgi?id=90207
--- Comment #15 from Dieter Nützel ---
(In reply to Aaron Watry from comment #14)
> (In reply to José Fonseca from comment #13)
> > I think I figured out the problem.
> >
> > As commented on DECL_RESOURCE_FUNC macro, the RESOURCE_VAR inline func
On Tue, Apr 28, 2015 at 6:17 PM, Rogovin, Kevin wrote:
> Hello,
>
>
>> No, because the non-shared code is (by your own admission) untested and/or
>> dead code. Untested code is broken code. I would personally be ok with a
>> lot > of the changes that just replace fb->Width with
>> _mesa_geomet
Hello,
> No, because the non-shared code is (by your own admission) untested and/or
> dead code. Untested code is broken code. I would personally be ok with a
> lot > of the changes that just replace fb->Width with
> _mesa_geometric_width(fb) since it's effectively just replacing a direct
>
On Tue, Apr 28, 2015 at 6:08 PM, Ilia Mirkin wrote:
> On Tue, Apr 28, 2015 at 9:03 PM, Matt Turner wrote:
>> On Tue, Apr 28, 2015 at 5:23 PM, Ilia Mirkin wrote:
>>> Yes, sorry, thought that was implied since I had given it earlier
>>> pending my (as it turns out, incorrect) suggestion.
>>
>> A n
On Tue, Apr 28, 2015 at 9:03 PM, Matt Turner wrote:
> On Tue, Apr 28, 2015 at 5:23 PM, Ilia Mirkin wrote:
>> Yes, sorry, thought that was implied since I had given it earlier
>> pending my (as it turns out, incorrect) suggestion.
>
> A number of people have been confused (rightly so) by "LGTM" im
On Tue, Apr 28, 2015 at 5:23 PM, Ilia Mirkin wrote:
> Yes, sorry, thought that was implied since I had given it earlier
> pending my (as it turns out, incorrect) suggestion.
A number of people have been confused (rightly so) by "LGTM" implying
Reviewed-by. Let's please not ever start implying or
if (blend_per_rt(ctx) || colormask_per_rt(ctx)) {
num_state = ctx->Const.MaxDrawBuffers;
blend->independent_blend_enable = 1;
}
So independent blend won't get enabled even though the backend
supports it in the case where you have the same settings but with one
RGB and one RGBA ta
Yes, sorry, thought that was implied since I had given it earlier
pending my (as it turns out, incorrect) suggestion.
Reviewed-by: Ilia Mirkin
On Tue, Apr 28, 2015 at 8:20 PM, Brian Paul wrote:
> R-b?
>
> -Brian
>
>
> On 04/28/2015 05:47 PM, Ilia Mirkin wrote:
>>
>> That's... really asymmetrica
R-b?
-Brian
On 04/28/2015 05:47 PM, Ilia Mirkin wrote:
That's... really asymmetrical. There's a
PIPE_FORMAT_R10G10B10X2_SNORM. Oh well -- no reason to add it in just
for this.
On Tue, Apr 28, 2015 at 7:47 PM, Brian Paul wrote:
Unless I'm not seeing it, there is no such gallium format.
-Bria
This doesn't actually change behavior, but it matches the surrounding
code and makes more sense.
If independent blend mode is supported (GL_ARB_draw_buffers_blend) i==j
so there's no difference. If independent blend mode is not supported,
Blend[i].EquationRGB/A will never be GL_MIN/MAX if i>0.
--
If the user requested a GL_RGB texture but the driver actually allocated
an RGBA texture, the alpha values in the texture may not be defined.
If we later bind the texture as a color target and try to blend into
it with GL_DST_ALPHA or GL_ONE_MINUS_DST_ALPHA we may blend with
undefined alpha values
On 04/28/2015 05:52 PM, Ilia Mirkin wrote:
On Tue, Apr 28, 2015 at 7:52 PM, Brian Paul wrote:
On 04/28/2015 04:35 PM, Ilia Mirkin wrote:
On Tue, Apr 28, 2015 at 6:26 PM, Ilia Mirkin wrote:
Reviewed-by: Ilia Mirkin
ctually
Awesome! Now I can go remove this set of hacks from f
On Tuesday, April 28, 2015 12:04:50 AM Jordan Justen wrote:
> On 2015-04-27 19:02:38, Kenneth Graunke wrote:
> > On Friday, April 24, 2015 04:33:43 PM Jordan Justen wrote:
> > > + BEGIN_BATCH(dwords);
> > > + OUT_BATCH(GPGPU_WALKER << 16 | (dwords - 2));
> >
> > I was going to suggest splittin
Am 29.04.2015 um 01:52 schrieb Brian Paul:
> On 04/28/2015 04:35 PM, Ilia Mirkin wrote:
>> On Tue, Apr 28, 2015 at 6:26 PM, Ilia Mirkin
>> wrote:
>>> Reviewed-by: Ilia Mirkin
>>
>> ctually
>>
>>>
>>> Awesome! Now I can go remove this set of hacks from freedreno. And
>>> this fixes the sam
On Tue, Apr 28, 2015 at 7:52 PM, Brian Paul wrote:
> On 04/28/2015 04:35 PM, Ilia Mirkin wrote:
>>
>> On Tue, Apr 28, 2015 at 6:26 PM, Ilia Mirkin wrote:
>>>
>>> Reviewed-by: Ilia Mirkin
>>
>>
>> ctually
>>
>>>
>>> Awesome! Now I can go remove this set of hacks from freedreno. And
>>> th
On 04/28/2015 04:35 PM, Ilia Mirkin wrote:
On Tue, Apr 28, 2015 at 6:26 PM, Ilia Mirkin wrote:
Reviewed-by: Ilia Mirkin
ctually
Awesome! Now I can go remove this set of hacks from freedreno. And
this fixes the same issue in nouveau. Thanks for doing it the real way
:)
On Tue, Apr
That's... really asymmetrical. There's a
PIPE_FORMAT_R10G10B10X2_SNORM. Oh well -- no reason to add it in just
for this.
On Tue, Apr 28, 2015 at 7:47 PM, Brian Paul wrote:
> Unless I'm not seeing it, there is no such gallium format.
>
> -Brian
>
>
> On 04/28/2015 04:22 PM, Ilia Mirkin wrote:
>>
>
Unless I'm not seeing it, there is no such gallium format.
-Brian
On 04/28/2015 04:22 PM, Ilia Mirkin wrote:
Presumably you should also include RGB10_X2 while you're at it?
With that, Reviewed-by: Ilia Mirkin
On Tue, Apr 28, 2015 at 6:16 PM, Brian Paul wrote:
---
src/mesa/state_tracker/s
On Tue, Apr 28, 2015 at 3:37 PM, Rogovin, Kevin wrote:
>
>> I read the patch again and I'm still in the opinion that the changes to the
>> pure pre-gen7 logic (i.e., logic that is not re-used for later gens) are not
>> needed.
>
> As I have tried and apparently failed to communicate, it is -bette
On Tuesday, April 28, 2015 02:27:17 PM Neil Roberts wrote:
> The opt_sampler_eot optimisation of fs_visitor effectively assumes
> that it is running on a fragment shader because it casts the program
> key to a brw_wm_prog_key. However on Skylake fs_visitor can also be
> used for vertex shaders. It
> I read the patch again and I'm still in the opinion that the changes to the
> pure pre-gen7 logic (i.e., logic that is not re-used for later gens) are not
> needed.
As I have tried and apparently failed to communicate, it is -better- and more
consistent. Need
is a far stronger word. Without
On Tue, Apr 28, 2015 at 6:26 PM, Ilia Mirkin wrote:
> Reviewed-by: Ilia Mirkin
ctually
>
> Awesome! Now I can go remove this set of hacks from freedreno. And
> this fixes the same issue in nouveau. Thanks for doing it the real way
> :)
>
> On Tue, Apr 28, 2015 at 6:16 PM, Brian Paul wr
Reviewed-by: Ilia Mirkin
Awesome! Now I can go remove this set of hacks from freedreno. And
this fixes the same issue in nouveau. Thanks for doing it the real way
:)
On Tue, Apr 28, 2015 at 6:16 PM, Brian Paul wrote:
> If the user requested a GL_RGB texture but the driver actually allocated
> a
On Thursday, April 23, 2015 09:00:25 PM Topi Pohjolainen wrote:
> This series introduces virtual member functions for blorp parameters
> that know how certain part of the batch is to be programmed for the
> shader in question.
>
> This will be taken advantage of later on when I add support for
> l
Presumably you should also include RGB10_X2 while you're at it?
With that, Reviewed-by: Ilia Mirkin
On Tue, Apr 28, 2015 at 6:16 PM, Brian Paul wrote:
> ---
> src/mesa/state_tracker/st_format.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_f
On Thursday, April 23, 2015 09:00:28 PM Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp.h| 4 +++-
> src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +--
> src/mesa/drivers/dri/i965/gen7_blorp.cpp | 3 ++-
> 3 files changed, 14
If the user requested a GL_RGB texture but the driver actually allocated
an RGBA texture, the alpha values in the texture may not be defined.
If we later bind the texture as a color target and try to blend into
it with GL_DST_ALPHA or GL_ONE_MINUS_DST_ALPHA we may blend with
undefined alpha values
---
src/mesa/state_tracker/st_format.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_format.c
b/src/mesa/state_tracker/st_format.c
index 181465d..db7b5b7 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -99
On Tuesday, April 28, 2015 01:16:14 PM Matt Turner wrote:
> Could anyone spare a minute to take a look at this patch? It seems
> fine to me... but line rasterization rules are not something I really
> claim to understand. FWIW, it does fix Eric's line-aa-width piglit
> test.
>
> I'm inclined to co
On Wednesday, April 22, 2015 11:47:20 PM Topi Pohjolainen wrote:
> Currently batch emission logic is bolted into using the current
> gl-state and currently bound user shader programs as input. This
> series refactors the api to allow caller to give individual bits of
> information needed explicitly
On Wednesday, April 22, 2015 11:47:34 PM Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_state.h | 8 +
> src/mesa/drivers/dri/i965/gen6_wm_state.c | 56
> ++-
> 2 files changed, 41 insertions(+), 23 deletions(-
On Tue, Apr 28, 2015 at 02:27:17PM +0100, Neil Roberts wrote:
> The opt_sampler_eot optimisation of fs_visitor effectively assumes
> that it is running on a fragment shader because it casts the program
> key to a brw_wm_prog_key. However on Skylake fs_visitor can also be
> used for vertex shaders.
On Wednesday, April 22, 2015 11:47:33 PM Topi Pohjolainen wrote:
> Also changed a couple of direct shifts into SET_FIELD().
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 3 ++-
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30
>
https://bugs.freedesktop.org/show_bug.cgi?id=90207
--- Comment #14 from Aaron Watry ---
(In reply to José Fonseca from comment #13)
> I think I figured out the problem.
>
> As commented on DECL_RESOURCE_FUNC macro, the RESOURCE_VAR inline function
> is not type safe, and stuff that's not a ir_va
On Fri, Apr 24, 2015 at 12:59:53PM +0200, EdB wrote:
> Since clover should compile use -std=c++11,
> compat classes are no longer neccessary
>
> EdB (4):
> clover: remove compat class that matche std one
> clover: remove compat::string
> clover: make module::symbol::name a string
> clover:
On Wednesday, April 22, 2015 11:47:23 PM Topi Pohjolainen wrote:
> Read and write parts of the state stage are also split into
> explicit arguments allowing future patches to use constant
> program data.
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_binding_tables.c |
It's returning random values, because RESOURCE_VAR() is casting
different objects into ir_variable pointers.
This updates _mesa_count_active_attribs to filters the resources with
the same logic used in _mesa_longest_attribute_name_length.
https://bugs.freedesktop.org/show_bug.cgi?id=90207
P.S.:
https://bugs.freedesktop.org/show_bug.cgi?id=90207
--- Comment #13 from José Fonseca ---
I think I figured out the problem.
As commented on DECL_RESOURCE_FUNC macro, the RESOURCE_VAR inline function is
not type safe, and stuff that's not a ir_variable is wrongly being casted into
it.
This patc
Have an:
Acked-by: Chris Forbes
On Fri, Apr 24, 2015 at 3:41 AM, Marius Predut wrote:
> On SNB and IVB hw, for 1 pixel line thickness or less,
> the general anti-aliasing algorithm give up - garbage line is generated.
> Setting a Line Width of 0.0 specifies the rasterization of
> the “thinnest”
Could anyone spare a minute to take a look at this patch? It seems
fine to me... but line rasterization rules are not something I really
claim to understand. FWIW, it does fix Eric's line-aa-width piglit
test.
I'm inclined to commit it (and the Gen7 patch).
When the const block and offset are immediate values. Otherwise just
fall-back to the previous method of uploading the UBO constant data to
GRF using pull constants.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 12
src/mesa/drivers/dri/i965/brw_vec4.h
Now that UBOs are uploaded as push constants. We need to obtain and
append the amount of push constant entries generated by the UBO entry
fetches to the 3DSTATE_CONSTANT_* packets.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 7 ---
1 file changed, 4 inse
Use the gather table generated from the uniform uploads and
ir_binop_ubo_load to gather and pack the constants to the gather pool.
Note that the 3DSTATE_CONSTANT_* packet now refers to the gather
pool generated by the resource streamer instead of the constant buffer
pointed to by an offset of the
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface st
Signed-off-by: Abdiel Janulgue
---
src/glsl/nir/nir_types.cpp | 5 +
src/glsl/nir/nir_types.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/src/glsl/nir/nir_types.cpp b/src/glsl/nir/nir_types.cpp
index f0d0b46..249678f 100644
--- a/src/glsl/nir/nir_types.cpp
+++ b/src/glsl/nir/nir_
Signed-off-by: Abdiel Janulgue
---
src/glsl/nir/nir_types.cpp | 6 ++
src/glsl/nir/nir_types.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/src/glsl/nir/nir_types.cpp b/src/glsl/nir/nir_types.cpp
index 249678f..7218eeb 100644
--- a/src/glsl/nir/nir_types.cpp
+++ b/src/glsl/nir/nir
By generating the generating the gather constants channel mask.
Each gather push constant entry equates to a constant buffer
fetch for entries scattered around the buffer in 128-bit increments.
To select which bits are loaded into an entry, a channel mask
interface is provided by the hardware to na
Since we now consider UBOs as push constants, we need to layout
our push constant register space in such a way that UBO registers
are packed right after uniform registers.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 38 ++
1 file ch
This patch series enables resource streamer gather constants for UBOs.
With this feature, we treat UBO fetches as push constants instead of
pull. The resource streamer hardware makes it possible to gather and
pack easily with minimal overhead non-contiguous blocks of constant
data from an arbitrary
This patch implements the binding table enable command which is also
used to allocate a binding table pool where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.
Also inse
Now that we consider UBO constants as push constants, we need to include
the sizes of the UBO's constant slots in the visitor's uniform slot sizes.
This information is needed to properly pack vector constants tightly next to
each other.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i96
When the const block and offset are immediate values. Otherwise just
fall-back to the previous method of uploading the UBO constant data to
GRF using pull constants.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 11
src/mesa/drivers/dri/i965/brw_fs.h
To be able to refer to a constant buffer, the resource streamer needs
to index it with a hardware binding table entry. This blankets the ubo
buffers with hardware binding table indices.
Gather constants hardware fetches in 16-entry binding table blocks.
So we need to use a block that is unused.
S
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/ge
Switches on push constants whenever we have UBO entries.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 9
Programming null constants with gather constant tables seems to
be unsupported and results in a GPU lockup even with the prescribed
GPU workarounds in the bspec. Found out by trial and error that
disabling HW gather constant when the constant state for a stage
needs to be nullified is the only way
And generate the gather mask constant entries from our uniform data.
Data generated here will later be packed together with UBO constants.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a
When the const block and offset are immediate values. Otherwise just
fall-back to the previous method of uploading the UBO constant data to
GRF using pull constants.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 ++
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 59
If there are UBO constant entries, append them to stage_state->push_const_size.
The gather pool contains the combined entries of both ordinary uniforms
and UBO constants.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/gen6_vs_state.c | 20 ++--
1 file changed, 18 in
The 3DSTATE_GATHER_POOL_ALLOC is used to enable or disable the gather
push constants feature within a context. This patch provides the toggle
functionality of using gather push constants to program constant data
within a batch.
Using gather push constants require that a gather pool be allocated so
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 12
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c4c77b2..799d79e 10064
Assign the uploaded uniform block with hardware binding table indices.
This is indexed by the resource streamer to fetch the constant buffers
referred to by our gather table entries.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/gen6_vs_state.c | 11 +--
1 file changed, 9
Reserve space in the gather pool where the gathered uniforms are flushed.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/gen6_vs_state.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
b/src/mesa/drivers/dri/i965/gen6_vs_state.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_defines.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index da288d3..8079433 100644
--- a/src/mesa/drivers/dri/i965/
Unlike normal software binding tables where the driver has to manually
generate and fill a binding table array which are then uploaded to the
hardware, the resource streamer instead presents the driver with an option
to fill out slots for individual binding table indices. The hardware
accumlates th
The resource streamer is able to gather and pack sparsely-located
constant data from any buffer object by a referring to a gather table
This patch adds support for keeping track of these constant data
fetches into a gather table.
The gather table is generated from two sources. Ordinary uniform fet
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_defines.h | 24
src/mesa/drivers/dri/i965/intel_reg.h | 3 +++
3 files changed, 28 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/sr
https://bugs.freedesktop.org/show_bug.cgi?id=90207
--- Comment #12 from José Fonseca ---
I ran the test inside apitrace multiple times. When it passes we have
glGetProgramiv(program = 36, pname = GL_ACTIVE_ATTRIBUTES, params = &2)
when it fails we have
glGetProgramiv(program = 36, pname
https://bugs.freedesktop.org/show_bug.cgi?id=90207
José Fonseca changed:
What|Removed |Added
CC||jfons...@vmware.com
Component|Dr
On Sat, Jan 31, 2015 at 12:54 PM, Francisco Jerez wrote:
> ---
> src/glsl/ast_to_hir.cpp | 12
> 1 file changed, 12 insertions(+)
Patches 1-2 were already reviewed and committed.
Patches 3-7 are
Reviewed-by: Matt Turner
___
mesa-dev mai
On Sat, Jan 31, 2015 at 10:27 AM, Francisco Jerez wrote:
> ---
> src/mesa/main/uniform_query.cpp | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
> index 32870d0..82e5e38 100644
> --- a/src/mesa/main/unif
On Thu, Apr 23, 2015 at 11:56 AM, Matt Turner wrote:
> I've looked through all 18 patches, and they look fine to me -- but
> I'm not sure how much that's worth.
>
> I noted a bunch of whitespace mistakes (Is there a way to configure
> git commit to warn you about things like this?) but not much el
On Tue, Apr 28, 2015 at 10:08 AM, Francisco Jerez wrote:
> [PATCH 01/21] i965/fs: Fix passing an immediate to half().
> [PATCH 02/21] i965/fs: Fix offset() for registers with zero stride.
These two are
Reviewed-by: Matt Turner
Then I looked at patch 03/21 and realized this depends on something
---
src/mesa/drivers/dri/i965/brw_ir_glsl_intrinsics.h | 136 +
src/mesa/drivers/dri/i965/brw_reg.h| 1 +
2 files changed, 137 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_glsl_intrinsics.h
b/src/mesa/drivers/dri/i965/brw_ir_glsl_intrinsics.h
Define some utility functions to query the bitfield layout of a given
image format and whether it satisfies a number of more or less
hardware-specific properties.
---
src/mesa/drivers/dri/i965/brw_ir_surface_builder.h | 125 +
1 file changed, 125 insertions(+)
diff --git a/src
This is a rewrite of the GLSL IR atomic counter intrinsics translation
code based on the recently introduced surface builder. The new
implementation is considerably cleaner and back-end-independent.
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_ir_g
---
src/mesa/drivers/dri/i965/brw_fs.h | 9 --
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 26 ++---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 166 ++-
3 files changed, 19 insertions(+), 182 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
This works on either SVEC4 or VEC4 IR types and uses the builder
framework in order to generate IR in a back-end-agnostic fashion.
---
src/mesa/drivers/dri/i965/brw_ir_surface_builder.h | 219 +
1 file changed, 219 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_su
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_nir_intrinsics.h | 80 ++
2 files changed, 81 insertions(+)
create mode 100644 src/mesa/drivers/dri/i965/brw_nir_intrinsics.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
Reviewed-by: Paul Berry
v2: Disable the extension for the time being if NIR is in use until it
grows the necessary intrinsics.
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drive
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 15 +++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 17 -
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cp
---
src/mesa/drivers/dri/i965/brw_vec4.h | 9 ---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 96 ++
2 files changed, 7 insertions(+), 98 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index fbbee4b..f
---
src/mesa/drivers/dri/i965/brw_ir_glsl_intrinsics.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_glsl_intrinsics.h
b/src/mesa/drivers/dri/i965/brw_ir_glsl_intrinsics.h
index df7b1a3..b4d8f04 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_gl
Reviewed-by: Paul Berry
---
src/mesa/drivers/dri/i965/brw_context.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 0f2f9ad..a8fe3a6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/
Until now atomic counter built-ins were handled in a way that
prevented the visitor from encountering atomic counter IR variables
and dereferences directly. With the new intrinsic lowering code it's
going to be more convenient to be able to call back into the visitor
to let it handle the ugly deta
These functions implement the memory layout of a vecN value in a
message or return payload. The conversion is not always trivial
because the shared unit may not support the SIMD16 or SIMD4x2 vector
layouts, requiring splitting the payload in half and merging the reply
in the former case, or spread
Define a function to calculate the memory address of the image
location given by a vector of coordinates. This is required in cases
where we need to fall back to untyped surface access, which take a raw
memory offset and know nothing about surface coordinates, type
conversion or memory tiling and
This method will be used by the back-end-agnostic implementation of
the image and atomic counter built-ins to extract the register
location of its arguments.
---
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 +++
src/mesa/drivers/dri
These utility functions check whether an image access is valid.
According to the spec an invalid image access should have no effect on
the image and yield well-defined results. Typically the hardware
implements correct bounds and surface checking by itself, but in some
cases (typed atomics on IVB
Until now atomic counter built-ins were handled in a way that
prevented the visitor from encountering atomic counter IR variables
and dereferences directly. With the new intrinsic lowering code it's
going to be more convenient to be able to call back into the visitor
to let it handle the ugly deta
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4
4 files changed, 12 insertions(+), 12 deletions(-)
This is the last major piece missing in the i965 driver for
ARB_shader_image_load_store support. It has been tested on IVB, HSW
and BDW and passes all applicable piglit tests (some 4400 currently)
modulo hardware bugs, namely
"ARB_shader_image_load_store/invalid/index bounds test" on IVB and
"ARB_
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