This patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 06/19/2015 06:08 AM, Jose Fonseca wrote:
---
src/glsl/link_varyings.cpp | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/glsl/link_varyings.cpp b/src/glsl/link_varyings.cpp
index
https://bugs.freedesktop.org/show_bug.cgi?id=91044
--- Comment #1 from Emil Velikov emil.l.veli...@gmail.com ---
Based of the patch date (17 July 2012) and the extension revision history I'd
say that things were changed/nuked in Version 12 or later. With Version 15
being the prime suspect.
As
http://patchwork.freedesktop.org/patch/52138/
I've already pushed this patch btw, Chris gave me a r-b over IRC. But
it seems I neglected to push the piglit patch, my bad.
On Mon, Jun 22, 2015 at 11:35 AM, Ian Romanick i...@freedesktop.org wrote:
This seems believable... is there a piglit test?
On 06/19/2015 06:08 AM, Jose Fonseca wrote:
When input and output varyings started to be counted separately (commit
42305fb5) the is_varying_var function wasn't updated to return true for
output varyings or input varyings for stages other than the fragment
shader), effectively making the
On Mon, Jun 22, 2015 at 11:30 AM, Christian König
deathsim...@vodafone.de wrote:
On 22.06.2015 15:41, Ilia Mirkin wrote:
On Mon, Jun 22, 2015 at 9:39 AM, Tom Stellard t...@stellard.net wrote:
On Mon, Jun 22, 2015 at 12:23:54PM +0200, Marek Olšák wrote:
On Mon, Jun 22, 2015 at 5:36 AM, Ilia
I will happily remove the branch after the kernel driver lands.
I also wonder why all Mesa developers can force-push branches in Mesa
but not libdrm.
Marek
On Mon, Jun 22, 2015 at 5:39 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Mon, Jun 22, 2015 at 11:30 AM, Christian König
First, sorry for the late answer, I somehow missed your replies (I was
not in CC).
On mar, 2015-06-09 at 10:59 -0700, Ian Romanick wrote:
On 06/09/2015 10:40 AM, Carl Worth wrote:
On Tue, Jun 09 2015, Ian Romanick wrote:
From section 3.4 (Preprocessor) of the GLSL ES 3.00 specification:
On 22.06.2015 15:41, Ilia Mirkin wrote:
On Mon, Jun 22, 2015 at 9:39 AM, Tom Stellard t...@stellard.net wrote:
On Mon, Jun 22, 2015 at 12:23:54PM +0200, Marek Olšák wrote:
On Mon, Jun 22, 2015 at 5:36 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Sun, Jun 21, 2015 at 11:33 PM, Michel Dänzer
This seems believable... is there a piglit test?
On 06/17/2015 12:15 PM, Ilia Mirkin wrote:
This allows mod(int, int) to become selected as float mod when doubles
are supported.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Cc: 10.6 mesa-sta...@lists.freedesktop.org
---
Hi,
On 06/20/2015 03:32 PM, Timothy Arceri wrote:
The restrictions in ES make the extension easier to implement so
I thought I'd try get this stuff reviewed an committed before finishing
up the full extension.
The bits that I'm still working on for the desktop version are AoA inputs
outputs,
Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
On Mon, Jun 22, 2015 at 10:33 AM, Brian Paul bri...@vmware.com wrote:
Print GL_FLOAT, etc. instead of hex value.
---
src/mesa/main/varray.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/varray.c
On 06/22/2015 10:40 AM, Marek Olšák wrote:
I will happily remove the branch after the kernel driver lands.
I also wonder why all Mesa developers can force-push branches in Mesa
but not libdrm.
That's probably just historical. We probably ought to restrict that on
Mesa as well.
It sounds
Hi all,
As kindly hinted by Marek, currently we do have a wide selection of
supported dri loader combinations.
Although we like to think that things never break, we have to admit
that not many of us test every possible combinations of dri modules
and loaders. With the chances getting smaller as
As kindly hinted by Marek, currently we do have a wide selection of
supported dri loader combinations.
Although we like to think that things never break, we have to admit
that not many of us test every possible combinations of dri modules
and loaders. With the chances getting smaller as
Reviewed-by: Marek Olšák marek.ol...@amd.com
For Gallium, a new PIPE_CAP or new get_xxx_param function will be needed.
Marek
On Mon, Jun 22, 2015 at 8:41 PM, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
Commit b765119c changed the default value of all
Niiice, thank you. For most drivers - gallium, i965 this is
implemented, leaving nouveau_vieux, radeon, r200 and i915. From these
i915 does work with EGL, while nouveau_vieux dies miserably (missing
__DRI_IMAGE v7 iirc). How well does radeon/r200 fair ?
So as a nice starter task one can, modify
Hi everyone,
I spent some time building Mesa/llvmpipe on Windows and created a Python
script
that implements all the required steps (downloading/extracting all
prerequisites and sources,
configuring and building LLVM and Mesa).
The script is available at:
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
On 2015-06-03 00:01:17, Iago Toral Quiroga wrote:
Shader storage buffer objects (SSBO) require special handling: when we
detect writes to any channel of a shader buffer variable we need to
emit the corresponding write to memory. We will
This will allow to monitor global performance counters through the
command stream of the GPU instead of using ioctls.
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 11 +++
src/gallium/drivers/nouveau/nv50/nv50_screen.h | 1
This notifier buffer object will be used to read back global performance
counters results written by the kernel.
For each domain, we will store the handle of the perfdom object, an
array of 4 counters and the number of cycles. Like the Gallium's HUD,
we keep a list of busy queries in a ring in
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/gallium/drivers/nouveau/nv50/nv50_query.c | 41 ++
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 +
src/gallium/drivers/nouveau/nv50/nv50_screen.h | 3 ++
3 files changed, 45 insertions(+)
diff --git
This commit adds support for both compute and graphics global
performance counters which have been reverse engineered with
CUPTI (Linux) and PerfKit (Windows).
Currently, only one query type can be monitored at the same time because
the Gallium's HUD doesn't fit pretty well. This will be improved
This exposes a group of global performance counters that enables
GL_AMD_performance_monitor. All piglit tests are okay.
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/gallium/drivers/nouveau/nv50/nv50_query.c | 35 ++
This may happen when nv50_query_create() fails to create a new query.
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/gallium/drivers/nouveau/nv50/nv50_query.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git
On Thu 18 Jun 2015, Emil Velikov wrote:
Hi Boyan,
On 13 June 2015 at 08:33, Boyan Ding boyan.j.d...@gmail.com wrote:
The call to dri2_x11_add_configs_for_visuals (previously
dri2_add_configs_for_visuals) was moved downwards in commit f8c5b8a1,
but appeared again in its original position
Hello there,
This series exposes NVIDIA's global performance counters for Tesla through the
Gallium's HUD and the GL_AMD_performance_monitor extension.
This adds support for 24 hardware events which have been reverse engineered
with PerfKit (Windows) and CUPTI (Linux). These hardware events will
To write data at the right offset, the kernel has to know some
parameters of this ring buffer, like the number of domains and the
maximum number of queries.
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 7 +++
1 file changed, 7
This commit implements the base interface for hardware performance
counters that will be shared between nv50 and nvc0 drivers.
TODO: Bump libdrm version of mesa when nvif will be merged.
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/gallium/drivers/nouveau/Makefile.sources |
If query_create fails, why would any of these functions get called?
On Mon, Jun 22, 2015 at 4:53 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:
This may happen when nv50_query_create() fails to create a new query.
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
On 06/22/2015 10:52 PM, Ilia Mirkin wrote:
If query_create fails, why would any of these functions get called?
Because the HUD doesn't check if query_create() fails and it calls other
pipe_query functions with NULL pointer instead of a valid query object.
On Mon, Jun 22, 2015 at 4:53
Reviewed-by: Matt Turner matts...@gmail.com
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
24-26 once again makes me wonder if these optimization *can* be used
with SSBOs based on the same ext spec wording I referenced before:
The ability to write to buffer objects creates the potential for
multiple independent shader invocations to read and write the same
underlying memory. The same
For the series:
Reviewed-by: Roland Scheidegger srol...@vmware.com
Am 22.06.2015 um 06:01 schrieb Dave Airlie:
From: Dave Airlie airl...@redhat.com
This extends the draw code to add support for invocations.
Signed-off-by: Dave Airlie airl...@redhat.com
---
We were initializing it in each subclasses' constructors for some
reason.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 +---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
src/mesa/drivers/dri/i965/brw_shader.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3
Coverity sees that the functions immediately below the new assertions
dereference these pointers, but is unaware that an ENDIF always follows
an IF, etc.
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
Coverity sees the if (mode = BRW_PRIM_OFFSET (128)) test and assumes
that the else-branch might execute for mode to up 127, which out be out
of bounds.
---
src/mesa/drivers/dri/i965/brw_draw.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
On Wed, Jun 10, 2015 at 03:30:47PM -0700, Anuj Phogat wrote:
Buffers with Yf/Ys tiling end up using meta upload / download
paths or the blitter for cases where they used tiled_memcpy paths
in case of Y tiling. This has exposed some bugs in meta path. To
avoid any piglit regressions on SKL this
On Wednesday, June 17, 2015 01:01:24 AM Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
There is no way to lower them, because the array sizes are unknown
at compile time.
Based on a patch from: Fabian Bieler fabianbie...@fastmail.fm
I'm a bit confused by the justification given
On Mon, Jun 22, 2015 at 5:13 PM, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, Jun 10, 2015 at 03:30:50PM -0700, Anuj Phogat wrote:
In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
libdrm need not know
1-4 (with/without changes) are:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
On Wed, Jun 10, 2015 at 03:30:49PM -0700, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 30
If the stride is 0, the source is a uniform and we should not modify the
stride.
Cc: 10.6 mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91047
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 20
1 file changed, 16 insertions(+), 4
Can't find any uses of it in git history.
---
Strangely, when it was moved to its current location in commit 27558a1,
it was moved from mmath.h... which seems to have been lost from git's
history. Searching further git log --grep mmath.h shows that various
commit messages mention modifying mmath.h
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
On 2015-06-22 14:58:27, Matt Turner wrote:
Can't find any uses of it in git history.
---
Strangely, when it was moved to its current location in commit 27558a1,
it was moved from mmath.h... which seems to have been lost from git's
history.
On 23 June 2015 at 08:16, Ian Romanick i...@freedesktop.org wrote:
On 06/22/2015 11:54 AM, Dave Airlie wrote:
As kindly hinted by Marek, currently we do have a wide selection of
supported dri loader combinations.
Although we like to think that things never break, we have to admit
that not
From: Nanley Chery nanley.g.ch...@intel.com
Aligning with a non-power-of-two number is a general task that can be used in
various places. This commit is required for the next one.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_upload.c | 6 --
From: Nanley Chery nanley.g.ch...@intel.com
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN is changed to ALIGN_NPOT because alignment values are sometimes not
powers of two when working with ASTC.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 12 ++--
From: Nanley Chery nanley.g.ch...@intel.com
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
v2: remove extra newlines.
v3: follow existing coding style in translate_tex_format().
Signed-off-by: Nanley Chery
From: Nanley Chery nanley.g.ch...@intel.com
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Because the original
From: Nanley Chery nanley.g.ch...@intel.com
v2: alphabetize the extensions.
remove OES ASTC extension.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/extensions.c | 2 ++
src/mesa/main/mtypes.h | 2 ++
2 files
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove extra newline.
v3: use bool instead of GLboolean.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 28
From: Nanley Chery nanley.g.ch...@intel.com
This patch series enables support for the KHR_texture_compression_astc_{ldr,hdr}
extensions on Skylake machines. This revision includes developer suggestions and
fixes rendering issues on previously untested systems. The sRGB issues were
fixed and
From: Nanley Chery nanley.g.ch...@intel.com
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the macro be a power of two in the comments. Using software assertions
verifies this to be the case.
v2: use static inline functions instead of gcc-specific statement
From: Nanley Chery nanley.g.ch...@intel.com
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove OES ASTC extension reference.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
v2: add newlines to separate declarations, statments, and comments.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Reviewed-by: Neil
From: Nanley Chery nanley.g.ch...@intel.com
Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
v2: reintroduce brw.
don't include functional changes.
don't adjust function parameters or create a new function.
Signed-off-by:
I am shocked this is the only place we do this...
On Wed, Jun 10, 2015 at 03:30:48PM -0700, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 17 -
1 file changed, 12
On Monday, June 22, 2015 02:58:36 PM Matt Turner wrote:
If the stride is 0, the source is a uniform and we should not modify the
stride.
Cc: 10.6 mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91047
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 20
Series Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
On 2015-06-22 14:56:06, Matt Turner wrote:
Coverity sees that the functions immediately below the new assertions
dereference these pointers, but is unaware that an ENDIF always follows
an IF, etc.
---
From: Nanley Chery nanley.g.ch...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c
From: Nanley Chery nanley.g.ch...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50
From: Nanley Chery nanley.g.ch...@intel.com
v2: correct the spelling of the sRGB variants.
remove spaces around = when setting the enum value.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with the coding style, functions that aren't directly visible
to the GL API should prefer the use of bool over GLboolean.
Suggested-by: Ian Romanick ian.d.roman...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git
On 06/22/2015 05:02 PM, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the macro be a power of two in the comments. Using software assertions
verifies this to be the case.
v2: use static inline functions
On Wed, Jun 10, 2015 at 03:30:50PM -0700, Anuj Phogat wrote:
In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
libdrm need not know about the tiling format because these buffers
don't have hardware support
On Thu, Jun 18, 2015 at 03:41:50PM -0700, Kenneth Graunke wrote:
On Wednesday, June 17, 2015 03:50:13 PM Ben Widawsky wrote:
On gen9+ MOCS is an index into a table. It is 7 bits, and AFAICT, bit 0 is
for
doing encrypted reads.
I don't recall how I decided to do this for BXT. I don't
On Mon, Jun 22, 2015 at 2:53 PM, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, Jun 10, 2015 at 03:30:47PM -0700, Anuj Phogat wrote:
Buffers with Yf/Ys tiling end up using meta upload / download
paths or the blitter for cases where they used tiled_memcpy paths
in case of Y tiling. This has
As of this commit, nothing actually needs the brw_context.
---
src/mesa/drivers/dri/i965/brw_cs.cpp| 6 --
src/mesa/drivers/dri/i965/brw_fs.cpp| 12 ++--
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
Previously, we were pulling it from brw-do_rep_send
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
On 06/22/2015 11:54 AM, Dave Airlie wrote:
As kindly hinted by Marek, currently we do have a wide selection of
supported dri loader combinations.
Although we like to think that things never break, we have to admit
that not many of us test every possible combinations of dri modules
and
Previously, each shader took 3 shader time indices which were potentially
at arbirary points in the shader time buffer. Now, each shader gets a
single index which refers to 3 consecutive locations in the buffer. This
simplifies some of the logic at the cost of having a magic 3 a few places.
---
---
src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 92d1085..dcbd240 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++
---
src/mesa/drivers/dri/i965/brw_cs.cpp | 8 +++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 55 ---
src/mesa/drivers/dri/i965/brw_fs.h| 7 ++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 ++-
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5563c5a..ac65202 100644
---
Previously, these were pulled out of the GL context conditionally based on
whether we were running ff/ARB or a GLSL program. Now, we just pass them
in so that the visitor doesn't have to grab them itself.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
This creates the options at screen cration time and then we just copy them
into the context at context creation time. We also move is_scalar to the
brw_compiler structure.
We also end up manually setting some values that the core would have set by
default for us. Fortunately, there are only two
While we're at it, we'll drop the note about 10-20% performance loss.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a9d9f37..40e2c44
This way we can stop doing is_gles3 checks inside of the compiler.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp| 4 +++-
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 9 +
src/mesa/drivers/dri/i965/brw_vs.h| 5 -
3 files changed, 12 insertions(+), 6
v2 (Ken): Make shader_debug_log a printf-like function.
v3 (Jason): Add a void * to pass the brw_context through
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_cs.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +
src/mesa/drivers/dri/i965/brw_shader.cpp | 26 ++
src/mesa/drivers/dri/i965/brw_shader.h | 1 +
3 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
---
src/mesa/drivers/dri/i965/brw_context.c | 10 +-
src/mesa/drivers/dri/i965/intel_debug.c | 13 ++---
src/mesa/drivers/dri/i965/intel_debug.h | 4 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 2 ++
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git
I started working on this project some time ago to remove brw_context from
the backend compiler. I got a bunch of refactoring done but eventualy got
stuck up on shader_time and some debug logging stuff. I've finally gotten
around to finishing it and here it is.
Jason Ekstrand (15):
i965:
From: Kenneth Graunke kenn...@whitecape.org
This will be useful for wrapper functions.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/main/errors.c | 29 +
src/mesa/main/errors.h | 9 +
2 files changed, 30 insertions(+), 8 deletions(-)
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_cs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.h| 4 +++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 5 +++--
On Fri, Jun 19, 2015 at 02:41:50PM -0700, Anuj Phogat wrote:
On Wed, Jun 10, 2015 at 3:34 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
It can be later turned on for other tiling patterns (X,Y) too.
V3: Flush in
We never used the fact that it was variadic anyway.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
On Fri, 2015-06-19 at 13:32 -0700, Anuj Phogat wrote:
On Thu, Jun 18, 2015 at 11:41 PM, Iago Toral ito...@igalia.com wrote:
On Thu, 2015-06-18 at 09:19 -0700, Anuj Phogat wrote:
On Thu, Jun 18, 2015 at 7:09 AM, Iago Toral ito...@igalia.com wrote:
On Tue, 2015-06-16 at 11:15 -0700, Anuj
On Thu, Jun 04, 2015 at 05:35:11PM -0700, Ben Widawsky wrote:
On Wed, Jun 03, 2015 at 09:32:55PM +0300, Pohjolainen, Topi wrote:
On Wed, Jun 03, 2015 at 09:21:11PM +0300, Topi Pohjolainen wrote:
Shader programs are cached per stage (FS, VS, GS) using the
corresponding shader source
On Mon, Jun 22, 2015 at 01:28:12PM +0300, Pohjolainen, Topi wrote:
On Thu, Jun 04, 2015 at 05:35:11PM -0700, Ben Widawsky wrote:
On Wed, Jun 03, 2015 at 09:32:55PM +0300, Pohjolainen, Topi wrote:
On Wed, Jun 03, 2015 at 09:21:11PM +0300, Topi Pohjolainen wrote:
Shader programs are cached
Should there be some clamping somewhere to prevent crashes due to
out-of-bound unit index?
In any case,
Reviewed-by: Roland Scheidegger srol...@vmware.com
Am 22.06.2015 um 05:18 schrieb Dave Airlie:
This is required for ARB_gpu_shader5 support in softpipe.
v2: add support to txd/txf/txq
On Mon, Jun 22, 2015 at 5:36 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Sun, Jun 21, 2015 at 11:33 PM, Michel Dänzer mic...@daenzer.net wrote:
On 22.06.2015 00:31, Ilia Mirkin wrote:
On Sun, Jun 21, 2015 at 12:22 PM, Emil Velikov emil.l.veli...@gmail.com
wrote:
On 20/06/15 10:01, Eirik
On 22/06/15 19:40, Florian Link wrote:
Hi everyone,
I spent some time building Mesa/llvmpipe on Windows and created a Python
script
that implements all the required steps (downloading/extracting all
prerequisites and sources,
configuring and building LLVM and Mesa).
The script is available at:
Matt, Jason, and I haven't found this useful in a long time.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_nir.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
From: Ian Romanick ian.d.roman...@intel.com
Commit b765119c changed the default value of all the counter bits to
64. However, older hardware only has 32 counter bits.
This has only been build-tested. We don't have any tests that verify
the advertised value against implementation behavior, so I
On 22 June 2015 at 15:01, Jose Fonseca jfons...@vmware.com wrote:
On 19/06/15 23:09, Emil Velikov wrote:
On 19 June 2015 at 21:26, Jose Fonseca jfons...@vmware.com wrote:
On 19/06/15 20:56, Emil Velikov wrote:
Hi all,
A lovely series inspired (more like 'was awaken to send these out') by
On 06/22/2015 07:01 AM, Jose Fonseca wrote:
On 19/06/15 23:09, Emil Velikov wrote:
On 19 June 2015 at 21:26, Jose Fonseca jfons...@vmware.com wrote:
On 19/06/15 20:56, Emil Velikov wrote:
Hi all,
A lovely series inspired (more like 'was awaken to send these out') by
Pal Rohár, who was
We were not emitting the LOD, which led to message lengths of 1 instead
of 3. Setting has_lod makes us emit the LOD, but I had to make changes
to avoid emitting the non-existent coordinate as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91022
Cc: mesa-sta...@lists.freedesktop.org
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