On Thu, 2015-06-25 at 13:24 -0700, Jason Ekstrand wrote:
Previously, fs_inst::regs_read() fell back to depending on the register
width for the second source. This isn't really correct since it isn't a
SIMD8 value at all, but a SIMD4x2 value. This commit changes it to
explicitly be always one
On 06/25/2015 05:24 PM, Emil Velikov wrote:
Hi gents,
On 9 June 2015 at 14:09, Francisco Jerez curroje...@riseup.net wrote:
Francisco Jerez curroje...@riseup.net writes:
Tapani Pälli tapani.pa...@intel.com writes:
Desktop GLSL 130 and GLSL ES 300 allow sampler array indexing where
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
On Thu, 2015-06-25 at 13:24 -0700, Jason Ekstrand wrote:
Soon we will start using the builder to explicitly set all the execution
sizes. We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a
Reviewed-by: Iago Toral Quiroga ito...@igali.com
On Thu, 2015-06-25 at 13:24 -0700, Jason Ekstrand wrote:
Shortly, offset() will depend on the builder so we need it moved to some
place where it has access to that.
---
src/mesa/drivers/dri/i965/brw_fs.h| 21 +
https://bugs.freedesktop.org/show_bug.cgi?id=90264
--- Comment #24 from Boyan Ding stu_...@126.com ---
Furkan, try launching chrome with LIBGL_DRI3_DISABLE=1 and see if the problem
still persist. The problem at least went away on my machine when I disable
DRI3.
--
You are receiving this mail
https://bugs.freedesktop.org/show_bug.cgi?id=90264
--- Comment #25 from Furkan fal...@gmail.com ---
I forgot to add, I have DRI3 disabled already. From my Xorg log:
[12.974] (II) RADEON(0): [DRI2] Setup complete
[12.974] (II) RADEON(0): [DRI2] DRI driver: radeonsi
[12.974] (II)
On Thu, Jun 25, 2015 at 01:24:53PM -0700, Jason Ekstrand wrote:
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 42
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 58
https://bugs.freedesktop.org/show_bug.cgi?id=90264
--- Comment #26 from Eero Tamminen eero.t.tammi...@intel.com ---
(In reply to Matt Whitlock from comment #15)
(In reply to Furkan from comment #14)
For those of you who are using nouveau, does the problem go away after
reverting the mesa
From: Alejandro Piñeiro apinhe...@igalia.com
Disables nir_lower_alu_to_scalar when the shader stage being processed work
on vec4 vectors, like the upcoming NIR-vec4 backend.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_nir.c | 16
From: Antia Puentes apuen...@igalia.com
Based on the vec4_visitor IR implementation for the ir_binop_load_ubo
operation. Notice that unlike the vec4_visitor IR, adding the !=0
comparison for UBO bools is not needed here because that comparison is
already added by the nir_visitor when processing
From: Iago Toral Quiroga ito...@igalia.com
For the indirect case we need to take the index delivered by
NIR and compute the parent uniform that we are accessing (the one
that we uploaded to a surface) and the constant offset into that
surface.
Bugzilla:
From: Antia Puentes apuen...@igalia.com
Implementation based on the vec4_visitor IR implementation
for the operations ir_binop_mul and ir_binop_imul_high.
Adds NIR ALU operations:
* nir_op_fmul
* nir_op_imul
* nir_op_imul_high
* nir_op_umul_high
Bugzilla:
From: Iago Toral Quiroga ito...@igalia.com
The same we do in the FS NIR backend, only that here we need to consider
the number of components in the condition and adjust the swizzle
accordingly.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
This is taken as-is from fs_nir.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
From: Alejandro Piñeiro apinhe...@igalia.com
These include:
nir_intrinsic_load_vertex_id_zero_base
nir_intrinsic_load_base_vertex
nir_intrinsic_load_instance_id
The source register is fetched from the nir_system_values map initialized
during nir_setup_system_values stage.
Bugzilla:
This implementation sets up a map of output variable offsets to output indexes
and types.
This map will then be queried when processing store_output intrinsic operations,
to use it as an index into the output_reg array where the output registers are
stored. The original type of the variable is
The index into the output_reg array where to store the destination register is
fetched from the nir_outputs map built during nir_setup_outputs stage.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 17 +++--
1 file
New method brw_writemask_for_size() will return a writemask with the first
'size'
components activated.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_reg.h | 9 +
1 file changed, 9 insertions(+)
diff --git
The source register is fetched from the nir_inputs map built during
nir_setup_inputs stage.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git
This patch makes public the is_scalar_shader_stage() method in brw_shader, and
renames it to brw_compiler_is_scalar_shader_stage(). The plan is to later reuse
it
in brw_nir, to enable/disable optimization passes depending on the type
of shader stage.
The new method accepts a brw_compiler instead
It basically allocates registers local to a function in a nir_locals map,
then emits all its control-flow blocks.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12 +++-
2
From: Alejandro Piñeiro apinhe...@igalia.com
Similar to other variable setups, system values will initialize the
corresponding register inside a 'nir_system_values' map, which will then
be queried later when processing the different system value intrinsics
for the appropriate register.
Bugzilla:
From: Iago Toral Quiroga ito...@igalia.com
The current implementation operates in scalar mode only, so add a vec4
mode where types are padded to vec4 sizes.
This will be useful in the i965 driver for its vec4 nir backend
(and possbly other drivers that have vec4-based shaders).
Bugzilla:
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
These methods are essential for the implementation of the NIR-vec4 pass. They
work similar to their fs_nir counter-parts.
When processing instructions, these methods are invoked to resolve the
brw registers (source or destination)
From: Alejandro Piñeiro apinhe...@igalia.com
The implementation is based on its fs_nir counterpart.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff
Upcoming NIR-vec4 pass can benefit from this method, so lets move it up.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 18 --
src/mesa/drivers/dri/i965/brw_nir.c | 18 ++
From: Iago Toral Quiroga ito...@igalia.com
This is based on similar code existing in vec4_visitor. It builds the
uniform register file iterating through each uniform variable. It
also stores the index of each register at the corresponding offset
in a map. This map will later be used by
From: Alejandro Piñeiro apinhe...@igalia.com
The new virtual method is more flexible, it has a signature:
dst_reg *make_reg_for_system_value(int location, const glsl_type *type);
so the current method will be chained through this one.
Bugzilla:
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Avoid copying an overwritten swizzle, use the original values.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/nir/nir_opt_peephole_ffma.c | 5 -
1
This patch changes the signature of gather_channel() to accept the gather
component directly instead of fetching it internally from ir_texture.
This will allow reuse in the upcoming NIR-vec4 pass.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
The code is adapted from vec4_visitor with only minimum modifications.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 34 --
1 file changed, 32
The implementation is taken as-is from vec4_visitor.
It is similar for both operations, so it makes sense to group them together.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 14 +-
1 file changed, 13 insertions(+), 1
From: Alejandro Piñeiro apinhe...@igalia.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
This is a helper method that returns a shader instruction opcode from the
corresponding NIR texture opcode. It will be used to keep code in
nir_emit_texture() clean.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 39
On Fri, Jun 26, 2015 at 08:51:59AM +0300, Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool
-Original Message-
From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
Behalf Of Matt Turner
Sent: Friday, June 26, 2015 1:40 AM
To: Ben Widawsky
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH v2] mesa : NULL check InfoLog
On Thu, Jun 25, 2015
This patch will add a brw_vec4_nir.cpp file filled with entry point methods to
the main functionality, following a structure similar to brw_fs_nir.cpp.
Subsequent patches in this series will be adding the implementations for these
methods, incrementally.
Bugzilla:
This implementation sets up a map of input variable offsets to source registers
that are already initialized with the corresponding register offset.
This map will then be queried when processing load_input intrinsic operations,
to obtain the correct register source from which the input data will
Hello,
This series adds a new vec4 backend for i965 based on NIR. It is the result of
working on
https://bugs.freedesktop.org/show_bug.cgi?id=89580.
This backend is activated if all the following conditions are met:
* INTEL_USE_NIR environment variable is set to 1 (or true)
* The stage is a
The type_size() method is currently accessible only in the implementation of
vec4_visitor. Since we need to reuse it in the upcoming NIR-vec4 pass, lets
make
it a method of the class instead.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4.h
The NIR-vec4 pass will be activated if ALL the following conditions are met:
* INTEL_USE_NIR environment variable is defined and is positive (1 or true)
* The stage is vertex shader
* The HW generation is either SandyBridge (gen6), IvyBridge or Haswell (gen7)
Bugzilla:
From: Alejandro Piñeiro apinhe...@igalia.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 5a1d494..fa3f187
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index
This is the NIR-vec4 version of vec4_visitor::swizzle_result(). It is
essentially the same code except that we also pass the destination register
as argument, so that the result is MOVed to that register instead of
to vec4_visitor::result, which is what vec4_visitor::swizzle_result() does
and
This patch changes the signature of emit_mcs_fetch() to accept lower level
arguments. The purpose is to reuse it in the upcoming NIR-vec4 pass.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4.h | 3 ++-
From: Alejandro Piñeiro apinhe...@igalia.com
This is useful for the upcoming texture support in NIR-vec4 pass, as we found
several cases where the brw_type is available, but not the glsl_type.
Without this new constructor, the alternative would be:
dst_reg reg(MRF, reg)
reg.type = brw_type
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 0f54858..5a1d494
This implementation is taken as-is from fs_nir.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index
The code has been taken almost as-is from vec4_visitor.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git
From: Alejandro Piñeiro apinhe...@igalia.com
The code has been taken as-is from vec4_visitor.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
The is_high_sample() method is currently accessible only in the implementation
of
vec4_visitor. Since we need to reuse it in the upcoming NIR-vec4 pass, lets
make
it a method of the class instead.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
From: Antia Puentes apuen...@igalia.com
Follows the vec4_visitor IR implementation but
sets the saturate value in addition.
Adds NIR ALU operations:
* nir_op_fsign
* nir_op_isign
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |
From: Antia Puentes apuen...@igalia.com
Used the same implementation than the vec4_visitor NIR.
Adds NIR ALU operations:
* nir_op_b2i
* nir_op_b2f
* nir_op_f2b
* nir_op_i2b
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |
This method returns the glsl_base_type corresponding to a nir_alu_type.
It will factorize code currently present in fs_nir, that can be reused
in vec4_nir on its upcoming emit_texture support.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
From: Alejandro Piñeiro apinhe...@igalia.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
From: Antia Puentes apuen...@igalia.com
Needed in the NIR backend to set the saturate value of the
instruction.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 8
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Thu, Jun 25, 2015 at 10:26 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeonsi/si_shader.c| 5 +
On Thu, Jun 25, 2015 at 09:17:38AM -0700, Kenneth Graunke wrote:
This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c
from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19.
No Piglit changes on Sandybridge.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by:
From: Marta Lofstedt marta.lofst...@intel.com
When a program is compiled, but linking failed the
sh-InfoLog could be NULL. This is exploited
by OpenGL ES 3.1 conformance tests.
V3: Chnaged title.
Signed-off-by: Marta Lofstedt marta.lofst...@intel.com
---
src/mesa/main/shaderapi.c | 3 ++-
1
On Fri, Jun 26, 2015 at 08:52:01AM +0300, Abdiel Janulgue wrote:
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding table pointer commands
as pipelined state.
From: Antia Puentes apuen...@igalia.com
This enables NIR pass lower_vec_to_movs on shaders that work on vec4.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_nir.c| 5 +
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 +
2 files
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_flt
* nir_op_ilt
* nir_op_ult
* nir_op_fge
* nir_op_ige
* nir_op_uge
* nir_op_feq
* nir_op_ieq
* nir_op_fne
* nir_op_ine
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_fadd
* nir_op_iadd
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_bany2
* nir_op_bany3
* nir_op_bany4
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12
1 file changed, 12 insertions(+)
diff --git
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_ishl
* nir_op_ishr
* nir_op_ushr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12
1 file changed, 12 insertions(+)
diff --git
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operation:
* nir_op_flrp
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
From: Antia Puentes apuen...@igalia.com
NIR ALU operations:
* nir_op_fabs
* nir_op_iabs
* nir_op_fneg
* nir_op_ineg
* nir_op_fsat
should be lowered by lower_source mods
* nir_op_fdiv
should be lowered in the compiler by DIV_TO_MUL_RCP.
* nir_op_fmod
From: Antia Puentes apuen...@igalia.com
Marked them as unreachable.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
From: Antia Puentes apuen...@igalia.com
* Lowered floating-point pack and unpack operations are not valid in VS.
* Pack and unpack 2x16 operations should be handled by lower_packing_builtins.
* Adds NIR ALU operations:
* nir_op_pack_half_2x16
* nir_op_unpack_half_2x16
*
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_uadd_carry
* nir_op_usub_borrow
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16
1 file changed, 16 insertions(+)
diff --git
From: Antia Puentes apuen...@igalia.com
For operations that have a predefined operand size 0, defined in
glsl/nir/nir_opcodes.c, NIR returns a swizzle containing zeros in the
components from outside the source vector. However, the driver
expects those components to have a swizzle value equal to
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_bany_fnequal2
* nir_op_bany_inequal2
* nir_op_bany_fnequal3
* nir_op_bany_inequal3
* nir_op_bany_fnequal4
* nir_op_bany_inequal4
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
From: Antia Puentes apuen...@igalia.com
Same implementation than the IR case.
Adds NIR ALU operations:
* nir_op_bitfield_reverse
* nir_op_bit_count
* nir_op_ufind_msb
* nir_op_ifind_msb
* nir_op_find_lsb
* nir_op_ubitfield_extract
* nir_op_ibitfield_extract
* nir_op_bfm
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_ftrunc
* nir_op_fceil
* nir_op_ffloor
* nir_op_ffrac
* nir_op_fround_even
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 40
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operation:
* nir_op_ffma
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_inot
* nir_op_ixor
* nir_op_ior
* nir_op_iand
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16
1 file changed, 16 insertions(+)
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_f2i
* nir_op_f2u
* nir_op_i2f
* nir_op_u2f
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 11 +++
1 file changed, 11 insertions(+)
diff
From: Antia Puentes apuen...@igalia.com
Needed in the NIR backend to set the saturate value of the
instruction.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 +++-
2
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_frcp
* nir_op_fexp2
* nir_op_flog2
* nir_op_fexp
* nir_op_flog
* nir_op_fsin
* nir_op_fcos
* nir_op_idiv
* nir_op_udiv
* nir_op_umod
* nir_op_ldexp
* nir_op_fsqrt
* nir_op_frsq
*
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_fdot2
* nir_op_fdot3
* nir_op_fdot4
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_bcsel
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_ball_fequal2
* nir_op_ball_iequal2
* nir_op_ball_fequal3
* nir_op_ball_iequal3
* nir_op_ball_fequal4
* nir_op_ball_iequal4
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
From: Antia Puentes apuen...@igalia.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
From: Antia Puentes apuen...@igalia.com
Adds NIR ALU operations:
* nir_op_imov
* nir_op_fmov
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git
From: Antia Puentes apuen...@igalia.com
Needed in the NIR backend to set the saturate value of the
instruction.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4.h | 5 +++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 6 --
2
From: Antia Puentes apuen...@igalia.com
This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 19 ++-
1
On 06/26/2015 01:06 AM, Ilia Mirkin wrote:
On Thu, Jun 25, 2015 at 4:22 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Thu, Jun 25, 2015 at 5:08 AM, Marta Lofstedt
marta.lofst...@linux.intel.com wrote:
From: Marta Lofstedt marta.lofst...@intel.com
v4 : only expose GL_ARB_texture_multisample
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Wed, Jun 24, 2015 at 9:26 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:
The HUD doesn't check if query_create() fails and it calls other
pipe_query functions with NULL pointer instead of a valid query object.
Signed-off-by: Samuel
The compiler doesn't know that there's another thread. And it won't
start to assume that there might always be another thread because then
it could never optimize pointer derefs.
On Fri, Jun 26, 2015 at 11:55 AM, Marek Olšák mar...@gmail.com wrote:
I assumed the atomic operation in another
On 25 June 2015 at 23:10, Matt Turner matts...@gmail.com wrote:
On Thu, Jun 25, 2015 at 2:05 PM, Erik Faye-Lund kusmab...@gmail.com wrote:
Back in March[1], I sent a patch porting _mesa_strto[df] to
C rather than C++. I fixed up the patch according to the
criticism, but unfortunately I dropped
Erik Faye-Lund kusmab...@gmail.com writes:
On Fri, Jun 26, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net
wrote:
Davin McCall dav...@davmac.org writes:
On 26/06/15 14:31, Eirik Byrkjeflot Anonsen wrote:
Erik Faye-Lund kusmab...@gmail.com writes:
On Fri, Jun 26, 2015 at 1:23 PM,
Francisco Jerez curroje...@riseup.net writes:
Erik Faye-Lund kusmab...@gmail.com writes:
On Fri, Jun 26, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net
wrote:
Davin McCall dav...@davmac.org writes:
On 26/06/15 14:31, Eirik Byrkjeflot Anonsen wrote:
Erik Faye-Lund
Davin McCall dav...@davmac.org writes:
On 26/06/15 14:31, Eirik Byrkjeflot Anonsen wrote:
Erik Faye-Lund kusmab...@gmail.com writes:
On Fri, Jun 26, 2015 at 1:23 PM, Davin McCall dav...@davmac.org wrote:
On 26/06/15 12:03, Davin McCall wrote:
... The stored value of 'n' is not accessed by
On Fri, Jun 26, 2015 at 6:14 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Fri, Jun 26, 2015 at 12:03 PM, Emil Velikov emil.l.veli...@gmail.com
wrote:
On 25 June 2015 at 23:10, Matt Turner matts...@gmail.com wrote:
On Thu, Jun 25, 2015 at 2:05 PM, Erik Faye-Lund kusmab...@gmail.com wrote:
Yeah, but there are a whole bunch of places, non-blit-related, where
we call st_validate_state that will hit this same problem.
On Fri, Jun 26, 2015 at 11:43 AM, Brian Paul bri...@vmware.com wrote:
If we really do need to call _mesa_update_state() for this, I think the
right place would be in
On Fri, Jun 26, 2015 at 11:33 AM, Marek Olšák mar...@gmail.com wrote:
I expect the variable will be changed using an atomic operation by the
CPU, or using a coherent store instruction by the GPU.
If this is wrong and volatile is really required here, then
p_atomic_read is wrong too. Should we
My question was how to fix p_atomic_read? Would the volatile read that
I proposed work?
Marek
On Fri, Jun 26, 2015 at 5:59 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
The compiler doesn't know that there's another thread. And it won't
start to assume that there might always be another thread
p_atomic_read is fine as-is. The read is guaranteed to be atomic up to
a word size on x86 processors. I suspect other cpu's have similar
guarantees, and if not, then hopefully have other ops to perform the
read atomically.
On Fri, Jun 26, 2015 at 12:18 PM, Marek Olšák mar...@gmail.com wrote:
My
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