https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #2 from Laurent carlier lordhea...@gmail.com ---
Also reproduced with radeonsi hd7870/mesa-git/llvm-svn
--
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You are the assignee for the bug.
sources with file == HW_REG get all their information from the
fixed_hw_reg field, so we need to get the stride and type from there
when computing the size.
Signed-off-by: Connor Abbott connor.w.abb...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 24 ++--
1 file
From: Jordan Justen jordan.l.jus...@intel.com
If a source register in the push constant registers uses more than on
register, then we wouldn't update payload_last_use_ip for subsequent
registers.
Unlike most uniform data pushed into registers, the CS gl_LocalInvocationID
data varies per
From: Connor Abbott cwabbo...@gmail.com
regs_read() will handle LINTERP for us since the previous commit. In
addition, we were being too conservative, since it will only read 2
registers on SIMD8.
instructions in affected programs: 9061 - 8893 (-1.85%)
helped:
Hi Neil,
On 01/07/15 17:08, Neil Roberts wrote:
If we wanted to avoid growing the size of exec_list to four pointers
instead of three, maybe we could store it in a union like below:
struct exec_list {
union {
struct {
struct exec_node head_sentinel;
struct
Re-post, where lines are hopefully not wrapped.
Davin
From b946157dcac2ca198ccf1981151525a1fc3ae39f Mon Sep 17 00:00:00 2001
From: Davin McCall dav...@davmac.org
Date: Sat, 27 Jun 2015 13:48:41 +0100
Subject: [PATCH] glsl: fix some strict aliasing issues in exec_list
There is a problem in
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #7 from Béla Gyebrószki gyebr...@gmail.com ---
(In reply to Ilia Mirkin from comment #6)
The plot thickens... it actually renders fine on HSW (i965) on mesa 10.3.7,
but fails with (approx) HEAD. Actually I'm not 100% sure if it's
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #8 from Ilia Mirkin imir...@alum.mit.edu ---
Created attachment 116848
-- https://bugs.freedesktop.org/attachment.cgi?id=116848action=edit
bisect log for color issue
OK, so I bisected the color issue to
$ git bisect good
The second source always stays within the same SIMD8 register.
Signed-off-by: Connor Abbott connor.w.abb...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
From: Connor Abbott cwabbo...@gmail.com
Before, we were setting payload_last_use_ip for unused payload
registers to 0, which made them interfere with whatever the first
instruction wrote to due to the workaround for SIMD16 uniform arguments.
Just use -1 to mean unused instead, and then skip
Jason Ekstrand ja...@jlekstrand.net writes:
Now that we can create builders with a bigger width than their parent as
long as it's exec_all, we don't need to create the instruction manually.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 11 +--
1 file changed, 5 insertions(+), 6
Hi Jason,
thanks for the review.
On mar, 2015-06-30 at 14:10 -0700, Jason Ekstrand wrote:
First off, this needs a different commit message. float-related
functions isn't particularly descriptive. How about various
rounding functions because these really are all rounding modes.
True, I will
Instead of relying on hardware defaults the i915 kernel driver is
going program custom MOCS tables system-wide on Gen9 hardware. The
WT entry previously used for renderbuffers had a number of problems:
It disabled caching on eLLC, it used a reserved L3 cacheability
setting, and it used to
Follow-up to i965/gen9: Use custom MOCS entries set up by the
kernel., sent as a separate patch to make the SKL change easier to
back-port to stable branches.
---
This change depends on Ville's [PATCH 1/2] i965: House MOCS settings
in brw_context/brw_device_info:
Ben Widawsky b...@bwidawsk.net writes:
I am not the right person to judge the complexity tradeoff, but it
seems like a worthwhile patch to me. I spent a few minutes thinking
about how it could hurt performance and was unable to come up with
anything.
Thanks. I was thinking more that the
Jason Ekstrand ja...@jlekstrand.net writes:
On Fri, Jun 26, 2015 at 11:51 AM, Francisco Jerez curroje...@riseup.net
wrote:
Jason Ekstrand ja...@jlekstrand.net writes:
On Fri, Jun 26, 2015 at 8:52 AM, Francisco Jerez curroje...@riseup.net
wrote:
Jason Ekstrand ja...@jlekstrand.net writes:
On 29/06/15 09:11, Jordan Justen wrote:
On 2015-06-24 07:36:24, Iago Toral wrote:
On Wed, 2015-06-24 at 15:43 +0300, Francisco Jerez wrote:
AFAICT the reason why this (and many of the other changes in GLSL
optimization passes) is needed is because SSBO loads have been
implemented as
https://bugs.freedesktop.org/show_bug.cgi?id=90264
--- Comment #30 from Eero Tamminen eero.t.tammi...@intel.com ---
(In reply to Matt Whitlock from comment #29)
Also, for what it's worth, this problem seems to have disappeared for me. I
have rebuilt Mesa 10.5.6 without the revert of 95073a2d,
This is not needed anymore.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 7 --
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 29 ---
src/mesa/drivers/dri/i965/gen8_surface_state.c| 26
instead of update_texture_surface().
For gen 7 this interface can be supported relatively easily
by changing the interface of brw_update_texture_surface().
I didn't switch BRW_SURFACE_LOD_SHIFT to be emitted using
SET_FIELD() as the mask for it is not defined yet. This can be
addressed as a
v2: Non-trivial rebase
Reviewed-by: Matt Turner matts...@gmail.com (v1)
Reviewed-by: Kenneth Graunke kenn...@whitecape.org (v1)
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h
v2: Non-trivial rebase
Reviewed-by: Matt Turner matts...@gmail.com (v1)
Reviewed-by: Kenneth Graunke kenn...@whitecape.org (v1)
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
All hardware platforms have this in common, so do it in the
hardware independent dispatcher.
v2 (Matt): Removed extra whitespace.
v3: Non-trivial rebase
Reviewed-by: Matt Turner matts...@gmail.com (v1)
Reviewed-by: Kenneth Graunke kenn...@whitecape.org (v1)
Signed-off-by: Topi Pohjolainen
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 4 ++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_surface_state.c|
Hi,
On 06/25/2015 04:56 PM, Davin McCall wrote:
On 25/06/15 14:32, Eero Tamminen wrote:
On 06/25/2015 03:53 PM, Davin McCall wrote:
On 25/06/15 12:27, Eero Tamminen wrote:
On 06/25/2015 02:48 AM, Davin McCall wrote:
In terms of performance:
(export LIBGL_ALWAYS_SOFTWARE=1; time glmark2)
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #3 from Tapani Pälli lem...@gmail.com ---
reproduced with i965 (IVB)
--
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You are the QA Contact for the bug.
You are the assignee for the bug.
___
On 06/30/2015 01:47 AM, Jason Ekstrand wrote:
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev el...@igalia.com wrote:
It basically allocates registers local to a function in a nir_locals map,
then emits all its control-flow blocks.
Bugzilla:
Equivalent logic for newer generations (= 7) use the tex object
format instead. This patch prepares for merging the decision
making for all generations.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-
1 file changed, 1
Here is a rebase of refactoring originally sent in early May. This
is now based on Curro's work and applies on top of the current
master. I chose to re-order my patches in order to keep them as
tiny as possible. Especially the dispatch for the texture buffer
surfaces is split in two parts - one
All generations do the same exact dispatch and it could be
therefore done in the hardware independent stage.
v2: Rebased where there are still duplicate calls in gen7 and gen8
handlers. These will be dropped in subsequent patches.
Reviewed-by: Matt Turner matts...@gmail.com (v1)
Reviewed-by:
as it is only used for reading.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_surface_state.c| 2 +-
3 files changed, 3
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c14f00a..b68b136
On 1 July 2015 at 08:49, Ilia Mirkin imir...@alum.mit.edu wrote:
We want to require different versions for nouveau and nouveau_vieux.
autoconf will only check for NOUVEAU once if both drivers are enabled,
meaning both version checks don't get executed. Rename the nouveau_vieux
one to NVVIEUX
v2: Rebased to include consideration for atomic ops in the
shader.
CC: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/brw_state.h | 9 +++
src/mesa/drivers/dri/i965/gen7_wm_state.c | 102
Signed-off-by: Boyan Ding boyan.j.d...@gmail.com
---
configure.ac |3 +
src/egl/drivers/dri2/Makefile.am |5 +
src/egl/drivers/dri2/egl_dri2.c | 65 +-
src/egl/drivers/dri2/egl_dri2.h | 12 +-
src/egl/drivers/dri2/platform_x11.c
Hi,
Does this address comments raised for the 2014 EGL/DRI3 patch:
http://patchwork.freedesktop.org/patch/35399/
?
- Eero
On 07/01/2015 06:31 PM, Boyan Ding wrote:
The patch that follows implements DRI3 support for EGL API. Most of the
code is directly ported from dri3_glx.c,
On 01/07/15 13:32, Eero Tamminen wrote:
Hi,
On 06/25/2015 04:56 PM, Davin McCall wrote:
On 25/06/15 14:32, Eero Tamminen wrote:
On 06/25/2015 03:53 PM, Davin McCall wrote:
On 25/06/15 12:27, Eero Tamminen wrote:
On 06/25/2015 02:48 AM, Davin McCall wrote:
In terms of performance:
(export
Hi,
On 06/24/2015 05:53 AM, Matt Turner wrote:
On Tue, Jun 23, 2015 at 6:44 PM, Ian Romanick i...@freedesktop.org wrote:
Please quote the spec.
Section 6.5 Expressions of the draft C99 spec I have says (page 68, 80
of the pdf):
7 An object shall have its stored value accessed only by an
Hi,
On 06/30/2015 01:15 AM, Davin McCall wrote:
This is the third iteration of a patch to resolve a strict aliasing
problem in the exec_list structure.
At the suggestion of Francisco Jerez this is a return to the original
(v1) style of the patch, which replaces the three 'exec_node *' members
On Wed, Jul 1, 2015 at 8:26 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
On 1 July 2015 at 08:49, Ilia Mirkin imir...@alum.mit.edu wrote:
We want to require different versions for nouveau and nouveau_vieux.
autoconf will only check for NOUVEAU once if both drivers are enabled,
meaning both
From: Rob Clark robcl...@freedesktop.org
Fixes issue with gallium HUD. See this thread for details:
http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 143
From: Rob Clark robcl...@freedesktop.org
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/docs/source/tgsi.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 89ca172..4e869e7 100644
---
From: Ilia Mirkin imir...@alum.mit.edu
We need to distinguish a shader that has separate writes to each MRT
from one which is supposed to write the data from MRT 0 to all the MRTs.
In TGSI this is done with a property. NIR doesn't have that, so encode
it as a funny location and decode on the
From: Rob Clark robcl...@freedesktop.org
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/glsl/nir/nir_lower_phis_to_scalar.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/glsl/nir/nir_lower_phis_to_scalar.c
b/src/glsl/nir/nir_lower_phis_to_scalar.c
index a57d253..739170d
From: Rob Clark robcl...@freedesktop.org
Resend, with the patches that didn't yet get an explicit r-b (hint,
hint). No real changes, although did add a bit of info to the commit
msg for 2/4.
Also picked up a patch from Ilia for fixing MRT. This would be solved
differently after we gain some
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #5 from Béla Gyebrószki gyebr...@gmail.com ---
(In reply to Ilia Mirkin from comment #4)
Béla (or anyone else): would probably also be good to check that the *trace*
replays OK with the nvidia blob drivers. Sometimes wine will do
Hi,
If we wanted to avoid growing the size of exec_list to four pointers
instead of three, maybe we could store it in a union like below:
struct exec_list {
union {
struct {
struct exec_node head_sentinel;
struct exec_node *dummy_pointer_a;
};
struct {
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #4 from Ilia Mirkin imir...@alum.mit.edu ---
Béla (or anyone else): would probably also be good to check that the *trace*
replays OK with the nvidia blob drivers. Sometimes wine will do different
things there since it has more support
The patch that follows implements DRI3 support for EGL API. Most of the
code is directly ported from dri3_glx.c, with changes to match the EGL
API and to fit the style of egl_dri2 driver. And most of the code
specific to DRI3 lives in platform_x11_dri3.c (and .h). It depends on
another patch [1]
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #11 from Béla Gyebrószki gyebr...@gmail.com ---
(In reply to Ilia Mirkin from comment #9)
Fix for the color issue available at:
http://patchwork.freedesktop.org/patch/53425/
Béla, any chance you could supply a screenshot of what
Rob Clark robdcl...@gmail.com writes:
From: Rob Clark robcl...@freedesktop.org
Fixes issue with gallium HUD. See this thread for details:
http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html
I had to apply and git show -b to make any sense of this.
This block is getting
Rob Clark robdcl...@gmail.com writes:
From: Ilia Mirkin imir...@alum.mit.edu
We need to distinguish a shader that has separate writes to each MRT
from one which is supposed to write the data from MRT 0 to all the MRTs.
In TGSI this is done with a property. NIR doesn't have that, so encode
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #9 from Ilia Mirkin imir...@alum.mit.edu ---
Fix for the color issue available at:
http://patchwork.freedesktop.org/patch/53425/
Béla, any chance you could supply a screenshot of what the models are supposed
to look like? They don't
Fixes: (Flickering shadows in unreleased title trace)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80500
https://bugs.freedesktop.org/show_bug.cgi?id=91173
On Wed, Jul 1, 2015 at 10:16 AM, Mike Stroyan m...@lunarg.com wrote:
When there are no color buffer render targets, gen6 and gen7
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #12 from Ilia Mirkin imir...@alum.mit.edu ---
The problem draw appears to be the one at call 838845. The previous one 838747
still doesn't show any bits of the model.
It uses a vertex program (ARB_fp) with indirect constbuf
Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced
proper transferops handling, but in updating the source to the newly
allocated temporary image neglected to reset the source packing. Set it
to the default which should be appropriate for the floats used.
Fixes: 4b249d2ee
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #14 from Ilia Mirkin imir...@alum.mit.edu ---
Erm... ok...
MOV R0.zw, c[A0.x + 9];
MOV R1.x, c[0].w;
ADD R0.x, c[A0.x + 9].y, R1;
FLR R0.y, R0.x;
vs
0: MAD TEMP[0].xy, IN[1], CONST[7]., CONST[7].
3: MOV TEMP[0].zw,
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
On 2015-07-01 11:51:39, Connor Abbott wrote:
From: Connor Abbott cwabbo...@gmail.com
Before, we were setting payload_last_use_ip for unused payload
registers to 0, which made them interfere with whatever the first
instruction wrote to due
Personally, I think this is sensible given that, in the generator, we
just copy+paste the fixed_hw_reg field. However, I'd like a second
opinion.
--Jason
On Wed, Jul 1, 2015 at 11:51 AM, Connor Abbott cwabbo...@gmail.com wrote:
sources with file == HW_REG get all their information from the
Seems reasonable to me.
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Thu, Jul 2, 2015 at 7:18 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced
proper transferops handling, but in updating the source to the newly
allocated
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Thu, Jul 2, 2015 at 4:16 AM, Mike Stroyan m...@lunarg.com wrote:
When there are no color buffer render targets, gen6 and gen7 still
use the first BLEND_STATE element to determine alpha test.
gen6_upload_blend_state was allocating zero elements when
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #13 from Ilia Mirkin imir...@alum.mit.edu ---
Created attachment 116854
-- https://bugs.freedesktop.org/attachment.cgi?id=116854action=edit
tgsi shader generated by that program
Note that the headers of that program have stuff like
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #15 from Ilia Mirkin imir...@alum.mit.edu ---
The following patch fully fixes the problem for me (in addition to the color
thing obviously). Still need to figure out exactly which opt is broken. Kinda
tempted to just remove the whole
On 2015-07-01 11:51:37, Connor Abbott wrote:
From: Jordan Justen jordan.l.jus...@intel.com
If a source register in the push constant registers uses more than on
Doh. I have to point out my own typo. :)
on=one
register, then we wouldn't update payload_last_use_ip for subsequent
registers.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
On 2015-07-01 11:51:35, Connor Abbott wrote:
The second source always stays within the same SIMD8 register.
Signed-off-by: Connor Abbott connor.w.abb...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
1 file changed, 2
On 2015-07-01 11:51:38, Connor Abbott wrote:
From: Connor Abbott cwabbo...@gmail.com
regs_read() will handle LINTERP for us since the previous commit. In
addition, we were being too conservative, since it will only read 2
registers on SIMD8.
instructions in affected programs: 9061 -
On 01/07/15 16:46, Eero Tamminen wrote:
Hi,
On 06/30/2015 01:15 AM, Davin McCall wrote:
This is the third iteration of a patch to resolve a strict aliasing
problem in the exec_list structure.
At the suggestion of Francisco Jerez this is a return to the original
(v1) style of the patch, which
On Wed, Jul 1, 2015 at 12:18 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced
proper transferops handling, but in updating the source to the newly
allocated temporary image neglected to reset the source packing. Set it
to the
This is more consistent with how we do it in the FS backend, and reduces
a tiny bit of duplication. It'll also allow for a bit more tidying.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_gs.c | 5 +
src/mesa/drivers/dri/i965/brw_vec4.cpp | 7
When there are no color buffer render targets, gen6 and gen7 still
use the first BLEND_STATE element to determine alpha test.
gen6_upload_blend_state was allocating zero elements when
ctx-Color.AlphaEnabled was false.
That left _3DSTATE_CC_STATE_POINTERS or _3DSTATE_BLEND_STATE_POINTERS
pointing
On Wed, Jul 1, 2015 at 3:21 AM, Francisco Jerez curroje...@riseup.net wrote:
Jason Ekstrand ja...@jlekstrand.net writes:
Now that we can create builders with a bigger width than their parent as
long as it's exec_all, we don't need to create the instruction manually.
---
On Wed, Jul 1, 2015 at 8:02 AM, Rob Clark robdcl...@gmail.com wrote:
From: Rob Clark robcl...@freedesktop.org
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/glsl/nir/nir_lower_phis_to_scalar.c | 1 +
1 file changed, 1 insertion(+)
diff --git
This patch:
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Wed, Jul 1, 2015 at 5:02 PM, Rob Clark robdcl...@gmail.com wrote:
From: Rob Clark robcl...@freedesktop.org
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/docs/source/tgsi.rst | 1 +
1 file changed, 1
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #6 from Ilia Mirkin imir...@alum.mit.edu ---
The plot thickens... it actually renders fine on HSW (i965) on mesa 10.3.7, but
fails with (approx) HEAD. Actually I'm not 100% sure if it's fine, but it's
definitely nowhere near as messed
On 29.06.2015 23:18, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
Absolute timeouts are used with the amdgpu kernel driver.
It also makes waiting for several variables and fences at the same time
easier (the timeout doesn't have to be recalculated after every wait call).
On 07/01/2015 01:46 AM, Jason Ekstrand wrote:
Ok, I think I've looked through more-or-less the whole thing. The
only thing I haven't looked at is the texturing stuff but I think I'd
like (and Ken agrees) to just refactor the old code to split the guts
into something re-usable and make a much
We want to require different versions for nouveau and nouveau_vieux.
autoconf will only check for NOUVEAU once if both drivers are enabled,
meaning both version checks don't get executed. Rename the nouveau_vieux
one to NVVIEUX to avoid the issue.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
On 07/01/2015 04:49 PM, Ilia Mirkin wrote:
We want to require different versions for nouveau and nouveau_vieux.
autoconf will only check for NOUVEAU once if both drivers are enabled,
meaning both version checks don't get executed. Rename the nouveau_vieux
one to NVVIEUX to avoid the issue.
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #1 from Ilia Mirkin imir...@alum.mit.edu ---
Reproduced on nvc0. Might be nice to verify on a radeon or i965, but most
likely a core or at least gallium bug if it repros on swrast as well.
--
You are receiving this mail because:
You
On 01/07/15 01:37, Jason Ekstrand wrote:
If we can avoid duplication in the texturing code, that would be
really nice. Could we do this as a refactor of the old code and then
a much smaller NIR function that calls some shared code?
We worked under the assumption that the IR path would be
Forgot to mention that I was running piglit on platform x11_egl.
Actually, I found egl and glx on dri2 both passes this test, but
glx/dri3 fails. That's why you saw the failure without my patch.
Regards,
Boyan Ding
2015-07-02 10:58 GMT+08:00 Michel Dänzer mic...@daenzer.net:
On 02.07.2015
Seems fair.
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Thu, Jul 2, 2015 at 10:22 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
The optimization logic relies on being able to read out constbuf values
from program parameters. However that only works if there's no relative
addressing involved.
Brian, what happened to this series? Was there some conflict with DSA
and so you held off?
On Sat, Dec 13, 2014 at 9:42 AM, Brian Paul bri...@vmware.com wrote:
One of the two new functions in GL_ARB_get_texture_sub_image.
---
src/mesa/main/texgetimage.c | 305
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #17 from Béla Gyebrószki gyebr...@gmail.com ---
(In reply to Ilia Mirkin from comment #16)
The second issue is fixed for real by
http://patchwork.freedesktop.org/patch/53442/
Confirming, the patch fixes the remaining issue in the
On Wed, Jul 1, 2015 at 3:22 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
The optimization logic relies on being able to read out constbuf values
from program parameters. However that only works if there's no relative
addressing involved.
Bugzilla:
On 02.07.2015 00:31, Boyan Ding wrote:
piglit shows only one regression, gl-1.0-swapbuffers-behavior went from
pass to fail (quite strange, I don't know why).
That test also breaks when enabling DRI3 without your patch.
--
Earthling Michel Dänzer |
https://bugs.freedesktop.org/show_bug.cgi?id=90264
--- Comment #31 from Furkan fal...@gmail.com ---
FWIW, I tried temporarily enabling DRI3, and the effect for me is exactly the
same as it is with DRI2.
I have other problems with DRI3 and Chrome (that's why I keep it disabled), but
that's a
On 01/07/15 22:30, bugzilla-dae...@freedesktop.org wrote: *Comment # 14
https://bugs.freedesktop.org/show_bug.cgi?id=91173#c14
on bug 91173 https://bugs.freedesktop.org/show_bug.cgi?id=91173 from
Ilia Mirkin mailto:imir...@alum.mit.edu *
Erm... ok...
MOV R0.zw, c[A0.x + 9];
MOV R1.x,
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #10 from Ilia Mirkin imir...@alum.mit.edu ---
Created attachment 116850
-- https://bugs.freedesktop.org/attachment.cgi?id=116850action=edit
screenshot with HEAD + color patch
OK, so I guess the model is a little wrong :) Looks like
Paul's original code had emit_control_data_bits() skip the URB write if
vertex_count was 0. This meant wrapping every control data write in a
conditional write.
We accumulate control data bits in a single UD (32-bit) register. For
simple shaders that don't emit many vertices, the control data
The last patch left the code indented too far.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 142 +++---
1 file changed, 70 insertions(+), 72 deletions(-)
diff --git
Prefer blit-based texture transfers only if the chip has dedicated VRAM
since it would translate to a copy into the same memory on shared-memory
chips.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reported-by: Ilia Mirkin imir...@alum.mit.edu
---
Amended locally to put this back into the supported caps section
(but at the bottom), rather than the non-boolean caps section. Will
push this out shortly.
On Wed, Jul 1, 2015 at 10:36 PM, Alexandre Courbot acour...@nvidia.com wrote:
Prefer blit-based texture transfers only if the chip has
https://bugs.freedesktop.org/show_bug.cgi?id=91173
--- Comment #16 from Ilia Mirkin imir...@alum.mit.edu ---
The second issue is fixed for real by
http://patchwork.freedesktop.org/patch/53442/
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Certain compressed formats require this setting. The docs don't go into much
detail as to why it's needed exactly.
This fixes 0 piglit failures with a GBM gpu piglit run.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
I had this one sitting around for almost 2 months. I'm not sure why I
Assuming this passes piglit,
Reviewed-by: Connor Abbott cwabbo...@gmail.com
On Wed, Jul 1, 2015 at 4:00 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
---
src/glsl/nir/nir.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/glsl/nir/nir.c
At this point, the brw_vs_compile structure only contains the key and
gl_vertex_program pointer. We may as well pass and store them directly;
it's simpler and more convenient (key- instead of vs_compile-key...).
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
This patch makes us only issue the performance warning about register
spilling if we actually spilled registers. We also use scratch space
for indirect addressing and the like.
This is basically commit c51163b0cf7aff0375b1a5ea4cb3da9d9e164044 for
the vec4 backend.
Signed-off-by: Kenneth Graunke
Jason plumbed this through a while back in the FS backend, but
apparently we were just passing NULL in the vec4 backend.
This patch passes brw in as intended.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_vec4.cpp| 2 +-
After tearing it out another level or two, and just passing the key and
vp directly, we can finally remove this struct. It also eliminates a
pointless memcpy() of the key.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 37
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