On Tue, 2015-08-04 at 21:20 +1000, Timothy Arceri wrote:
On Tue, 2015-08-04 at 08:24 +0300, Tapani Pälli wrote:
On 08/04/2015 01:27 AM, Timothy Arceri wrote:
On Mon, 2015-08-03 at 23:16 +1000, Timothy Arceri wrote:
On Mon, 2015-08-03 at 09:02 +0300, Tapani Pälli wrote:
Currently
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 89fdccb..540c655 100644
---
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.
The relevant enum values are
MIPTREE_LAYOUT_ALLOC_YTILED = 1 5
MIPTREE_LAYOUT_ALLOC_XTILED = 1 6
MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED |
On Tue, 2015-08-04 at 17:54 -0700, Jason Ekstrand wrote:
On Tue, Aug 4, 2015 at 5:09 PM, Jordan Justen jordan.l.jus...@intel.com
wrote:
I checked the extension spec, and it appears that like image
load/store, ssbo is only required in fragment and compute stages. I
don't think the ssbo
On Tue, Aug 4, 2015 at 11:18 PM, Matt Turner matts...@gmail.com wrote:
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.
The relevant enum values are
MIPTREE_LAYOUT_ALLOC_YTILED = 1 5
MIPTREE_LAYOUT_ALLOC_XTILED = 1 6
On Tue, 2015-08-04 at 14:08 -0700, Jordan Justen wrote:
On 2015-07-14 00:46:10, Iago Toral Quiroga wrote:
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
They only can be defined in the last position of the shader
storage blocks.
When an unsized array is used in different
On Wed, Aug 5, 2015 at 9:36 AM, Christian Zigotzky
chzigot...@xenosoft.de wrote:
Hi Oded,
Is the r600g driver ready for the Gallium3D infrastructure of big endian
hosts or did you only solve the wrong colors problem?
Cheers,
Christian
Hi Christian,
I'm only working on software rendering
On Tue, 2015-08-04 at 16:04 -0700, Jordan Justen wrote:
On 2015-08-04 15:12:06, Jordan Justen wrote:
On 2015-07-14 00:46:11, Iago Toral Quiroga wrote:
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
It also creates unop and triop expressions to tell the driver to
calculate the
On Tue, Jul 21, 2015 at 07:38:49PM +0300, Francisco Jerez wrote:
v2: Move the image_params array back to brw_stage_prog_data.
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 31 +++
src/mesa/drivers/dri/i965/brw_shader.h | 1 +
2 files changed, 32 insertions(+)
On Tue, 2015-08-04 at 14:08 -0700, Jordan Justen wrote:
On 2015-07-14 00:46:10, Iago Toral Quiroga wrote:
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
They only can be defined in the last position of the shader
storage blocks.
When an unsized array is used in different
On Wed, Aug 05, 2015 at 10:36:09AM +0300, Pohjolainen, Topi wrote:
On Tue, Jul 21, 2015 at 07:38:49PM +0300, Francisco Jerez wrote:
v2: Move the image_params array back to brw_stage_prog_data.
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 31
+++
On 04.08.2015 02:51, Alex Deucher wrote:
v2: fix tonga chip check
Reviewed-by: Marek Olšák marek.ol...@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
Reviewed-by: David Zhang david1.zh...@amd.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
The series is
On 08/05/2015 09:01 AM, Timothy Arceri wrote:
On Tue, 2015-08-04 at 21:20 +1000, Timothy Arceri wrote:
On Tue, 2015-08-04 at 08:24 +0300, Tapani Pälli wrote:
On 08/04/2015 01:27 AM, Timothy Arceri wrote:
On Mon, 2015-08-03 at 23:16 +1000, Timothy Arceri wrote:
On Mon, 2015-08-03 at 09:02
On 08/04/2015 05:10 PM, Timothy Arceri wrote:
On Tue, 2015-08-04 at 14:54 +0300, Tapani Pälli wrote:
Hi;
I've tried to understand more about AoA to review the linker changes.
Now I'm testing your patches (and taking currently closer look at 9/20).
Overall it looks fine, calling itself
We use the same dirty state for SSBOs and UBOs because they share the
same infrastructure.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 2 ++
2 files changed, 3 insertions(+)
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
v2:
- Add tessellation shader constants assignment
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 12
1 file
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c5c0d2c..748853c
This is the same we do for other things like uniforms because it ensures
optimal performance.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index f15c088..b08a53b 100644
---
Since these are a special kind of UBOs we emit them together reusing the
same infrastructure, however, we use a RAW surface so we can reuse
existing untyped read/write/atomic messages which include a pixel mask
header that we need to set to obtain correct behavior with helper
invocations of the
---
src/glsl/ast_to_hir.cpp | 25 +
src/glsl/glsl_types.h | 11 +++
2 files changed, 36 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 40fa664..37ad571 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@
The same we did for the fragment shader with commit 7452f18b.
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 1472f75..1fe08b8
The error location won't be right, but fixing that would require to check
for this as we process each type of AST node that can involve a variable
read.
---
src/glsl/ast_to_hir.cpp | 49 +
1 file changed, 49 insertions(+)
diff --git
---
src/glsl/nir/glsl_to_nir.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index be4cd66..aa96e40 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -1011,7 +1011,8 @@
Shader Storage Buffer Object will add new atomic functions that are not
associated with counters, so better have atomic counter-specific functions
explicitly include the word counter in their names.
---
src/glsl/builtin_functions.cpp | 30 +++---
1 file changed, 15
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
v2:
- Reduce the number of lines over 80 character line width
limit. (Thomas Hellan)
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/lower_ubo_reference.cpp | 190 +++
1 file
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/glsl/glsl_parser_extras.cpp
The first argument to SSBO atomics is a reference to a SSBO buffer variable
so we want to compute its block index and offset and provide these values
to an internal version of the intrinsic that takes them instead of the
buffer variable reference.
---
src/glsl/lower_ubo_reference.cpp | 141
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
v2:
- Add ShaderStorageBlockBinding to static_data.py
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
.../glapi/gen/ARB_shader_storage_buffer_object.xml | 36
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Otherwise we can expect odd things to happen if, for example, we ask
for the size of the attached buffer from shader code, since that
might query this value from the surface we uploaded and get random
results.
Signed-off-by: Samuel Iglesias
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
The returned drm buffer object has a size multiple of 4096 but that should not
be exposed to the API user, which is working with a different size.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/mesa/main/tests/enum_strings.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/main/tests/enum_strings.cpp
---
src/glsl/glsl_lexer.ll | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/glsl/glsl_lexer.ll b/src/glsl/glsl_lexer.ll
index efa0bb6..b9d700a 100644
--- a/src/glsl/glsl_lexer.ll
+++ b/src/glsl/glsl_lexer.ll
@@ -405,11 +405,11 @@ image2DShadow
From: Kristian Høgsberg k...@bitplanet.net
---
src/glsl/ast_to_hir.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 5427be5..40fa664 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2841,7
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
According to ARB_uniform_buffer_object spec:
If the parameter (starting offset or size) was not specified when the
buffer object was bound (e.g. if bound with BindBufferBase), or if no
buffer object is bound to index, zero is returned.
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Now std140 is not the only interface packing qualifier that can be used.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/ast.h | 10 +
src/glsl/ast_to_hir.cpp | 54
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Notice that Skylake needs to include a header in the sampler message
so it will need some tweaks to work there.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
The original GLSL IR intrinsics have been lowered to an internal
version that accepts a block index and an offset instead of a
SSBO reference.
---
src/glsl/nir/glsl_to_nir.cpp | 55 +++
src/glsl/nir/nir_intrinsics.h | 12 ++
2 files changed, 67
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/linker.cpp | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 5d7d77f..88da643 100644
---
These handle querying the buffer name attached to a giving binding point
as well as the start offset and size of that buffer.
---
src/mesa/main/get.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
It also creates unop and triop expressions to tell the driver to
calculate the unsized array length.
Two expressions are needed to do the calculation:
* The unop expression saves the ir_rvalue* whose length should be
calculated.
*
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
This commit also adds functions to calculate std430 base alignment and sizes
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/ast.h | 1 +
src/glsl/ast_to_hir.cpp | 20 +--
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Including TOP_LEVEL_ARRAY_SIZE and TOP_LEVEL_ARRAY_STRIDE queries.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/ir_uniform.h| 5 +
This is roughly the same as v3 (mostly with some review feedback addressed) but
it adds 3 new patches to the beginning of the series that implement
typed/untyped vec4 messages, which we need for vec4 SSBO support. These patches
where initially part of the ARB_shader_image_load_store series that
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/lower_ubo_reference.cpp | 65 ++--
1 file changed, 49 insertions(+), 16 deletions(-)
diff --git a/src/glsl/lower_ubo_reference.cpp
Since memory qualifiers are also keywords we need to do the same
trick we use for other keywords that can be used as layout qualifiers
to handle alternate capitalizations in desktop GLSL, like row_major, etc.
---
src/glsl/ast_to_hir.cpp | 31
src/glsl/glsl_parser.yy | 75
---
src/glsl/builtin_functions.cpp | 185 +
1 file changed, 185 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 826524d..879e27e 100644
--- a/src/glsl/builtin_functions.cpp
+++
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 49
1 file changed, 49 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
The original GLSL IR intrinsics have been lowered to an internal
version that accepts a block index and an offset instead of a
SSBO reference.
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 103 +
2 files
---
src/glsl/ast_to_hir.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index e834a46..518612d 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -811,8 +811,15 @@ do_assignment(exec_list
Buffer variables are the same as uniforms, only that read/write, so we want
the same treatment.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Francisco Jerez curroje...@riseup.net
See i965/fs: Introduce FS IR builder. for the rationale.
v2: Drop scalarizing VEC4 builder.
v3: Take a backend_shader as constructor argument. Improve handling
of debug annotations and execution control flags. Rename instr
variable.
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Defined in ARB_shader_storage_buffer_object extension.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/mesa/main/uniforms.c | 52
src/mesa/main/uniforms.h | 4
2
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
v2:
- Add tessellation shader constants support
v3:
- Add GLES 3.1 support.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/mesa/main/get.c | 7 +++
src/mesa/main/get_hash_params.py | 16
---
src/glsl/nir/glsl_to_nir.cpp | 36
src/glsl/nir/nir_intrinsics.h | 12 ++--
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 642affd..cbec2df 100644
---
From: Antia Puentes apuen...@igalia.com
Commit 1ca25ab (glsl: Do not eliminate 'shared' or 'std140' blocks
or block members) considered as active 'shared' and 'std140' uniform
blocks and uniform block arrays, but did not include the block array
elements. Because of that, it was possible to have
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 77
2 files changed, 79 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 9315e5a..41ef7b0 100644
---
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
They only can be defined in the last position of the shader
storage blocks.
When an unsized array is used in different shaders, it might be
converted in different sized arrays, avoid get a linker error
in that case.
v2:
- Rework error
From: Francisco Jerez curroje...@riseup.net
These functions handle the conversion of a vec4 into the form expected
by the dataport unit in message and message return payloads. The
conversion is not always trivial because some messages don't support
SIMD4x2 for some generations, in which case a
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Otherwise, generate a link time error as per the
ARB_shader_storage_buffer_object spec.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/glsl_types.cpp | 9 +++--
src/glsl/link_uniform_blocks.cpp | 17
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 76 ++
2 files changed, 77 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index ab1ff81..8cbf3b4 100644
---
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Notice that we should differentiate betweeb shader storage blocks and
uniform blocks, since they have different limits.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/linker.cpp | 43
---
src/glsl/nir/glsl_to_nir.cpp| 67 -
src/glsl/nir/nir_intrinsics.h | 2 +-
src/glsl/nir/nir_lower_phis_to_scalar.c | 2 +
3 files changed, 69 insertions(+), 2 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp
From: Francisco Jerez curroje...@riseup.net
Implement helper functions that can be used to construct and send
untyped and typed surface read, write and atomic messages to the
shared dataport unit.
v2: Split from the FS implementation.
v3: Rewrite to avoid evil array_reg, emit_collect and
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 71
1 file changed, 71 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index fde65e9..b247cf2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/link_uniforms.cpp | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp
index
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs.h | 3 ++
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/nir/glsl_to_nir.cpp | 10 ++
src/glsl/nir/nir_intrinsics.h | 9 +
2 files changed, 19 insertions(+)
diff --git a/src/glsl/nir/glsl_to_nir.cpp
v2:
- Mark it too for GLES 3.1
---
docs/GL3.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 8124383..823f009 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -164,7 +164,7 @@ GL 4.3, GLSL 4.30:
GL_ARB_program_interface_query
---
src/glsl/ast_function.cpp | 37 +
1 file changed, 37 insertions(+)
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index 0fb8928..c7d1591 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -142,6 +142,31 @@
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
When propagating std430 packing qualifier to the struct's members, new
glsl_types need to be created because the existing ones are const.
The new glsl_types are meant to replace the already defined one
taking into account that the field names
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
---
src/mesa/drivers/dri/i965/brw_vec4.h | 2 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 157 +
2 files changed, 159 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 3f73beb..ab1ff81 100644
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 62
1 file changed, 62 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index b247cf2..e46bc54 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++
On Thu, 2015-07-30 at 12:33 +0200, Iago Toral wrote:
On Wed, 2015-07-29 at 15:21 -0700, Ian Romanick wrote:
On 07/29/2015 07:01 AM, Samuel Iglesias Gonsalvez wrote:
From: Iago Toral Quiroga ito...@igalia.com
Currently, we only consider precision qualifiers at compile-time. This
On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size
From: Michel Dänzer michel.daen...@amd.com
Fixes a bunch of random (mostly tessellation related) piglit failures
since commit 7ac946e5 (glsl: Add constuctors for the common cases of
glsl_struct_field).
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/glsl/builtin_variables.cpp | 2 ++
On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
Shader Storage Buffer Object will add new atomic functions that are not
associated with counters, so better have atomic counter-specific functions
explicitly include the word counter in their names.
Reviewed-by: Timothy Arceri
On Wed, Aug 05, 2015 at 12:11:02PM +0300, Pohjolainen, Topi wrote:
On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are
On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size
Hi!
On 07/10/2015 01:12 PM, Marek Olšák wrote:
I wonder... do we still need XA considering that everybody can just
use glamor instead?
Marek
Just back from vacation so I late reply.
In the case of VMware/vmwgfx, the rendering setup latency is huge.
Glamor tries to accelerate everything.
On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
---
src/glsl/ast_to_hir.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index e834a46..518612d 100644
--- a/src/glsl/ast_to_hir.cpp
+++
Cc: Iago Toral Quiroga ito...@igalia.com
Cc: Jason Ekstrand jason.ekstr...@intel.com
---
src/glsl/nir/nir_lower_io.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 3c17929..71bfd34 100644
--- a/src/glsl/nir/nir_lower_io.c
+++
Iago Toral ito...@igalia.com writes:
On Tue, 2015-08-04 at 16:04 -0700, Jordan Justen wrote:
On 2015-08-04 15:12:06, Jordan Justen wrote:
On 2015-07-14 00:46:11, Iago Toral Quiroga wrote:
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
It also creates unop and triop expressions
Pohjolainen, Topi topi.pohjolai...@intel.com writes:
On Wed, Aug 05, 2015 at 10:36:09AM +0300, Pohjolainen, Topi wrote:
On Tue, Jul 21, 2015 at 07:38:49PM +0300, Francisco Jerez wrote:
v2: Move the image_params array back to brw_stage_prog_data.
---
thanks, this fixes the build for me.
Should I commit this marking you as reviewer?
On Wed, Aug 5, 2015 at 5:21 AM, Jan Vesely jan.ves...@rutgers.edu wrote:
On Tue, 2015-08-04 at 22:40 +0200, Zoltan Gilian wrote:
There is no MDOperand in llvm 3.5.
thanks, this fixes the build for me.
jan
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
On Wed, 2015-08-05 at 20:31 +1000, Timothy Arceri wrote:
Cc: Iago Toral Quiroga ito...@igalia.com
Cc: Jason Ekstrand jason.ekstr...@intel.com
---
src/glsl/nir/nir_lower_io.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi Rob,
I recreationally looked at your recent patch set and saw that you left the
comment above #define MAX_RENDER_TARGETS in
054526e49abb5e7fd49fed6f589cff6f1ab4c9f6. I think you intended to remove
this comment after this delivery.
If I am wrong, please disregard this message.
Regards,
Gustaw
https://bugs.freedesktop.org/show_bug.cgi?id=91556
--- Comment #2 from Serge Martin edb+freedesk...@sigluy.net ---
Hello
I didn't test your program, but it seems that dim_t on host side should be
defined with cl_long instead of long long.
See
On Wed, 2015-08-05 at 20:04 +1000, Timothy Arceri wrote:
On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
---
src/glsl/ast_to_hir.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index
Zoltán Gilián zoltan.gil...@gmail.com writes:
thanks, this fixes the build for me.
Should I commit this marking you as reviewer?
fixes the build for me hardly qualifies as a Tested-by. Also I've
noticed that you've pushed a few patches [1][2][3][4] without
Reviewed-by tag. Please stop.
[1]
On Wed, 2015-08-05 at 13:38 +0300, Francisco Jerez wrote:
Iago Toral ito...@igalia.com writes:
On Tue, 2015-08-04 at 16:04 -0700, Jordan Justen wrote:
On 2015-08-04 15:12:06, Jordan Justen wrote:
On 2015-07-14 00:46:11, Iago Toral Quiroga wrote:
From: Samuel Iglesias Gonsalvez
On Wed, 2015-08-05 at 13:45 +0200, Iago Toral wrote:
On Wed, 2015-08-05 at 20:04 +1000, Timothy Arceri wrote:
On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
---
src/glsl/ast_to_hir.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
On Wed, 2015-08-05 at 22:22 +1000, Timothy Arceri wrote:
On Wed, 2015-08-05 at 13:45 +0200, Iago Toral wrote:
On Wed, 2015-08-05 at 20:04 +1000, Timothy Arceri wrote:
On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
---
src/glsl/ast_to_hir.cpp | 9 -
1 file
On Wed, 2015-08-05 at 22:22 +1000, Timothy Arceri wrote:
On Wed, 2015-08-05 at 13:45 +0200, Iago Toral wrote:
On Wed, 2015-08-05 at 20:04 +1000, Timothy Arceri wrote:
On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
---
src/glsl/ast_to_hir.cpp | 9 -
1 file
Also I've
noticed that you've pushed a few patches [1][2][3][4] without
Reviewed-by tag. Please stop.
Yes, I've already been told to include patch versions and reviewer.
I'm sorry, I'll try not to screw it up again.
On Wed, Aug 5, 2015 at 1:55 PM, Francisco Jerez curroje...@riseup.net wrote:
Hi all,
Just thought I'd bump this with a little more info.
- I've tested this with the new i965 vec4 nir backend without regressions.
- I've got subroutine and varying AoA working I just need to do some
tessellation shader tests and then desktop support will be ready**. I'll send
a follow-up
Hi Oded,
Is the r600g driver ready for the Gallium3D infrastructure of big endian
hosts or did you only solve the wrong colors problem?
Cheers,
Christian
On 04 August 2015 at 6:57 PM, Oded Gabbay wrote:
On Mon, Aug 3, 2015 at 6:40 PM, Emil Velikov emil.l.veli...@gmail.com
Since the introduction of new gl_shader_stages in
commit a2af956963b6bc4d29f37485e44c98008d2ef077
Author: Fabian Bieler fabianbie...@fastmail.fm
Date: Fri Mar 7 10:19:09 2014 +0100
mesa: add tessellation shader enums
the translation table for the stage into the HW binding table edit
Stage ref cannot be queried for transform feedback.
Also simplify the build_stageref function by passing the
correct mode for uniforms.
Cc: Tapani Pälli tapani.pa...@intel.com
---
No piglit regressions, no program_interface_query CTS regressions.
src/glsl/linker.cpp | 10 --
1 file
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