Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_types.cpp | 6 ++
src/glsl/nir/nir_types.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/src/glsl/nir/nir_types.cpp b/src/glsl/nir/nir_types.cpp
index 62176f5..940c676 100644
--- a/src/glsl/nir/nir_types.cpp
+++ b/src/glsl/nir/nir_
On 8 August 2015 at 15:09, Rhys Kidd wrote:
> OpenGL 2.0 function StencilOp() is in part internally implemented via
> StencilOpSeparate(). This change happened some time ago, however the
> accompanying doxygen todo comment was not accordingly updated.
>
> Replace the outdated portion of this doxy
On Fri, 2015-08-14 at 15:30 -0700, Connor Abbott wrote:
> Less duplication and one less case to handle for doubles.
>
> Signed-off-by: Connor Abbott
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 ++--
> 1 file changed, 2 insertions(+), 14 deletions(-)
>
> diff --git a/src/
On Fri, 2015-08-14 at 15:30 -0700, Connor Abbott wrote:
> This way the caller doesn't have to initialize all 4 channels when they
> aren't using them.
>
> Signed-off-by: Connor Abbott
> ---
> src/glsl/nir/nir_builder.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src
I misinterpreted the alignmnet restriction in XY_FAST_COPY_BLT earlier.
Instead of checking pitch for 64KB alignmnet we need to check it for
tile widh alignment.
Signed-off-by: Anuj Phogat
Cc: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 18 +++---
1 file changed, 7 ins
This change is required by the later patches.
Cc: Ben Widawsky
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_misc_state.c| 8 +---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++-
src/mesa/drivers/dri/i965/i
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_blit.c | 25 +
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index c177eec..d15a64d 100644
--- a/src/mesa/driver
It takes care of using the correct tile width if we later use other tiling
patterns (e.g. Yf) for aux miptree.
Cc: Ben Widawsky
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/m
Current code checks the alignment restrictions only for Y tiling.
From Broadwell PRM vol 10:
"pitch is of 512Byte granularity for Tile-X: This means the tiled-x
surface pitch can be (512, 1024, 1536, 2048...)/4 (in Dwords)."
This patch adds the restriction for X tiling as well.
Cc: Ben Widaws
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_blit.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index f8606b8..c177eec 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.
Cc: Ben Widawsky
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 67 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++
2 files changed, 50 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b
A later patch in this series uses it to compute tile dimensions.
Cc: Ben Widawsky
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_misc_state.c| 10 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 39 +++
Reviewed-by: Timothy Arceri
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Reviewed-by: Timothy Arceri
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On Tue 11 Aug 2015, Nanley Chery wrote:
> From: Nanley Chery
>
> Combine the adjacent cases which have the same GL type in the switch statemnt.
>
> Signed-off-by: Nanley Chery
> ---
> src/mesa/main/formats.c | 152
> ++--
> 1 file changed, 17 insert
On Wed 12 Aug 2015, Nanley Chery wrote:
> My comment about making ASTC format detection simpler is a little
> subjective. I'm planning to remove it from the final patch if it's
> accepted. What this change allows in general is detecting compressed
> formats belonging to a certain category of compre
I'm hardly a build expert, but looks good to me.
Reviewed-by: Roland Scheidegger
Am 15.08.2015 um 00:22 schrieb Vinson Lee:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
> Signed-off-by: Vinson Lee
> ---
> scons/gallium.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Tue 11 Aug 2015, Nanley Chery wrote:
> From: Nanley Chery
>
> All compressed formats return GL_FALSE. Remove all switch cases for
> compressed formats. Compressed formats should be at the bottom of
> the switch statement, so ordering is still preserved.
>
> Cc: Jason Ekstrand
> Signed-off-by
On Tue 11 Aug 2015, Nanley Chery wrote:
> From: Nanley Chery
>
> Only uncompressed formats have a non-void type and actual components per
> pixel.
> Rename _mesa_format_to_type_and_comps to
> _mesa_uncompressed_format_to_type_and_comps and require callers to check if
> the format is not compress
On Fri, Aug 14, 2015 at 3:21 PM, Timothy Arceri wrote:
> On Fri, 2015-08-14 at 10:43 -0700, Anuj Phogat wrote:
>> On Fri, Aug 14, 2015 at 10:30 AM, Anuj Phogat wrote:
>> > On Mon, Aug 10, 2015 at 1:06 AM, Tapani Pälli
>> > wrote:
>> > > Signed-off-by: Tapani Pälli
>> > > ---
>> > > src/mesa/ma
While working on fp64 support for i965, I noticed a bunch of things that
were broken that weren't directly related to fp64 or weren't directly
related to i965. To help reduce the number of outstanding patches, I've
pulled out some of the ones that I think can land right now. So, here's
the result o
This can happen when the source of the compare was split by the SIMD
lowering pass. Potentially, we could allow the case where the exec size
of scan_inst is larger, and scan_inst has the right quarter selected,
but doing that seems a little more risky.
Signed-off-by: Connor Abbott
---
src/mesa/d
Signed-off-by: Connor Abbott
---
src/glsl/nir/nir_opcodes.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py
index df5b7e2..77c766b 100644
--- a/src/glsl/nir/nir_opcodes.py
+++ b/src/glsl/nir/nir_opcodes.py
@@ -510,
This makes intelligent autocomplete plugins much happier.
Signed-off-by: Connor Abbott
---
src/glsl/nir/nir_builder.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir_builder.h b/src/glsl/nir/nir_builder.h
index 9223e83..1745453 100644
--- a/src/glsl/nir/nir_builder.h
+++ b
There are various restrictions on what the hstride can be that depend on
the Gen, and now that we're using hstride == 2 for packing/unpacking
doubles, we're going to run into these restrictions a lot more often.
Pull them out into a separate function, and move the one restriction we
checked previou
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 386e9a2..5474eac 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers
This way the caller doesn't have to initialize all 4 channels when they
aren't using them.
Signed-off-by: Connor Abbott
---
src/glsl/nir/nir_builder.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_builder.h b/src/glsl/nir/nir_builder.h
index 1745453..9592b8
Signed-off-by: Connor Abbott
---
src/glsl/builtin_functions.cpp | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 2175c66..ac55170 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin
In some cases, we need to emit ALU instructions with a certain stride
due to a HW limitation. When splitting that instruction, we need to
respect the original stride when creating the temporaries we load from
and store into. Otherwise, we'll reintroduce the problem we were trying
to work around.
S
Less duplication and one less case to handle for doubles.
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_
Signed-off-by: Connor Abbott
---
src/glsl/ir_equals.cpp | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ir_equals.cpp b/src/glsl/ir_equals.cpp
index cc1964e..c6446f7 100644
--- a/src/glsl/ir_equals.cpp
+++ b/src/glsl/ir_equals.cpp
@@ -58,8 +58,13 @@ ir_consta
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ce1edc3..812648f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src
Signed-off-by: Connor Abbott
---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index c7628dc..44af5f3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/s
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
Signed-off-by: Vinson Lee
---
scons/gallium.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/scons/gallium.py b/scons/gallium.py
index 51b84d7..46dbf0e 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -300,6 +300,7 @@ def g
On Fri, 2015-08-14 at 10:43 -0700, Anuj Phogat wrote:
> On Fri, Aug 14, 2015 at 10:30 AM, Anuj Phogat wrote:
> > On Mon, Aug 10, 2015 at 1:06 AM, Tapani Pälli
> > wrote:
> > > Signed-off-by: Tapani Pälli
> > > ---
> > > src/mesa/main/teximage.c | 28
> > > 1 file c
On Fri, Aug 14, 2015 at 11:03 AM, Emil Velikov wrote:
> Hi Anuj,
>
> On 13 August 2015 at 22:51, Anuj Phogat wrote:
> ...
>> + if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS)
>> + ret_align *= multiplier;
> Out of curiosity, have you noticed if the compiler is clever enough to
> optimise the a
On Fri, Aug 14, 2015 at 11:19 AM, Matt Turner wrote:
> Ken added support for 2DArray (commit ec23d5197e) and 1DArray (commit
> 14ca61125) last year.
> ---
> src/mesa/drivers/common/meta_generate_mipmap.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/c
This test regresses a large number of tests in piglit and dEQP, for
example:
piglit.spec.oes_texture_float.oes_texture_float.snbgt2m64 (from piglit)
Standard Output
/tmp/build_root/m64/lib/piglit/bin/oes_texture_float -auto -fbo
oes-texture-float: error 0x502 at
/var/lib/jenkins/jobs/Leeroy/work
On Fri, Aug 14, 2015 at 2:34 PM, Eric Anholt wrote:
> Ilia Mirkin writes:
>
>> On Thu, Aug 13, 2015 at 7:19 PM, Eric Anholt wrote:
>>> Ilia Mirkin writes:
>>>
Signed-off-by: Ilia Mirkin
---
The blending-in-shader piglit test passed even without the flush,
which doesn't
Ilia Mirkin writes:
> On Thu, Aug 13, 2015 at 7:19 PM, Eric Anholt wrote:
>> Ilia Mirkin writes:
>>
>>> Signed-off-by: Ilia Mirkin
>>> ---
>>>
>>> The blending-in-shader piglit test passed even without the flush,
>>> which doesn't inspire me with confidence, but those piglit_draw_rect
>>> thin
Hi All,
Since I need to load osmesa and system GL api at the same time on Linux, I need
to compile 10.5.9 osmesa in a mangled way. After a simple fix in glapi.h:
/* Is this needed? It is incomplete anyway. */
/*
#ifdef USE_MGL_NAMESPACE
#define _glapi_set_dispatch _mglapi_set_dispatch
#de
Ken added support for 2DArray (commit ec23d5197e) and 1DArray (commit
14ca61125) last year.
---
src/mesa/drivers/common/meta_generate_mipmap.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c
b/src/mesa/drivers/common/meta_genera
On Fri, Aug 14, 2015 at 4:37 AM, Eduardo Lima Mitev wrote:
> When validating format+type+internalFormat for texture pixel operations
> on GLES3, the effective internal format should be used if the one
> specified is an unsized internal format. Page 127, section "3.8 Texturing"
> of the GLES 3.0.4
Hi Anuj,
On 13 August 2015 at 22:51, Anuj Phogat wrote:
...
> + if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS)
> + ret_align *= multiplier;
Out of curiosity, have you noticed if the compiler is clever enough to
optimise the above multiplication to a shift ?
Thanks
Emil
__
Marta landed a similar patch in master.
On Mon, Aug 10, 2015 at 1:06 AM, Tapani Pälli wrote:
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/main/multisample.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/main/multisample.c b/src/mesa/main/multisample.c
On Fri, Aug 14, 2015 at 10:30 AM, Anuj Phogat wrote:
> On Mon, Aug 10, 2015 at 1:06 AM, Tapani Pälli wrote:
>> Signed-off-by: Tapani Pälli
>> ---
>> src/mesa/main/teximage.c | 28
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/src/mesa/main/teximage.c b/src/
On Mon, Aug 10, 2015 at 1:06 AM, Tapani Pälli wrote:
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/main/teximage.c | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> index 3ea7b2a..c6fd0be 100644
> ---
On Mon, Aug 10, 2015 at 1:06 AM, Tapani Pälli wrote:
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/main/teximage.c | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> index fc69387..3ea7b2a 100644
> --- a/s
On Wed, Aug 12, 2015 at 11:30 PM, Tapani Pälli wrote:
> This is done so that following patch can use it to verify dimensions
> for multisample variants of glTex*Storage.
>
> v2: move function to header, use bool instead GLboolean
>
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/main/texstorage.c
I guess though you'd need these bits when implementing things like
ARB_fragment_shader_ordering? (Thus stuff actually looks useful but I
don't know if anybody wants to implement it in the near term.)
Roland
Am 14.08.2015 um 18:27 schrieb Francisco Jerez:
> The hardware documentation relating to
On Friday, August 14, 2015 01:36:40 PM Tapani Pälli wrote:
> Signed-off-by: Tapani Pälli
> ---
> src/glsl/builtin_types.cpp | 6 +++---
> src/glsl/glsl_lexer.ll | 7 ---
> 2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/src/glsl/builtin_types.cpp b/src/glsl/builtin_type
The hardware documentation relating to the UAV HW-assisted coherency
mechanism and UAV access enable bits is scarce and sometimes
contradictory, and there's quite some guesswork behind this commit, so
let me summarize the background first: HSW and later hardware have
infrastructure to support a str
On 08/12/2015 10:58 PM, Matt Turner wrote:
> If an immediate is written to multiple channels, we can load it in a
> single writemasked MOV.
>
> total instructions in shared programs: 6285144 -> 6261991 (-0.37%)
> instructions in affected programs: 718991 -> 695838 (-3.22%)
> helped:
I don't think this applies on top of the patch Matt sent yesterday to use
fewer moves for loading constants.
On Aug 14, 2015 4:56 AM, "Antia Puentes" wrote:
>
> Loads constants using integer as their register type, this is done
> for consistency with the FS backend.
> ---
> src/mesa/drivers/dri/i
Change the commit message to "mesa: fix target error checking in
glGetTexLevelParameter" and Reviewed-by: Timothy Arceri
On Thu, 2015-08-13 at 17:03 +0300, Tapani Pälli wrote:
> With non-dsa functions we need to do target error checking before
> _mesa_get_current_tex_object which would just call
On Fri, 2015-08-14 at 08:55 +0300, Tapani Pälli wrote:
>
> On 08/13/2015 11:54 AM, Timothy Arceri wrote:
> > I've sent a couple of follow-up patches I notice when reviewing
> > this.
> >
> >
> > On Thu, 2015-08-13 at 09:30 +0300, Tapani Pälli wrote:
> > > v2: code cleanup
> > >
> > > Signed-of
Fixes a crash in Piglit's
spec@arb_shader_subroutine@lin...@no-mutual-recursion.vert for me.
Signed-off-by: Kai Wasserbäch
---
Hey everyone,
I ran the Piglit quick test suite afterwards and haven't observed any
regressions over my previous quick run, but the crash went away. The test
itself pass
If the register types do not match and the instruction
that contains the final destination is saturated, register
coalescing generated non-equivalent code.
This did not happen when using IR because types usually
matched, but it is visible in nir-vec4.
For example,
mov vgrf7:D vgrf2:D
m
Loads constants using integer as their register type, this is done
for consistency with the FS backend.
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw
Reviewed-by: Tapani Pälli
On 08/14/2015 02:30 PM, Marta Lofstedt wrote:
From: Marta Lofstedt
The function glMemoryBarrierByRegion is part of
OpenGL ES 3.1 and OpenGL 4.5 core and compatibility
profiles.
Signed-off-by: Marta Lofstedt
---
src/mapi/glapi/gen/GL4x.xml | 6 +
With this fix, we can load the constants in NIR-vec4 as integers,
as it is done in the FS backend.
This is related to:
http://lists.freedesktop.org/archives/mesa-dev/2015-July/089899.html
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When validating format+type+internalFormat for texture pixel operations
on GLES3, the effective internal format should be used if the one
specified is an unsized internal format. Page 127, section "3.8 Texturing"
of the GLES 3.0.4 spec says:
"if internalformat is a base internal format, the ef
> -Original Message-
> From: Dave Airlie [mailto:airl...@gmail.com]
> Sent: Friday, August 14, 2015 12:43 PM
> To: Lofstedt, Marta
> Cc: Palli, Tapani; Marta Lofstedt; mesa-dev@lists.freedesktop.org
> Subject: Re: [Mesa-dev] [PATCH v2] gles/es3.1: Implement
> glMemoryBarrierByRegion
>
> On
From: Marta Lofstedt
The function glMemoryBarrierByRegion is part of
OpenGL ES 3.1 and OpenGL 4.5 core and compatibility
profiles.
Signed-off-by: Marta Lofstedt
---
src/mapi/glapi/gen/GL4x.xml | 6 +
src/mesa/main/shaderimage.c | 40
On 14 August 2015 at 20:27, Lofstedt, Marta wrote:
>> -Original Message-
>> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
>> Behalf Of Tapani Pälli
>> Sent: Friday, August 14, 2015 7:31 AM
>> To: Marta Lofstedt; mesa-dev@lists.freedesktop.org
>> Subject: Re: [Mesa-dev]
Signed-off-by: Tapani Pälli
---
src/glsl/builtin_types.cpp | 6 +++---
src/glsl/glsl_lexer.ll | 7 ---
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/glsl/builtin_types.cpp b/src/glsl/builtin_types.cpp
index ffbc5e6..b0156a1 100644
--- a/src/glsl/builtin_types.cpp
+++
> -Original Message-
> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
> Behalf Of Tapani Pälli
> Sent: Friday, August 14, 2015 7:31 AM
> To: Marta Lofstedt; mesa-dev@lists.freedesktop.org
> Subject: Re: [Mesa-dev] [PATCH v2] gles/es3.1: Implement
> glMemoryBarrierByRegion
v2: Set CB_TARGET_MASK to zero for compute resources (Marek).
Remove unnecessary use of util_range_add (Marek).
Fix crash on non-contiguous RAT setup.
v3: Unreference surface instead of calling destroy directly (Marek).
Non-contiguous RAT setup can occur when the kernel signature contains
v2: Set CB_TARGET_MASK to zero for compute resources (Marek).
Remove unnecessary use of util_range_add (Marek).
Fix crash on non-contiguous RAT setup.
Non-contiguous RAT setup can occur when the kernel signature contains
no global buffer arguments, but there are write-only image args.
In t
Michel Dänzer writes:
> From: Michel Dänzer
>
> raw_svector_ostream::flush() is now unnecessary and forbidden:
>
> CXX llvm/libclllvm_la-invocation.lo
> ../../../../../src/gallium/state_trackers/clover/llvm/invocation.cpp: In
> function 'clover::module {anonymous}::build_module_llvm(llvm
On 13 August 2015 at 22:59, Alex Deucher wrote:
> On Thu, Aug 13, 2015 at 5:29 PM, Emil Velikov
> wrote:
>> On 13/08/15 22:22, Emil Velikov wrote:
>>> On 13/08/15 18:11, Alex Deucher wrote:
On Thu, Aug 13, 2015 at 12:06 PM, Emil Velikov
wrote:
> On 13 August 2015 at 16:42, Alex D
On Fri, Aug 14, 2015 at 11:16 AM, Zoltan Gilian wrote:
> v2: Set CB_TARGET_MASK to zero for compute resources (Marek).
> Remove unnecessary use of cb_target_mask (Marek).
> Fix crash on non-contiguous RAT setup.
>
> Non-contiguous RAT setup can occur when the kernel signature contains
> no
On 8/14/15, Zoltan Gilian wrote:
> Remove unnecessary use of cb_target_mask (Marek).
This is an error, it should be "Remove unnecessary use of
util_range_add". I'll fix this in a moment.
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v2: Set CB_TARGET_MASK to zero for compute resources (Marek).
Remove unnecessary use of cb_target_mask (Marek).
Fix crash on non-contiguous RAT setup.
Non-contiguous RAT setup can occur when the kernel signature contains
no global buffer arguments, but there are write-only image args.
In t
On Thu, Aug 13, 2015 at 09:58:52PM -0700, Kenneth Graunke wrote:
> On Thursday, August 13, 2015 02:57:20 PM Martin Peres wrote:
> > On 07/08/15 23:13, Chris Wilson wrote:
> > > intel_update_winsys_renderbuffer_miptree() will release the existing
> > > miptree when wrapping a new DRI2 buffer, so we
On 14/08/15 08:35, Pohjolainen, Topi wrote:
On Thu, Aug 13, 2015 at 08:00:43PM +0300, Martin Peres wrote:
v2, Review from Francisco Jerez:
- avoid the camelCase for the booleans
- init the booleans using the sampler type
- force the initialization of all the components of the output register
Si
On 13/08/15 20:09, Ilia Mirkin wrote:
On Thu, Aug 13, 2015 at 1:00 PM, Martin Peres
wrote:
v2, Review from Francisco Jerez:
- avoid the camelCase for the booleans
- init the booleans using the sampler type
- force the initialization of all the components of the output register
Signed-off-by: M
On 14/08/15 08:42, Pohjolainen, Topi wrote:
On Thu, Aug 13, 2015 at 07:58:53PM +0300, Martin Peres wrote:
The code is heavily inspired from Francisco Jerez's code supporting the
image_load_store extension.
Backends willing to support this builtin should handle
__intrinsic_image_size.
v2: Based
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