Re: [Mesa-dev] [PATCH] i965: Advertise 65536 for GL_MAX_UNIFORM_BLOCK_SIZE.

On 09/09/2015 04:04 AM, Kenneth Graunke wrote: Our old value of 16384 is the minimum value. DirectX apparently requires 65536 at a minimum; that's also what nVidia and the Intel Windows driver advertise. AMD advertises MAX_INT. Ilia Mirkin noticed that "Shadow Warrior" uses UBOs larger than

Re: [Mesa-dev] [PATCH 3/3] radeonsi: don't update polygon offset state if it has no effect

On 07.09.2015 07:14, Marek Olšák wrote: > From: Marek Olšák This patch is Reviewed-by: Michel Dänzer Patches 1 & 2 are Acked-by: Michel Dänzer -- Earthling Michel Dänzer | http://www.amd.com

Re: [Mesa-dev] [PATCH] mesa: Match MESA_FORMAT_B5G6R5 for a shallow pixel format of GL_RGB

On Thu, Sep 03, 2015 at 11:08:11AM -0700, Ian Romanick wrote: > On 09/03/2015 09:05 AM, Chris Wilson wrote: > > If the user supplies a pixel format of GL_RGB + GL_UNSIGNED_SHORT_5_6_5 > > and specifies a generic unsized GL_RGB internal format, match that to a > > texture format of

[Mesa-dev] [RFC 1/2] nir: Add a new lowering pass nir_lower_vec_and_coalesce

This pass will propagate the destination components of a vecN instructions, as destination of the instructions that define its sources; if certain conditions are met. If all the components of the destination register in the vecN instruction can be propagated, the instruction is removed.

[Mesa-dev] [RFC 2/2] i965/nir/vec4: Activate lower_vec_and_coalesce pass on non-scalar shaders

Enable the lower_vec_and_coalesce pass on non-scalar shaders, after the shader is out of SSA-form and before passing lower_vec_to_movs. shader-db VS results against non-NIR before this patch: total instructions in shared programs: 1853747 -> 1804428 (-2.66%) instructions in affected programs:

Re: [Mesa-dev] [PATCH 1/3] gallium/radeon: add separate stencil level dirty flags

On 07.09.2015 07:17, Marek Olšák wrote: > From: Marek Olšák > > We will only do depth-only or stencil-only decompress blits, whichever is > needed by textures, instead of always doing both. > --- > src/gallium/drivers/r600/evergreen_state.c| 4 ++-- >

Re: [Mesa-dev] [PATCH 2/3] radeonsi: only do depth-only or stencil-only in-place decompression

On 07.09.2015 07:17, Marek Olšák wrote: > From: Marek Olšák > > instead of always doing both. > Usually, only depth is needed, so stencil decompression is useless. [...] > @@ -247,6 +256,7 @@ void si_flush_depth_textures(struct si_context *sctx, >

Re: [Mesa-dev] [PATCH] mesa: Match MESA_FORMAT_B5G6R5 for a shallow pixel format of GL_RGB

On Thu, Sep 3, 2015 at 6:05 PM, Chris Wilson wrote: > If the user supplies a pixel format of GL_RGB + GL_UNSIGNED_SHORT_5_6_5 > and specifies a generic unsized GL_RGB internal format, match that to a > texture format of MESA_FORMAT_B5G6R5 if supported by the hardware. >

[Mesa-dev] [PATCH] nvc0: keep track of cb bindings per buffer, use for upload settings

CB updates to bound buffers need to go through the CB_DATA endpoints, otherwise the shader may not notice that the updates happened. Furthermore, these updates have to go in to the same address as the bound buffer, otherwise, again, the shader may not notice updates. So we keep track of all the

Re: [Mesa-dev] [PATCH v4 (part2) 24/59] glsl: a shader storage buffer must be smaller than the maximum size allowed

On 08/09/15 19:50, Jordan Justen wrote: > On 2015-08-05 01:30:21, Iago Toral Quiroga wrote: >> From: Samuel Iglesias Gonsalvez >> >> Otherwise, generate a link time error as per the >> ARB_shader_storage_buffer_object spec. >> >> Signed-off-by: Samuel Iglesias Gonsalvez

Re: [Mesa-dev] [PATCH v4 (part2) 23/59] glsl: add std430 interface packing support to ssbo store and unsized array length

On 08/09/15 18:52, Jordan Justen wrote: > On 2015-08-05 01:30:20, Iago Toral Quiroga wrote: >> From: Samuel Iglesias Gonsalvez >> >> Signed-off-by: Samuel Iglesias Gonsalvez >> --- >> src/glsl/lower_ubo_reference.cpp | 65 >>

Re: [Mesa-dev] [PATCH v4 (part2) 20/59] glsl: Add parser/compiler support for std430 interface packing qualifier

On 31/08/15 08:38, Samuel Iglesias Gonsálvez wrote: > > > On 29/08/15 02:27, Jordan Justen wrote: >> On 2015-08-05 01:30:17, Iago Toral Quiroga wrote: >>> From: Samuel Iglesias Gonsalvez >>> >>> This commit also adds functions to calculate std430 base alignment and sizes

Re: [Mesa-dev] [PATCH] mesa: Match MESA_FORMAT_B5G6R5 for a shallow pixel format of GL_RGB

On Wed, Sep 9, 2015 at 11:25 AM, Chris Wilson wrote: > On Wed, Sep 09, 2015 at 11:11:59AM +0200, Erik Faye-Lund wrote: >> On Thu, Sep 3, 2015 at 6:05 PM, Chris Wilson >> wrote: >> > If the user supplies a pixel format of GL_RGB +

[Mesa-dev] [PATCH 7/9] softpipe: Add functions for computing mipmap level

These functions will be used by textureQueryLod. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 100 +-- src/gallium/drivers/softpipe/sp_tex_sample.h | 7 ++ 2 files changed, 101 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c

[Mesa-dev] [PATCH 1/9] tgsi: Remove trailing backslash in comment

It clearly is here by accident. --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c index 75cd0d5..9544623 100644 ---

[Mesa-dev] [PATCH 3/9] softpipe: Split compute_lambda_lod into two functions

textureQueryLod returns a vec2 with a mipmap information and a LOD. The latter needs to be not clamped. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 55 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c

[Mesa-dev] [PATCH 8/9] tgsi: Add code for handling lodq opcode

This introduces new vfunc in tgsi_sampler just for this opcode. I decided against extending get_samples vfunc to return the mipmap level and LOD - the function's prototype is already too scary and doing the sampling for textureQueryLod would be a waste of time. ---

[Mesa-dev] [PATCH 5/9] softpipe: Split code getting a filter into separate function

This function will be later used by textureQueryLod. The img_filter_func are optional, because textureQueryLod will not need them. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 53 +++- 1 file changed, 37 insertions(+), 16 deletions(-) diff --git

[Mesa-dev] [PATCH 2/9] softpipe: Fix textureLod with nonzero GL_TEXTURE_LOD_BIAS value.

The level-of-detail bias wasn't simply added in the explicit LOD case. This case seems to be tested only in piglit's fs-texturequerylod-nearest-biased test, which is currently skipped, as softpipe does not support textureQueryLod at the moment. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 2

[Mesa-dev] [PATCH 9/9] softpipe: Implement and enable textureQueryLod

Passes the shader piglit tests and introduces no regressions. This commit finally makes use of the refactoring in previous commits. --- src/gallium/drivers/softpipe/sp_screen.c | 2 +- src/gallium/drivers/softpipe/sp_tex_sample.c | 47 +++- 2 files changed, 47

[Mesa-dev] [PATCH 6/9] softpipe: Split 3D to 2D coords conversion into separate function.

This is to avoid tying the conversion to sampling - textureQueryLod will need to do the conversion too, but it does not do any sampling. So instead of a "sample" vfunc, there is a "convert" vfunc. The drawback of this approach is that a "noop" convert copies 3 arrays of floats. Would be nice to

[Mesa-dev] [PATCH 4/9] softpipe: Put mip_filter_func inside a struct

Putting this function pointer into a struct enables grouping of several related functions in a single place. For now it is just a single function, but the struct will be later extended with a mip_level_func for returning mip level. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 28

[Mesa-dev] [PATCH 0/9] Implement textureQueryLod in softpipe

The following patches do some preparatory refactoring in softpipe's sp_tex_sample.{c,h} before actually implementing the feature. There is also a patch that fixes softpipe's textureLod with bias. I caught this bug when finished the textureQueryLod implementation - one of four textureQueryLod

[Mesa-dev] [PATCH] i915: fixing driver crashes if too few vertices are submitted

Comparison with a signed expression and unsigned value is converted to unsigned value, reason for minus value is interpreted as a big unsigned value. For this case the "for" loop is going into unexpected behavior. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38109 Signed-off-by: Marius

Re: [Mesa-dev] [PATCH] i965: Don't tell the hardware about our UAV access.

Mark Janes writes: > Francisco Jerez writes: > >> Mark Janes writes: >> >>> When I tested this, I saw an intermittent BSW gpu hang. I haven't been >>> able to confirm that it is due to the host-mem-barrier test. >>> >> It

Re: [Mesa-dev] [PATCH] mesa: Match MESA_FORMAT_B5G6R5 for a shallow pixel format of GL_RGB

On Wed, Sep 09, 2015 at 11:11:59AM +0200, Erik Faye-Lund wrote: > On Thu, Sep 3, 2015 at 6:05 PM, Chris Wilson wrote: > > If the user supplies a pixel format of GL_RGB + GL_UNSIGNED_SHORT_5_6_5 > > and specifies a generic unsized GL_RGB internal format, match that to a >

[Mesa-dev] [Bug 80821] When LIBGL_ALWAYS_SOFTWARE is set, KHR_create_context is not supported

https://bugs.freedesktop.org/show_bug.cgi?id=80821 Emil Velikov changed: What|Removed |Added Status|NEW |RESOLVED

Re: [Mesa-dev] [PATCH] mesa: Match MESA_FORMAT_B5G6R5 for a shallow pixel format of GL_RGB

On Wed, Sep 09, 2015 at 12:09:40PM +0200, Erik Faye-Lund wrote: > On Wed, Sep 9, 2015 at 11:25 AM, Chris Wilson > wrote: > > On Wed, Sep 09, 2015 at 11:11:59AM +0200, Erik Faye-Lund wrote: > >> On Thu, Sep 3, 2015 at 6:05 PM, Chris Wilson >

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/fs: Fix hang on IVB and VLV with image format mismatch.

Ian Romanick writes: > On 09/03/2015 06:03 AM, Francisco Jerez wrote: >> IVB and VLV hang sporadically when an untyped surface read or write >> message is used to access a surface of format other than RAW, as may >> happen when there is a mismatch between the format

Re: [Mesa-dev] Adaptive Vsync

On Wed, 9 Sep 2015 09:11:50 -0400 Alex Deucher wrote: > > Oh, absolutely - I had no issues with "this needs changing". My issue > > was with the fact it took months to get that. Had I come up with a new > > patch, it would likely have taken a similar time, months again,

Re: [Mesa-dev] [PATCH] i965: Don't tell the hardware about our UAV access.

Am 09.09.2015 um 15:04 schrieb Roland Scheidegger: > Am 09.09.2015 um 05:56 schrieb Ian Romanick: >> On 08/15/2015 02:24 AM, Francisco Jerez wrote: >>> Roland Scheidegger writes: >>> I guess though you'd need these bits when implementing things like

[Mesa-dev] [PATCH mesa v2 2/2] nv30: Disable msaa unless requested from the env by NV30_MAX_MSAA

Some modern apps try to use msaa without keeping in mind the restrictions on videomem of older cards. Resulting in dmesg saying: [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list [ 1197.850654] nouveau

[Mesa-dev] [PATCH mesa v2 1/2] nv30: Fix color resolving for nv3x cards

We do not have a generic blitter on nv3x cards, so we must use the sifm object for color resolving. This commit divides the sources and dest surfaces in to tiles which match the constraints of the sifm object, so that color resolving will work properly on nv3x cards. Signed-off-by: Hans de Goede

[Mesa-dev] i965: Move resolve from state-update notification to draw

Since _mesa_update_state() may be called several times per draw call, we wish to be judicious about the amount of work we place inside the intel_update_state() callback. By moving the current HiZ/color resolves we need before drawing from out of the notify and into the draw itself, we can save a

Re: [Mesa-dev] [Nouveau] [PATCH mesa 2/3] nv30: Fix color resolving for nv3x cards

Hi, On 08-09-15 09:53, Hans de Goede wrote: Hi, On 07-09-15 21:55, Ilia Mirkin wrote: May I ask why you're doing 512x512 instead of 1024x1024? These are already scaled up coordinates, so 1024x1024 should work no? Or is it because of the seams on the edges? Do those not also appear with

Re: [Mesa-dev] [PATCH v6 2/2] drm/i915: Add soft-pinning API for execbuffer

On Wed, Sep 09, 2015 at 04:07:09PM +0200, Michał Winiarski wrote: > From: Chris Wilson > > Userspace can pass in an offset that it presumes the object is located > at. The kernel will then do its utmost to fit the object into that > location. The assumption is that

[Mesa-dev] [PATCH v1] i915: fixing driver crashes if too few vertices are submitted

Comparison with a signed expression and unsigned value is converted to unsigned value, reason for minus value is interpreted as a big unsigned value. For this case the "for" loop is going into unexpected behavior. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38109 Signed-off-by: Marius

[Mesa-dev] [PATCH 7/7] i965: Remove redundant test for NULL intel_texture_object

Having checked whether the base class (gl_texture_object) is NULL, we know that intel_texture_object itself cannot be NULL. Signed-off-by: Chris Wilson Cc: Jordan Justen Cc: Jason Ekstrand Cc: Kenneth Graunke

Re: [Mesa-dev] [PATCH v2] i915/aa: fixing anti-aliasing bug for thinnest width lines

On 09/09/2015 07:59 AM, Marius Predut wrote: On PNV platform, for 1 pixel line thickness or less, the general anti-aliasing algorithm gives up, and a garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the "thinnest" (one-pixel-wide), non-antialiased lines.

[Mesa-dev] [PATCH 3/7] i965: Move the predraw resolve from _mesa_update_state into brw_draw_prims()

Performing the HiZ/color resolves is a fairly heavyweight operation that we don't need to perform on every state update, only before use the unresolved surfaces in a draw call. Since we use meta operations to perform the resolve, we cannot do so from inside brw_draw_prims() itself (as that will

[Mesa-dev] [PATCH 1/7] vbo: Reorder clearing NeedFlush flag with performing the flush

When we come to flush the vertices, we need to clear the NeedFlush flag first before calling into the backend as that backend may trigger FLUSH_VERTICES() itself (through use of meta) before dirtying the vertex state. If the NeedFlush flag is still in place, we end up recursing into the backend

[Mesa-dev] [PATCH 4/7] i965: Move update_state from brw_meta_resolve_color() to after all resolves

Now that we moved the resolving from out of the _mesa_update_state() callback we can remove the trick of calling _mesa_update_state() again from inside the resolver (as we no longer need to adhere to the _mesa_update_state() contract). However, we still need to make sure that the context is up to

[Mesa-dev] [PATCH 2/7] vbo: Add a predraw resolve callback

A common problem with using HiZ and multisampling is that surfaces need to resolved prior to use. Currently i965 does this inside its state update hook, but that is a comparatively heavyweight operation that need not be performed so frequently. The obvious solution (and therefore fraught with

[Mesa-dev] [PATCH 5/7] i965: Remove redundant update_state from intelReadPixels()

The very first operation performed by _mesa_readpixels() is to call _mesa_update_state() - we do not need to do so ourselves. Signed-off-by: Chris Wilson Cc: Jordan Justen Cc: Jason Ekstrand Cc: Kenneth Graunke

[Mesa-dev] [PATCH 6/7] i965: Only resolve the textures if a _NEW_STATE state change is flagged

Only walk through the set of enabled TextureUnits looking for a texture that needs to be resolved if the context state flags a new texture. Note that this will miss if the client is rendering into a texture that it is reading from, though that needs explicit barriers (and futhermore no piglits

[Mesa-dev] [PATCH v2] i915/aa: fixing anti-aliasing bug for thinnest width lines

On PNV platform, for 1 pixel line thickness or less, the general anti-aliasing algorithm gives up, and a garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the "thinnest" (one-pixel-wide), non-antialiased lines. Lines rendered with zero Line Width are rasterized

Re: [Mesa-dev] Adaptive Vsync

On Sun, Sep 6, 2015 at 4:28 AM, Lauri Kasanen wrote: > On Sat, 5 Sep 2015 23:29:05 + > Albert Freeman wrote: > >> The reply from Eric Anholt made two suggestions that should not be >> difficult to implement for someone who made the patch in the first

Re: [Mesa-dev] [PATCH] i965: Don't tell the hardware about our UAV access.

Am 09.09.2015 um 05:56 schrieb Ian Romanick: > On 08/15/2015 02:24 AM, Francisco Jerez wrote: >> Roland Scheidegger writes: >> >>> I guess though you'd need these bits when implementing things like >>> ARB_fragment_shader_ordering? (Thus stuff actually looks useful but I >>>

Re: [Mesa-dev] [PATCH v1] i915: fixing driver crashes if too few vertices are submitted

On 09/09/2015 08:16 AM, Marius Predut wrote: Comparison with a signed expression and unsigned value is converted to unsigned value, reason for minus value is interpreted as a big unsigned value. For this case the "for" loop is going into unexpected behavior. Bugzilla:

Re: [Mesa-dev] [PATCH 9/9] softpipe: Implement and enable textureQueryLod

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: Passes the shader piglit tests and introduces no regressions. This commit finally makes use of the refactoring in previous commits. --- src/gallium/drivers/softpipe/sp_screen.c | 2 +- src/gallium/drivers/softpipe/sp_tex_sample.c | 47

Re: [Mesa-dev] [PATCH 8/9] tgsi: Add code for handling lodq opcode

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: This introduces new vfunc in tgsi_sampler just for this opcode. I decided against extending get_samples vfunc to return the mipmap level and LOD - the function's prototype is already too scary and doing the sampling for textureQueryLod would be a

Re: [Mesa-dev] [PATCH mesa v2 1/2] nv30: Fix color resolving for nv3x cards

On Wed, Sep 9, 2015 at 9:52 AM, Hans de Goede wrote: > We do not have a generic blitter on nv3x cards, so we must use the > sifm object for color resolving. > > This commit divides the sources and dest surfaces in to tiles which > match the constraints of the sifm object, so

Re: [Mesa-dev] [PATCH 0/9] Implement textureQueryLod in softpipe

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: The following patches do some preparatory refactoring in softpipe's sp_tex_sample.{c,h} before actually implementing the feature. There is also a patch that fixes softpipe's textureLod with bias. I caught this bug when finished the textureQueryLod

Re: [Mesa-dev] [PATCH mesa v2 2/2] nv30: Disable msaa unless requested from the env by NV30_MAX_MSAA

On Wed, Sep 9, 2015 at 9:52 AM, Hans de Goede wrote: > Some modern apps try to use msaa without keeping in mind the > restrictions on videomem of older cards. Resulting in dmesg saying: > > [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate > [ 1197.850648]

Re: [Mesa-dev] [PATCH 4/9] softpipe: Put mip_filter_func inside a struct

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: Putting this function pointer into a struct enables grouping of several related functions in a single place. For now it is just a single function, but the struct will be later extended with a mip_level_func for returning mip level. ---

Re: [Mesa-dev] [PATCH 3/9] softpipe: Split compute_lambda_lod into two functions

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: textureQueryLod returns a vec2 with a mipmap information and a LOD. The latter needs to be not clamped. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 55 1 file changed, 39 insertions(+), 16 deletions(-) diff

Re: [Mesa-dev] [PATCH 5/9] softpipe: Split code getting a filter into separate function

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: This function will be later used by textureQueryLod. The img_filter_func are optional, because textureQueryLod will not need them. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 53 +++- 1 file changed, 37

[Mesa-dev] [RFC libdrm] intel: Add support for softpin

Softpin allows userspace to take greater control of GPU virtual address space and eliminates the need of relocations. It can also be used to mirror addresses between GPU and CPU (shared virtual memory). Calls to drm_intel_bo_emit_reloc are still required to build the list of

[Mesa-dev] [PATCH 1/2] drm/i915/gtt: Allow adventurous users to select enable_ppgtt=3

While support for 48b ppgtt is here, parameter enabling it is not known to the sanitize function. Let's update it to allow selecting full_48bit_ppgtt using module parameter. Cc: Michel Thierry Cc: Mika Kuoppala Signed-off-by: Michał Winiarski

[Mesa-dev] [RFC libdrm] intel: Softpin support

The goal of this series is to start a discussion whether the interface and implementation of softpin support proposed for libdrm is acceptable by all interested parties. The i915 patches are added so that it's easy to apply the series on latest drm-intel-nightly and libdrm master and start using

[Mesa-dev] [PATCH v6 2/2] drm/i915: Add soft-pinning API for execbuffer

From: Chris Wilson Userspace can pass in an offset that it presumes the object is located at. The kernel will then do its utmost to fit the object into that location. The assumption is that userspace is handling its own object locations (for example along with

Re: [Mesa-dev] [PATCH 7/9] softpipe: Add functions for computing mipmap level

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: These functions will be used by textureQueryLod. --- src/gallium/drivers/softpipe/sp_tex_sample.c | 100 +-- src/gallium/drivers/softpipe/sp_tex_sample.h | 7 ++ 2 files changed, 101 insertions(+), 6 deletions(-) diff

Re: [Mesa-dev] [PATCH 6/9] softpipe: Split 3D to 2D coords conversion into separate function.

On 09/09/2015 04:35 AM, Krzesimir Nowak wrote: This is to avoid tying the conversion to sampling - textureQueryLod will need to do the conversion too, but it does not do any sampling. So instead of a "sample" vfunc, there is a "convert" vfunc. The drawback of this approach is that a "noop"

Re: [Mesa-dev] [Mesa-dev, 3/5] i965/fs: Set first_non_payload_grf in assign_curb_setup

Jordan Justen writes: > first_non_payload_grf may be updated in assign_urb_setup for FS or > assign_vs_urb_setup for VS. Patch looks good, but I think we should clarify in the commit message that we're doing this so that compute will get first_non_payload_grf set up

[Mesa-dev] [PATCH] gallium/ttn: Simplify control flow stack handling.

Instead of storing insertion points, we simply store a single stack of control flow nodes representing the nir_if / nir_loop we're currently filling in. When handling ELSE, we can simply switch to the current nir_if's else_list. When handling ENDIF or ENDLOOP, we move the cursor to after the

[Mesa-dev] [PATCH] tgsi/scan: add support to figure out max nesting depth

From: Rob Clark Sometimes a useful thing for compilers (or, for example, tgsi_to_nir) to know. And pretty trivial for scan to figure this out for us. Signed-off-by: Rob Clark --- src/gallium/auxiliary/tgsi/tgsi_scan.c | 16

Re: [Mesa-dev] [PATCH] tgsi/scan: add support to figure out max nesting depth

On Wednesday, September 09, 2015 06:31:06 PM Rob Clark wrote: > From: Rob Clark > > Sometimes a useful thing for compilers (or, for example, tgsi_to_nir) to > know. And pretty trivial for scan to figure this out for us. > > Signed-off-by: Rob Clark

Re: [Mesa-dev] [Mesa-dev, 4/5] i965/cs: Support texture sampling for CS

Jordan Justen writes: > Signed-off-by: Jordan Justen Looks good - maybe change the subject to i965: Set up sampler state for compute shaders since this really only sets up that part of the state. Reviewed-by: Kristian Høgsberg

Re: [Mesa-dev] [Mesa-dev, 3/5] i965/fs: Set first_non_payload_grf in assign_curb_setup

___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] i915: fixing driver crashes if too few vertices are submitted

On Wed, Sep 09, 2015 at 11:53:54AM -0700, Ian Romanick wrote: > On 09/09/2015 11:16 AM, Marius Predut wrote: > > Comparison with a signed expression and unsigned value > > is converted to unsigned value, reason for minus value is interpreted > > as a big unsigned value. For this case the "for"

Re: [Mesa-dev] i965/cs: Enable barrier in MEDIA_INTERFACE_DESCRIPTOR

Jordan Justen writes: > Enable barrier in MEDIA_INTERFACE_DESCRIPTOR if the program uses the > barrier() GLSL function. > > On Ivy Bridge and Haswell, this allows the piglit test > tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test > to pass. On

Re: [Mesa-dev] [PATCH] i965: Don't tell the hardware about our UAV access.

Mark Janes writes: > Francisco Jerez writes: > >> Mark Janes writes: >> >>> When I tested this, I saw an intermittent BSW gpu hang. I haven't been >>> able to confirm that it is due to the host-mem-barrier test. >>> >> It

Re: [Mesa-dev] [Mesa-dev, 5/5] i965/cs: Emit texture surfaces to enable CS sampling

Jordan Justen writes: > Signed-off-by: Jordan Justen > Reviewed-by: Kristian Høgsberg > --- > src/mesa/drivers/dri/i965/brw_context.h | 2 +- > src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++ > 2 files

Re: [Mesa-dev] [PATCH] meta: Use result of texture coordinate clamping operation

On Wed, Sep 9, 2015 at 11:13 AM, Ian Romanick wrote: > From: Ian Romanick > > Previously the result of the complicated clamp() expression just dropped > on the floor: clamp does not modify any of its parameters. Looking at > the surrounding code,

[Mesa-dev] [PATCH 06/11] nir/lower_vec_to_movs: Add a state struct

While we're here, we also fix up a couple of potential ralloc-parenting bugs. In particular, we were calling nir_src_copy with the shader as the mem context instead of the instruction. --- src/glsl/nir/nir_lower_vec_to_movs.c | 22 -- 1 file changed, 16 insertions(+), 6

[Mesa-dev] [PATCH 09/11] nir/lower_vec_to_movs: Get rid of start_idx and swizzle compacting

Previously, we did this thing with keeping track of a separate start_idx which was different from the iteration variable. I think this was a relic of the way that GLSL IR implements writemasks. In NIR, if a given bit in the writemask is unset then that channel is just "unused", not missing. In

[Mesa-dev] [PATCH 08/11] i965/vec4_nir: Use partial SSA form rather than full non-SSA

We made this switch in the FS backend some time ago and it seems to make a number of things a bit easier. --- src/mesa/drivers/dri/i965/brw_nir.c| 2 +- src/mesa/drivers/dri/i965/brw_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 ++--- 3 files

[Mesa-dev] [PATCH 05/11] nir/from_ssa: Use instr_rewrite_dest

--- src/glsl/nir/nir_from_ssa.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/glsl/nir/nir_from_ssa.c b/src/glsl/nir/nir_from_ssa.c index 084f43d..eaf883d 100644 --- a/src/glsl/nir/nir_from_ssa.c +++ b/src/glsl/nir/nir_from_ssa.c @@ -512,9 +512,7 @@

Re: [Mesa-dev] [PATCH] meta: Use result of texture coordinate clamping operation

On Wed, Sep 9, 2015 at 6:19 PM, Ian Romanick wrote: > On 09/09/2015 04:55 PM, Anuj Phogat wrote: >> On Wed, Sep 9, 2015 at 11:30 AM, Ian Romanick wrote: >>> I'm pretty sure our implementation of this extension is complete >>> rubbish. I have attached

Re: [Mesa-dev] [PATCH v4 (part2) 20/59] glsl: Add parser/compiler support for std430 interface packing qualifier

On 09/09/2015 03:32 AM, Samuel Iglesias Gonsálvez wrote: > On 31/08/15 08:38, Samuel Iglesias Gonsálvez wrote: >> On 29/08/15 02:27, Jordan Justen wrote: >>> Hmm, you quoted the extension spec, but the 4.30 spec has: "When using >>> the std430 storage layout, shader storage blocks will be laid out

Re: [Mesa-dev] [PATCH] meta: Use result of texture coordinate clamping operation

On Wed, Sep 9, 2015 at 11:30 AM, Ian Romanick wrote: > I'm pretty sure our implementation of this extension is complete > rubbish. I have attached an image from the blit-scaled test. This > result cannot be useful to anyone. > Resending it with link to the image in place

[Mesa-dev] [PATCH 04/11] nir: Add a function for rewriting instruction destinations

--- src/glsl/nir/nir.c | 24 src/glsl/nir/nir.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c index e173b21..0090b08 100644 --- a/src/glsl/nir/nir.c +++ b/src/glsl/nir/nir.c @@ -1175,6 +1175,30 @@

[Mesa-dev] [PATCH 01/11] nir: Fix a bunch of ralloc parenting errors

As of a10d4937, we would really like things associated with an instruction to be allocated out of that instruction and not out of the shader. In particular, you should be passing the instruction that will ultimately be holding the source into nir_src_copy rather than an arbitrary memory context.

[Mesa-dev] [PATCH 02/11] nir: Remove the mem_ctx parameter from ssa_def_rewrite_uses

--- src/glsl/nir/nir.c| 2 +- src/glsl/nir/nir.h| 2 +- src/glsl/nir/nir_control_flow.c | 2 +- src/glsl/nir/nir_from_ssa.c | 5 ++--- src/glsl/nir/nir_lower_alu_to_scalar.c| 6 ++

[Mesa-dev] [PATCH 07/11] nir/lower_vec_to_movs: Handle partially SSA shaders

--- src/glsl/nir/nir_lower_vec_to_movs.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c b/src/glsl/nir/nir_lower_vec_to_movs.c index e297cb8..7d31e36 100644 --- a/src/glsl/nir/nir_lower_vec_to_movs.c +++

[Mesa-dev] [PATCH 11/11] HACK: nir/lower_vec_to_movs: Coalesce into destinations of fdot instructions

This is labeled HACK because it relies on the validator not validating destination write-masks with respect to nir_op_infos[op].output_size and relies on the fact that the i965 vec4 hardware does an implicit splat of any dot-product results. Technically, nir_op_fdotN produces a single component

[Mesa-dev] [PATCH 10/11] nir/lower_vec_to_movs: Coalesce movs on-the-fly when possible

The old pass blindly inserted a bunch of moves into the shader with no concern for whether or not it was really needed. This adds code to try and coalesce into the destination of the instruction providing the value. Shader-db results for vec4 shaders on Haswell: total instructions in shared

[Mesa-dev] [PATCH 03/11] nir: Only unlink sources that are actually valid

--- src/glsl/nir/nir.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c index 9a22fea..e173b21 100644 --- a/src/glsl/nir/nir.c +++ b/src/glsl/nir/nir.c @@ -714,9 +714,16 @@ nir_instr_insert(nir_cursor cursor, nir_instr

[Mesa-dev] [PATCH 00/11] Various vec4 NIR improvements

This patch series started out with me suggesting to Eduardo that his coalescing pass would be easier if the shader was in partial SSA. So I started working towards getting the vec4 backend using partial SSA like the FS backend does. Then I started adding more stuff to lower_vec_to_movs and the

Re: [Mesa-dev] [PATCH] meta: Use result of texture coordinate clamping operation

On 09/09/2015 04:55 PM, Anuj Phogat wrote: > On Wed, Sep 9, 2015 at 11:30 AM, Ian Romanick wrote: >> I'm pretty sure our implementation of this extension is complete >> rubbish. I have attached an image from the blit-scaled test. This >> result cannot be useful to anyone.

Re: [Mesa-dev] [PATCH 00/10] i965: add ARB_shader_texture_image_samples support

On Thursday, August 27, 2015 11:48:29 PM Ilia Mirkin wrote: > This should include everything. I sent a test for textureSamples to > piglit a while ago, not sure how to test imageSamples -- apparently ms > images aren't entirely supported on i965? But I'm not sure via what > feat that happens. > >

Re: [Mesa-dev] [PATCH 2/2] glsl/cs: Initialize gl_LocalInvocationIndex in main()

On 08/23/2015 01:50 AM, Jordan Justen wrote: > We initialize gl_LocalInvocationIndex based on the extension spec > formula: > > gl_LocalInvocationIndex = > gl_LocalInvocationID.z * gl_WorkGroupSize.x * gl_WorkGroupSize.y + > gl_LocalInvocationID.y * gl_WorkGroupSize.x + >

Re: [Mesa-dev] [PATCH] ralloc: Use __attribute__((destructor)) instead of atexit(3)

On 09/07/2015 06:54 AM, Jose Fonseca wrote: > On 07/09/15 10:17, Jean-Sébastien Pédron wrote: >> On 04.09.2015 01:37, Matt Turner wrote: >>> You need to test for this support in configure.ac. It's as simple as >>> adding a call to AX_GCC_FUNC_ATTRIBUTE in the existing alphabetized >>> list and

[Mesa-dev] [PATCH 2/9] i965: Silence unused parameter warnings in intel_mipmap_tree.c

From: Ian Romanick The target parameter of compute_msaa_layout appears to be unused since 83b83fb when support for CMS textures was added for Gen7. The brw parameter of intel_get_non_msrt_mcs_alignment appears to be unused since e92fbdc when the GEN check (along with

[Mesa-dev] [PATCH 9/9] i915, i965: Silence unused parameter warnings in intel_batchbuffer_advance

From: Ian Romanick These only occurred in release builds, but they occurred in every file that included intel_batchbuffer.h. Lots of spam. :( intel_batchbuffer.h: In function 'intel_batchbuffer_advance': intel_batchbuffer.h:153:47: warning: unused parameter 'brw'

[Mesa-dev] [PATCH 6/9] i915: Silence unused parameter warnings

From: Ian Romanick intel_mipmap_tree.c: In function 'old_intel_miptree_unmap_raw': intel_mipmap_tree.c:726:51: warning: unused parameter 'intel' [-Wunused-parameter] intel_miptree_unmap_raw(struct intel_context *intel,

[Mesa-dev] [PATCH 7/9] i915, i965: Silence unused parameter warnings in intel_miptree_unmap_gtt

From: Ian Romanick intel_mipmap_tree.c: In function 'intel_miptree_unmap_gtt': intel_mipmap_tree.c:777:34: warning: unused parameter 'map' [-Wunused-parameter] struct intel_miptree_map *map, ^ intel_mipmap_tree.c:778:17: warning:

[Mesa-dev] [PATCH 1/9] i965: Silence unused parameter warnings in intel_fbo.c

From: Ian Romanick intel_fbo.c: In function 'intel_alloc_window_storage': intel_fbo.c:415:48: warning: unused parameter 'ctx' [-Wunused-parameter] intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,

[Mesa-dev] [PATCH 4/9] i965: Make intel_miptree_map_raw static

From: Ian Romanick This hasn't been used outside intel_mipmap_tree.c since d5d4ba9 started using meta instead of the blitter for PBO TexSubImage. While we're here, 1. s/intel_miptree_\([^_]\)_raw/miptree_\1_raw/g because we don't generally prefix static functions. 2.

[Mesa-dev] [PATCH 3/9] i915, i965: Silence unused parameter warnings in intel_mipmap_tree.h

From: Ian Romanick These only occurred in release builds, but they occurred in every file that included intel_mipmap_tree.h. Lots of spam. :( intel_mipmap_tree.h: In function 'intel_miptree_check_level_layer': intel_mipmap_tree.h:595:59: warning: unused parameter 'mt'

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