On Sep 22, 2015 10:01 PM, "Jason Ekstrand" wrote:
>
> It's possible that, if a vecN operation is involved in a phi node, that we
> could end up moving from a register to itself. If swizzling is involved,
> we need to emit the move but. However, if there is no swizzling, then the
> mov is a no-op
I don't know of any piglit tests that are currently broken. However, there
is nothing stopping a vecN instruction from getting source modifiers and
lower_vec_to_movs is run after we lower to source modifiers.
---
src/glsl/nir/nir_lower_vec_to_movs.c | 6 +-
1 file changed, 5 insertions(+), 1
It's possible that, if a vecN operation is involved in a phi node, that we
could end up moving from a register to itself. If swizzling is involved,
we need to emit the move but. However, if there is no swizzling, then the
mov is a no-op and we might as well not bother emitting it.
Shader-db resu
On Tue, Sep 22, 2015 at 11:01 PM, Kenneth Graunke wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/Makefile.am | 14 +++
> src/glsl/nir/tests/control_flow_tests.cpp | 155
> ++
> 2 files changed, 169 insertions(+)
> create mode 100644 s
On Tue, Sep 22, 2015 at 11:01 PM, Kenneth Graunke wrote:
> The NIR control flow modification API churns the block structure,
> splitting blocks, stitching them back together, and so on. Preserving
> information about block dominance is hard (and probably not worthwhile).
>
> This patch makes nir_
On Tue, Sep 22, 2015 at 11:01 PM, Kenneth Graunke wrote:
> Consider the case of "while (...) { break }". Or in NIR:
>
> block block_0 (0x7ab640):
> ...
> /* succs: block_1 */
> loop {
> block block_1:
> /* preds: block_0 */
>
It doesn't matter whether a write is saturated or not, in another
implementation it might even have been a separate opcode. This code was
most likely copied from the copy-propagation pass (where one does have
to distinguish saturation).
Signed-off-by: Ilia Mirkin
---
Haven't run this through pig
First three are
Reviewed-by: Jason Ekstrand
I'm going to need more brain power for the rest.
--Jason
On Tue, Sep 22, 2015 at 8:01 PM, Kenneth Graunke wrote:
> Consider the following NIR:
>
>block block_0;
>/* succs: block_1 block_2 */
>if (...) {
> block block_1;
> ...
On Wed, 2015-09-23 at 13:23 +1000, Timothy Arceri wrote:
> Previously the code was trying to get the packing type from the array
> not the
> interface.
>
> Cc: Ian Romanick
> Cc: Antia Puentes
I meant to add that there is a piglit test here [1] and that this fixes
the second bug mentioned in th
On Tue, Sep 22, 2015 at 7:50 PM, Kenneth Graunke wrote:
> On Tuesday, September 22, 2015 06:18:12 PM Jason Ekstrand wrote:
>> We don't use any of the code after the switch and, as far as I can tell, it
>> wouldn't work anyway. The only reason this wasn't causing us problems is
>> that it's all de
Previously the code was trying to get the packing type from the array not the
interface.
Cc: Ian Romanick
Cc: Antia Puentes
---
src/glsl/link_uniform_block_active_visitor.cpp | 6 ++
src/glsl/opt_dead_code.cpp | 7 ++-
2 files changed, 4 insertions(+), 9 deletions(-)
There is a bug where we mess up predecessors/successors due to the
ordering of unlinking/recreating edges/adding fake edges. In order to
fix that, I need everything in one routine.
However, calling block_add_normal_succs() isn't safe from
cleanup_cf_node() - it would crash trying to insert phi un
By performing the vertex counting in NIR, we're able to elide a ton of
useless safety checks around every EmitVertex() call:
total instructions in shared programs: 3952 -> 3720 (-5.87%)
instructions in affected programs: 3491 -> 3259 (-6.65%)
helped:11
HURT:
I need to do this in a second place, and I'd rather make a helper
function than cut and paste the code.
Signed-off-by: Kenneth Graunke
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir_control_flow.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
***UNCHANGED SINCE THE F
This is invalid, and causes disasters if we try to unlink successors:
removing the first will work, but removing the second copy will fail
because the block isn't in the successor's predecessor set any longer.
Signed-off-by: Kenneth Graunke
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir_valida
The NIR control flow modification API churns the block structure,
splitting blocks, stitching them back together, and so on. Preserving
information about block dominance is hard (and probably not worthwhile).
This patch makes nir_cf_extract() throw away all metadata, like we do
when adding/removi
Consider the case of "while (...) { break }". Or in NIR:
block block_0 (0x7ab640):
...
/* succs: block_1 */
loop {
block block_1:
/* preds: block_0 */
break
/* succs: block_2 */
}
block
Consider the following NIR:
block block_0;
/* succs: block_1 block_2 */
if (...) {
block block_1;
...
} else {
block block_2;
}
Calling split_block_beginning() on block_1 would break block_0's
successors: link_block() sets both successors of a block, so calling
l
Signed-off-by: Kenneth Graunke
---
src/glsl/Makefile.am | 14 +++
src/glsl/nir/tests/control_flow_tests.cpp | 155 ++
2 files changed, 169 insertions(+)
create mode 100644 src/glsl/nir/tests/control_flow_tests.cpp
For now, this only adds a singl
Calling unlink_blocks(block, block->successors[0]) will successfully
unlink the first successor, but then will shift block->successors[1]
down to block->successor[0]. So the successors[1] != NULL check will
always fail.
Signed-off-by: Kenneth Graunke
Reviewed-by: Connor Abbott
---
src/glsl/nir
This patch also introduces a lowering pass to convert the simple GS
intrinsics to the new ones. See the comments above that for the
rationale behind the new intrinsics.
This should be useful for i965; it's a generic enough mechanism that I
could see other drivers potentially using it as well, so
I left a bunch of code indented a level in the previous patch to make
the diff easier to read. But now we should fix that.
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 124 +++---
src/mesa/drivers/dri/i965/ge
On Tuesday, September 22, 2015 06:18:12 PM Jason Ekstrand wrote:
> We don't use any of the code after the switch and, as far as I can tell, it
> wouldn't work anyway. The only reason this wasn't causing us problems is
> that it's all dead and DCE cleans it up.
Huh, really? Right after that switc
On Tuesday, September 22, 2015 06:18:16 PM Jason Ekstrand wrote:
> ---
> src/mesa/program/prog_to_nir.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
> index ec61100..1bd735a 100644
> --- a/src/mesa/progr
On Tue, Sep 22, 2015 at 6:18 PM, Jason Ekstrand wrote:
> ---
Thanks Jason! The whole series is
Reviewed-by: Matt Turner
Feel free to add these shader-db results to this commit message:
instructions in affected programs: 72 -> 56 (-22.22%)
___
me
---
src/glsl/nir/nir_lower_alu_to_scalar.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/glsl/nir/nir_lower_alu_to_scalar.c
b/src/glsl/nir/nir_lower_alu_to_scalar.c
index 84d4943..9313fc0 100644
--- a/src/glsl/nir/nir_lower_alu_to_scalar.c
+++ b/src/glsl/nir/nir_lowe
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 20c063d..c681ae4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri
---
src/glsl/nir/nir_lower_vec_to_movs.c | 3 ++-
src/glsl/nir/nir_opcodes.py | 5 +
src/glsl/nir/nir_opt_algebraic.py| 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c
b/src/glsl/nir/nir_lower_vec_to_movs.c
index b7ee4e8..62
---
src/mesa/program/prog_to_nir.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index ec61100..1bd735a 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -527,8 +527,7 @@ ptn_d
---
src/glsl/nir/nir_lower_alu_to_scalar.c | 47 --
1 file changed, 22 insertions(+), 25 deletions(-)
diff --git a/src/glsl/nir/nir_lower_alu_to_scalar.c
b/src/glsl/nir/nir_lower_alu_to_scalar.c
index 710bb37..5ef5ec2 100644
--- a/src/glsl/nir/nir_lower_alu_to_sca
We don't use any of the code after the switch and, as far as I can tell, it
wouldn't work anyway. The only reason this wasn't causing us problems is
that it's all dead and DCE cleans it up.
---
src/glsl/nir/nir_lower_alu_to_scalar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
https://bugs.freedesktop.org/show_bug.cgi?id=92072
--- Comment #4 from Ilia Mirkin ---
FYI Marek has a fix: http://patchwork.freedesktop.org/patch/60146/
I tested it with this trace, and it seems to fix it.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the
On Tue, Sep 22, 2015 at 8:40 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> Broken by: d082c5324914212f76e45be497229c7a0681f706
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92072
>
> Cc: mesa-sta...@lists.freedesktop.org
Tested-by: Ilia Mirkin
Sorry, no idea what this defined busin
From: Marek Olšák
Broken by: d082c5324914212f76e45be497229c7a0681f706
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92072
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/state_tracker/st_cb_blit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/state_tracker/st_cb_bli
On Tue, Sep 15, 2015 at 11:37:22AM -0700, Kristian Høgsberg wrote:
> On Thu, Sep 10, 2015 at 03:35:18PM +0200, Iago Toral Quiroga wrote:
> > This is the same we do for other things like uniforms because it ensures
> > optimal performance.
> >
> > Reviewed-by: Jordan Justen
> > ---
> > src/mesa/d
On Sat, Sep 19, 2015 at 3:50 PM, Jordan Justen
wrote:
> Signed-off-by: Jordan Justen
> ---
> src/mesa/drivers/dri/i965/brw_compute.c | 57
> ++---
> src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
> src/mesa/drivers/dri/i965/intel_reg.h | 5 +++
> 3 files changed
On Sat, Sep 19, 2015 at 03:50:49PM -0700, Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> ---
> src/mesa/drivers/dri/i965/brw_compute.c | 57
> ++---
> src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
> src/mesa/drivers/dri/i965/intel_reg.h | 5 +++
> 3 files
On Thu, Sep 17, 2015 at 05:00:14PM +0100, Neil Roberts wrote:
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 6 ++
> src/mesa/drivers/dri/i965/intel_screen.c | 5 -
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mes
On Thu, Sep 17, 2015 at 05:00:13PM +0100, Neil Roberts wrote:
> I'm not too sure about the expression used to index into sample_map in
> the shader. It looks like if fract(coord.x) and fract(coord.y) are
> close to 1.0 then it would index outside of the array. However the
> code for 4 and 8 has the
On Tue, Sep 22, 2015 at 4:29 PM, Matt Turner wrote:
> On Mon, Sep 21, 2015 at 7:22 PM, Jason Ekstrand wrote:
>> On Mon, Sep 21, 2015 at 6:15 PM, Jason Ekstrand wrote:
>>>
>>> On Sep 21, 2015 5:45 PM, "Matt Turner" wrote:
On Mon, Sep 21, 2015 at 3:18 PM, Jason Ekstrand
wrote:
>>>
On Thu, Sep 17, 2015 at 05:00:12PM +0100, Neil Roberts wrote:
> The destination rectangle is now drawn at 4x4 the size and the shader
> code to calculate the sample number is adjusted accordingly.
> ---
> src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 22 +-
> 1 file chang
On Mon, Sep 21, 2015 at 7:22 PM, Jason Ekstrand wrote:
> On Mon, Sep 21, 2015 at 6:15 PM, Jason Ekstrand wrote:
>>
>> On Sep 21, 2015 5:45 PM, "Matt Turner" wrote:
>>>
>>> On Mon, Sep 21, 2015 at 3:18 PM, Jason Ekstrand
>>> wrote:
>>> > At this point, piglit is the same as for GLSL and the shad
On Tue, Sep 22, 2015 at 4:04 PM, Matt Turner wrote:
> On Fri, Sep 18, 2015 at 12:49 AM, Eduardo Lima Mitev wrote:
>> When both fadd and fmul instructions have at least one operand that is a
>> constant and it is only used once, the total number of instructions can
>> be reduced from 3 (1 ffma + 2
On Thu, Sep 17, 2015 at 05:00:10PM +0100, Neil Roberts wrote:
> When 16 samples are used the MCS buffer needs 64 bits per pixel.
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/
On Thu, Sep 17, 2015 at 05:00:11PM +0100, Neil Roberts wrote:
> In order to accomodate 16x MSAA, the starting sample pair index is now
> 3 bits rather than 2 on SKL+.
Hooray for bad docs. "PS Thread Payload for Normal Dispatch": SSPI is 2 bits
(R0.0.7:6) with 1 reserved for expansion.
> ---
> sr
On Fri, Sep 18, 2015 at 12:49 AM, Eduardo Lima Mitev wrote:
> When both fadd and fmul instructions have at least one operand that is a
> constant and it is only used once, the total number of instructions can
> be reduced from 3 (1 ffma + 2 load_const) to 2 (1 fmul + 1 fadd); because
> the constan
On 09/17/2015 03:19 PM, Arlie Davis wrote:
> Ok, here's v2 of the change, with the suggested edits.
So... I think this code is fine, and I admire the effort. I have a
couple concerns.
1. We have no way to test this, so it's quite possible something was broken.
2. This function is only used in t
total instructions in shared programs: 6596689 -> 6595563 (-0.02%)
instructions in affected programs: 103154 -> 102028 (-1.09%)
helped:253
HURT: 217
It's kind of a wash in terms of programs helped/hurt, but of the
programs helped
"r600g: apply disable workaround on all scissors" forgot to update
num_dw, fix it.
Fixes: fbb423b433 "r600g: apply disable workaround on all scissors"
Reported-and-tested-by: Markus Trippelsdorf
Signed-off-by: Grazvydas Ignotas
---
resending with s-o-b
src/gallium/drivers/r600/r600_state_commo
On Mon, Sep 21, 2015 at 12:39:14PM +0200, Iago Toral wrote:
> Hi Kristian,
>
> On Fri, 2015-09-18 at 16:56 -0700, Kristian Høgsberg wrote:
> > On Thu, Sep 10, 2015 at 03:35:16PM +0200, Iago Toral Quiroga wrote:
> > > Hi,
> > >
> > > this is the latest version of the ARB_shader_storage_buffer_obje
This looks good. Just some nits below.
On Fri, Sep 4, 2015 at 9:47 PM, Bas Nieuwenhuizen
wrote:
> As the alignment requirements can be 32 KiB or more, also adding
> an aligned buffer creation function.
>
> Signed-off-by: Bas Nieuwenhuizen
> ---
> src/gallium/drivers/radeon/r600_buffer_common.c
On Tue, Sep 22, 2015 at 9:53 AM, Antia Puentes wrote:
> Gen6 MATH instructions can not execute in align16 mode, so swizzles or
> writemasking are not allowed.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92033
> ---
>
> I have tried to find an example where the writemask check is str
On 09/17/2015 09:00 AM, Neil Roberts wrote:
> In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
> takes two parameters for the MCS data. This patch makes it allocate a
> register that is twice as big for the MCS data and then always use
> the wider version.
> ---
> src/mesa/dr
On 09/17/2015 09:00 AM, Neil Roberts wrote:
> I'm not too sure about the expression used to index into sample_map in
> the shader. It looks like if fract(coord.x) and fract(coord.y) are
> close to 1.0 then it would index outside of the array. However the
> code for 4 and 8 has the same problem and
From: Ian Romanick
The old code had some significant problems with respect to
sampler2DArray textures. The biggest problem was that some of the code
would use vec3 for the texture coordinate type, and other parts of the
code would use vec2. The resulting shader would not even compile.
Since the
This function isn't specific to miptrees. So, drop the "miptree"
from function name.
V3: Add a comment explaining how the 1D Array texture height and
depth is interpreted by Intel hardware.
Cc: Chad Versace
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_fbo.c | 2
On Wed, Sep 16, 2015 at 4:30 PM, Chad Versace wrote:
> On Wed 19 Aug 2015, Anuj Phogat wrote:
>> This function isn't specific to miptrees. So, drop the "miptree"
>> from function name.
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
>> src/mesa/d
https://bugs.freedesktop.org/show_bug.cgi?id=92072
--- Comment #3 from Samuel Pitoiset ---
I can also reproduce this bug on GF119 (nvc0 driver) with master, and
(obviously) reverting that commit fixes the issue, but the assert in
ext_framebuffer_blit/blit-early is back.
--
You are receiving thi
On Thu, Sep 17, 2015 at 05:00:08PM +0100, Neil Roberts wrote:
> When 16x MSAA is used for sampling with texelFetch the compiler needs
> to use a different instruction which passes more arguments for the MCS
> data. Previously on skl+ it was unconditionally using this new
> instruction. However sinc
On Thu, Sep 17, 2015 at 05:00:07PM +0100, Neil Roberts wrote:
> In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
> takes two parameters for the MCS data. The MCS data in the response
> still fits in a single register so we just need to ensure we copy both
> values rather than
On Thu, Sep 17, 2015 at 05:00:06PM +0100, Neil Roberts wrote:
> In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
> takes two parameters for the MCS data. This patch makes it allocate a
> register that is twice as big for the MCS data and then always use
> the wider version.
>
On Mon, Sep 21, 2015 at 11:03:41AM +0200, Samuel Iglesias Gonsálvez wrote:
>
>
> On 19/09/15 00:30, Kristian Høgsberg wrote:
> > On Thu, Sep 10, 2015 at 03:35:56PM +0200, Iago Toral Quiroga wrote:
> >> v2:
> >> - Fix ssbo loads with boolean variables.
> >>
> >> Reviewed-by: Connor Abbott
> >> --
On Mon, Sep 21, 2015 at 12:13:27PM +0200, Iago Toral wrote:
> On Fri, 2015-09-18 at 13:02 -0700, Kristian Høgsberg wrote:
> > On Thu, Sep 10, 2015 at 03:35:54PM +0200, Iago Toral Quiroga wrote:
> > > ---
> > > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 148
> > > +
>
https://bugs.freedesktop.org/show_bug.cgi?id=92072
Ilia Mirkin changed:
What|Removed |Added
Summary|Wine breackage since |Wine breakage since
|504
https://bugs.freedesktop.org/show_bug.cgi?id=92072
Ilia Mirkin changed:
What|Removed |Added
Component|Drivers/DRI/nouveau |Mesa core
Assignee|nouveau@lists
On 22/09/15 19:27, Jason Ekstrand wrote:
> On Tue, Sep 22, 2015 at 9:17 AM, Alejandro Piñeiro
> wrote:
>>
>> On 22/09/15 18:09, Jason Ekstrand wrote:
>>> On Tue, Sep 22, 2015 at 8:06 AM, Alejandro Piñeiro
>>> wrote:
Now it is more similar to brw_fs_copy_propagation, with three
clear
Previously we would not print a swizzle on ssa_52 when only its .x
component is used (as seen in the definition of ssa_53):
vec3 ssa_52 = fadd ssa_51, ssa_51
vec1 ssa_53 = flog2 ssa_52
vec1 ssa_54 = flog2 ssa_52.y
vec1 ssa_55 = flog2 ssa_52.z
But this makes the interpretation of the R
On Tue, Sep 22, 2015 at 9:17 AM, Alejandro Piñeiro wrote:
>
>
> On 22/09/15 18:09, Jason Ekstrand wrote:
>> On Tue, Sep 22, 2015 at 8:06 AM, Alejandro Piñeiro
>> wrote:
>>> Now it is more similar to brw_fs_copy_propagation, with three
>>> clear stages:
>>>
>>> 1) Build up the value we are propag
Gen6 MATH instructions can not execute in align16 mode, so swizzles or
writemasking are not allowed.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92033
---
I have tried to find an example where the writemask check is strictly needed
in order to avoid an incorrect register coalescing, bu
On 22/09/15 18:09, Jason Ekstrand wrote:
> On Tue, Sep 22, 2015 at 8:06 AM, Alejandro Piñeiro
> wrote:
>> Now it is more similar to brw_fs_copy_propagation, with three
>> clear stages:
>>
>> 1) Build up the value we are propagating as if it were the source of a
>> single MOV:
>> 2) Check that w
On Tue, Sep 22, 2015 at 8:06 AM, Alejandro Piñeiro wrote:
> Now it is more similar to brw_fs_copy_propagation, with three
> clear stages:
>
> 1) Build up the value we are propagating as if it were the source of a
> single MOV:
> 2) Check that we can propagate that value
> 3) Build the final value
The series is
Reviewed-by: Matt Turner
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
The function was a no-op and if the ctx->Driver.BindFramebuffer pointer
is null, Mesa won't try to use it.
---
src/mesa/state_tracker/st_cb_fbo.c | 12
1 file changed, 12 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_fbo.c
b/src/mesa/state_tracker/st_cb_fbo.c
index 5707590.
---
src/mesa/main/teximage.c | 2 +-
src/mesa/main/teximage.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 8913a72..9bc176a 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -130,7 +130,7 @@ a
---
src/mesa/main/bufferobj.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 23da83e..f87cea9 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -246,7 +246,7 @@ bufferobj_range_mapped(const str
---
src/mesa/main/texstorage.c | 3 ++-
src/mesa/main/texstorage.h | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/texstorage.c b/src/mesa/main/texstorage.c
index a29175e..9fd969f 100644
--- a/src/mesa/main/texstorage.c
+++ b/src/mesa/main/texstorage.c
@@ -202
Now it is more similar to brw_fs_copy_propagation, with three
clear stages:
1) Build up the value we are propagating as if it were the source of a
single MOV:
2) Check that we can propagate that value
3) Build the final value
Previously everything was somewhat messed up, making the
implementation
On 22 September 2015 at 13:43, Predut, Marius wrote:
> In the upstream code , 'nr' variable is used intensively in many places for
> things like :
> for (j = 0; j + 2 < count; j += nr ) {
> nr = MIN2( currentsz, count - j );
>
> But first time when it is used it isn't initialized.
> I was unable
In the upstream code , 'nr' variable is used intensively in many places for
things like :
for (j = 0; j + 2 < count; j += nr ) {
nr = MIN2( currentsz, count - j );
But first time when it is used it isn't initialized.
I was unable to find a place (a macro or something) where "nr" is
initializ
Reviewed-by: Samuel Iglesias Gonsálvez
On 17/09/15 09:02, Timothy Arceri wrote:
> V2: Handle arrays of arrays in the same way structures are handled
>
> The ARB_arrays_of_arrays spec doesn't give very many details on how
> AoA uniforms are intended to be implemented. However in the
> ARB_program
Reviewed-by: Samuel Iglesias Gonsálvez
On 17/09/15 09:03, Timothy Arceri wrote:
> ---
> src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index e6
Reviewed-by: Samuel Iglesias Gonsálvez
On 20/09/15 14:07, Timothy Arceri wrote:
> ---
> I noticed this problem after adding AoA support [1] to Ian's random UBO test
> script [2].
>
> [1] http://patchwork.freedesktop.org/patch/59956/
> [2] http://cgit.freedesktop.org/~idr/piglit/log/?h=ubo-lo
In the upstream code , 'nr' variable is used intensively in many places for
things like :
for (j = 0; j + 2 < count; j += nr ) {
nr = MIN2( currentsz, count - j );
But first time when it is used it isn't initialized.
I was unable to find a place (a macro or something) where "nr" is
initializ
On Tue, 2015-09-22 at 14:34 +0300, Tapani Pälli wrote:
> Patch fixes a crash in conformance test that tries out different
> invalid arguments for glShaderSource and glGetShaderSource:
>
>ES2-CTS.gtf.GL.glGetShaderSource.getshadersource_programhandle
>
> This is a regression from commit:
>
On Tue, 2015-09-22 at 08:10 +0200, Iago Toral wrote:
> Hi Mark,
>
> On Mon, 2015-09-21 at 17:45 -0700, Mark Janes wrote:
> > Hi Iago,
> >
> > According to my tests, this patch series fixes the gles2/gles3
> > "functional.uniform_api.random.23" tests in dEQP, on sandybridge.
> >
> > Do you see th
That should make tracking where we do spills and pull loads a bit easier.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 --
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 --
src/mesa/drivers/dri/i965/brw_inst.h | 6 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor
Originally, these could conflict with our spills, but now that we moved the
latter to MRFs 21..23, that is no longer the case. Still, in gen6 we
now use MRFs 1..15 for URB writes, so we probably want to make our pull
constant loads out of that MRF space (currently, they start at MRFs 13/14).
Even
So they do not conflict with our (un)spills (MRF 21..23) or our
URB writes (MRF 1..15)
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 --
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 225a312..81fe7f5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.
Patch fixes a crash in conformance test that tries out different
invalid arguments for glShaderSource and glGetShaderSource:
ES2-CTS.gtf.GL.glGetShaderSource.getshadersource_programhandle
This is a regression from commit:
04e201d0c02cd30ace5c6fe80e9f021ebb733682
Additions in v2 also fix fo
Hi all,
I apologize for forgetting to add Tapani as the reviewer for the patches I just
merged:
commit 6c3de8996fbe9447e092cc75ccdd6f720fabaf4d
commit cf293e518ebd847cb28e03d4378679c47548206d
commit 419210005a84f1f26da353b945b3f783d53fa56a
The patches was reviewed here:
http://lists.freedesktop.
On mar, 2015-09-22 at 11:22 +0200, Antía Puentes wrote:
> I realized that if writemasking is also unsupported I should probably
> update the patch to avoid coalescing if the dst_writemask parameter is
> different from XYWZ. The condition in "vec4_instruction::can_reswizzle"
> would be something lik
No functional changes.
Signed-off-by: Samuel Iglesias Gonsalvez
---
src/glsl/glsl_types.cpp | 140
1 file changed, 70 insertions(+), 70 deletions(-)
diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index 97c79fa..b4525eb 100644
---
---
src/glsl/glsl_types.cpp | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index b4525eb..07d7248 100644
--- a/src/glsl/glsl_types.cpp
+++ b/src/glsl/glsl_types.cpp
@@ -1351,7 +1351,7 @@ glsl_type::std140_size(bool row_ma
v2:
- Fix a missing check in has_layout()
v3:
- Mention shader storage block in error message for layout qualifiers
(Kristian).
Signed-off-by: Samuel Iglesias Gonsalvez
Reviewed-by: Jordan Justen
---
src/glsl/ast.h | 1 +
src/glsl/ast_to_hir.cpp | 21 +
v2:
- Remove inst->regs_written assignment as the instruction only
writes to one register.
Signed-off-by: Samuel Iglesias Gonsalvez
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 24
1 file changed, 24 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cp
No functional changes.
---
src/glsl/ast.h | 5 ++
src/glsl/glsl_parser.yy | 127 +---
src/glsl/glsl_parser_extras.cpp | 122 ++
3 files changed, 128 insertions(+), 126 deletions(-)
diff --git a/src/
They are used to calculate size, base alignment and array stride values
for a glsl_type following std430 rules.
v2:
- Paste OpenGL 4.3 spec wording as it mentions stride of array. (Jordan)
Signed-off-by: Samuel Iglesias Gonsalvez
Reviewed-by: Jordan Justen
---
src/glsl/glsl_types.cpp | 207 +++
The unsized array length is computed with the following formula:
array.length() =
max((buffer_object_size - offset_of_array) / stride_of_array, 0)
Of these, only the buffer size needs to be provided by the backends, the
frontend already knows the values of the two other variables.
This patch
v2:
- Get interface packing information from interface's type, not the
variable type.
- Simplify is_std430 condition in emit_access() for readability (Jordan)
- Add a commment explaing why array of three-component vector case is
different in std430 than the rest of cases.
- Add calls to std430_
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