Re: [Mesa-dev] New GBM backend for dEQP

On 12/17/2016 03:58 AM, Chad Versace wrote: Happy Christmas to everyone who's busy squashing dEQP bugs. I wrote a new GBM backend for dEQP. I even submitted it to dEQP's upstream Gerrit. Pyry, dEQP's maintainer, told me over beer earlier this year that he would accept it if I submitted it,

Re: [Mesa-dev] [PATCH] egl: Check config's surface types in eglCreate*Surface()

Reviewed-by: Tapani Pälli On 12/17/2016 03:59 AM, Chad Versace wrote: If the provided EGLConfig does not support the requested surface type, then emit EGL_BAD_MATCH. Fixes dEQP-EGL.functional.negative_api.create_pbuffer_surface on GBM. Cc: "13.0"

Re: [Mesa-dev] V7 Loop unrolling in NIR

On Sun, 2016-12-18 at 21:58 -0800, Jason Ekstrand wrote: > On Dec 18, 2016 9:48 PM, "Timothy Arceri" om> wrote: > V7: >  - paritally out of ssa in unrolling pass to avoid phis >  - lots of simplification/tidy ups in the analysis pass >  - if_uses bug fix (missing

[Mesa-dev] [AppVeyor] mesa master #2953 completed

Build mesa 2953 completed Commit e2610bf165 by Liu Zhiquan on 12/9/2016 11:29 AM: EGL/android: Enhance pbuffer implementation\n\nSome dri drivers will pass multiple bits in buffer_mask parameter\nto droid_image_get_buffer(), more than the actual supported

[Mesa-dev] [AppVeyor] mesa fdo_master #2952 failed

Build mesa 2952 failed Commit e2610bf165 by Liu Zhiquan on 12/9/2016 11:29 AM: EGL/android: Enhance pbuffer implementation\n\nSome dri drivers will pass multiple bits in buffer_mask parameter\nto droid_image_get_buffer(), more than the actual supported

Re: [Mesa-dev] [PATCH 04/19] glsl: Use simpler visitor to determine which UBO and SSBO blocks are used

On Thu, 2016-12-15 at 20:10 -0800, Ian Romanick wrote: > From: Ian Romanick > > Very soon this visitor will get more complicated.  The users of the > existing ir_variable_refcount visitor won't need the coming > functionality, and this use doesn't need much of the

Re: [Mesa-dev] V7 Loop unrolling in NIR

On Dec 18, 2016 9:48 PM, "Timothy Arceri" wrote: V7: - paritally out of ssa in unrolling pass to avoid phis - lots of simplification/tidy ups in the analysis pass - if_uses bug fix (missing functionality) in lcssa fixed - better support for non trivial loop

Re: [Mesa-dev] [PATCH 03/19] glsl: Track the linearized array index for each UBO instance array element

On Thu, 2016-12-15 at 20:10 -0800, Ian Romanick wrote: > From: Ian Romanick > > Signed-off-by: Ian Romanick > Cc: mesa-sta...@lists.freedesktop.org > --- >  src/compiler/glsl/link_uniform_blocks.cpp | 17 ++--- >  

[Mesa-dev] [PATCH 09/12] nir: add a loop unrolling pass

V2: - tidy ups suggested by Connor. - tidy up cloning logic and handle copy propagation based of suggestion by Connor. - use nir_ssa_def_rewrite_uses to fix up lcssa phis suggested by Connor. - add support for complex loop unrolling (two terminators) - handle case were the ssa defs use outside

[Mesa-dev] [PATCH 06/12] nir: create helper for fixing phi srcs when cloning

This will be useful for fixing phi srcs when cloning a loop body during loop unrolling. Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir_clone.c | 36 +--- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git

[Mesa-dev] [PATCH 11/12] i965: use nir loop unrolling pass

shader-db results for BDW: total instructions in shared programs: 12589614 -> 12590119 (0.00%) instructions in affected programs: 50525 -> 51030 (1.00%) helped: 7 HURT: 145 total cycles in shared programs: 241524604 -> 241490502 (-0.01%) cycles in affected programs: 1941404 -> 1907302 (-1.76%)

[Mesa-dev] [PATCH 02/12] i965: use nir_lower_indirect_derefs() for GLSL

This moves the nir_lower_indirect_derefs() call into brw_preprocess_nir() so thats is called by both OpenGL and Vulkan and removes that call to the old GLSL IR pass lower_variable_index_to_cond_assign() We want to do this pass in nir to be able to move loop unrolling to nir. There is a increase

[Mesa-dev] [PATCH 12/12] i965: disable loop unrolling in GLSL IR

There is a single regression in loop unrolling which is: loops HURT: shaders/orbital_explorer.shader_test GS SIMD8:0 -> 1 However the loop is huge so it seems reasonable not to unroll it. It's surprising that GLSL IR does unroll it. shader-db results BDW: total instructions in shared

[Mesa-dev] [PATCH 10/12] nir: pass compiler rather than devinfo to functions that call nir_optimize

Later we will pass compiler to nir_optimise to be used by the loop unroll pass. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 -- src/mesa/drivers/dri/i965/brw_nir.c | 7 --- src/mesa/drivers/dri/i965/brw_nir.h | 4 ++--

[Mesa-dev] [PATCH 08/12] nir: add helper for cloning nir_cf_list

V2: - updated to create a generic list clone helper nir_cf_list_clone() - continue to assert on clone when fallback flag not set as suggested by Jason. Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir_clone.c| 62 +++--

[Mesa-dev] [PATCH 04/12] nir: Add a LCSAA-pass

From: Thomas Helland V2: Do a "depth first search" to convert to LCSSA V3: Small comment fixup V4: Rebase, adapt to removal of function overloads V5: Rebase, adapt to relocation of nir to compiler/nir Still need to adapt to potential if-uses Work around

[Mesa-dev] [PATCH 05/12] nir: don't count removal of lcssa_phi as progress

V2: - make the is_lcssa_phi bool const, suggested by Topi. --- src/compiler/nir/nir_opt_remove_phis.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_opt_remove_phis.c b/src/compiler/nir/nir_opt_remove_phis.c index acaa6e1..99d5d35 100644 ---

[Mesa-dev] [PATCH 07/12] nir: update fixup_phi_srcs() to handle registers

We need to do this because we partially get out of SSA when unrolling and cloning loops. --- src/compiler/nir/nir_clone.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c index fb1558c..91ffe62 100644 ---

[Mesa-dev] [PATCH 03/12] nir: Add a loop analysis pass

From: Thomas Helland This pass detects induction variables and calculates the trip count of loops to be used for loop unrolling. I've removed support for float induction values for now, for the simple reason that they don't appear in my shader-db collection, and so I

[Mesa-dev] [PATCH 01/12] i965: allow sampler indirects on all gens

Without this we will regress the max-samplers piglit test on Gen6 and lower when loop unrolling is done in NIR. There is a check in the GLSL IR linker that errors when it finds indirects and EmitNoIndirectSampler is set. As far as I can tell there is no reason for not enabling this for all gens

[Mesa-dev] V7 Loop unrolling in NIR

V7: - paritally out of ssa in unrolling pass to avoid phis - lots of simplification/tidy ups in the analysis pass - if_uses bug fix (missing functionality) in lcssa fixed - better support for non trivial loop terminators - fixed all loop HURT except 1 that is too big to unroll. total

Re: [Mesa-dev] [PATCH] Mesa: Fix error code for glTexImage3D in GLES

Hi, Chad & Ian I check the code again, we cannot easily move texture_format_error_check_gles ahead of _mesa_error_check_format_and_type, as the texture_format_error_check_gles is based on _mesa_error_check_format_and_type to handles some additional restrictions from GLES API. I am afraid

Re: [Mesa-dev] [PATCH 02/19] glsl: Fix wonkey indentation left from previous commit

Patches 1-2: Reviewed-by: Timothy Arceri ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] Mesa: Fix error code for glTexImage3D in GLES

Hi, Chad & Ian Thanks for your suggestion, and I understand and agree your point, while the texsubimage_error_check (in teximage.c) calls _mesa_error_check_format_and_type first, and if error happens, it will return immediately (in 2175) and not call texture_format_error_check_gles (in 2184).

Re: [Mesa-dev] [PATCH] Mesa: Return GL error INVALID_OPERATION in case invalid format/type

Thanks, Ian Yes, it's my local gitconfig issue, and it's gone after I add quotes around the name and re-commit the patch. Thanks, Randy -Original Message- From: Ian Romanick [mailto:i...@freedesktop.org] Sent: Saturday, December 17, 2016 6:07 AM To: Xu, Randy Cc:

Re: [Mesa-dev] [PATCH] radv: fix dual source blending

Reviewed-by: Bas Nieuwenhuizen Does dual source blending work now with this patch? And do you need me to commit it? - Bas On Fri, Dec 16, 2016 at 2:25 AM, Fredrik Höglund wrote: > Add the index to the location when assigning driver locations for >

[Mesa-dev] [PATCH] radv: Use correct workgroup size limits.

Not sure where the 16k comes from, but pretty sure 2k is the max. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

[Mesa-dev] [PATCH 16/23] radv: Implement cache flushing for the MEC.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/si_cmd_buffer.c | 36 +--- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 5ac2a14809..4b2624cb8e 100644 ---

[Mesa-dev] [PATCH 17/23] radv: update vkCmdUpdateBuffer for the MEC.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_buffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index 42297b9ce9..cd2973fa4a 100644 ---

[Mesa-dev] [PATCH 15/23] radv: add semaphore support

From: Dave Airlie Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 29 - src/amd/vulkan/radv_radeon_winsys.h | 9 ++ src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 45

[Mesa-dev] [PATCH 12/23] radv/winsys: Make WaitIdle queue aware.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 10 +-- src/amd/vulkan/radv_radeon_winsys.h | 3 +- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 34 +--

[Mesa-dev] [PATCH 11/23] radv/meta: update header info

From: Dave Airlie Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_bufimage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index

[Mesa-dev] [PATCH 23/23] radv: expose the compute queue

From: Dave Airlie v2: Don't expose the SDMA queue and use the CIK check also in the second if. (Bas) Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 52 ++-- 1 file changed, 41

[Mesa-dev] [PATCH 19/23] radv: Use RELEASE_MEM packet for MEC timestamp query.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/common/sid.h| 1 + src/amd/vulkan/radv_query.c | 29 - 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index 3b3983fe27..0a2c616e64

[Mesa-dev] [PATCH 13/23] radv: init compute queue and avoid initing transfer queues

From: Dave Airlie Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 41 src/amd/vulkan/radv_private.h| 2 ++ src/amd/vulkan/si_cmd_buffer.c | 7 --- 3 files changed, 35

[Mesa-dev] [PATCH 02/23] radv/winsys: start adding support for DMA/compute queue

From: Dave Airlie Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c

[Mesa-dev] [PATCH 21/23] radv: Create an empty CS per ring type.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 27 --- src/amd/vulkan/radv_private.h | 2 +- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

[Mesa-dev] [PATCH 14/23] radv: pass queue index into winsys submission

From: Dave Airlie This is so we can submit on separate queues if needed Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 4 ++-- src/amd/vulkan/radv_radeon_winsys.h | 1 +

[Mesa-dev] [PATCH 18/23] radv: Implement indirect dispatch for the MEC.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 26 +- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7d7f55a145..3c5fe25ce6 100644 ---

[Mesa-dev] [PATCH 09/23] radv: clear image implementation for compute queue

From: Dave Airlie Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta.h | 7 + src/amd/vulkan/radv_meta_bufimage.c | 269 ++-- src/amd/vulkan/radv_private.h | 5 + 3 files changed, 272

[Mesa-dev] [PATCH 03/23] radv: start fixing up queue allocate for multiple queues

From: Dave Airlie v2: Fix error handling and zero init the device (Bas) Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 52 ++- src/amd/vulkan/radv_private.h | 16 + 2 files

[Mesa-dev] [PATCH 22/23] radv: Only emit PFP ME syncs for DMA on the GFX queue.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/si_cmd_buffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 4b2624cb8e..e3f883f50b 100644 --- a/src/amd/vulkan/si_cmd_buffer.c

[Mesa-dev] [PATCH 20/23] radv: Don't enable CMASK on compute queues.

We can't fast clear on compute queues. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 40 src/amd/vulkan/radv_image.c | 18 -- src/amd/vulkan/radv_meta_clear.c | 2 +-

[Mesa-dev] [PATCH 07/23] radv: implement image->image copies using compute shader

From: Dave Airlie This is required for having a separate compute queue, we probably can't use this on GFX queue due to DCC. v2: Set coord_components = 2 for itoi texture fetch. (Bas) Signed-off-by: Dave Airlie Reviewed-by: Bas Nieuwenhuizen

[Mesa-dev] [PATCH 10/23] radv: hook compute clears into clear image api.

From: Dave Airlie These aren't used yet but we will want to use them when we implement a separate compute queue. Signed-off-by: Dave Airlie Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_clear.c | 41

[Mesa-dev] [PATCH 04/23] radv: Store queue family in command buffers.

From: Dave Airlie v2: Added helper (Bas) Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 30 -- src/amd/vulkan/radv_private.h| 7 +++ 2 files changed, 35 insertions(+), 2 deletions(-)

[Mesa-dev] [PATCH 05/23] radv: Use correct pitch for views with different block size.

Needed when accessing a comrpessed texture as R32G32B32A32 from a shader. This was not encountered previously, as we used the CB for the reinterpretation, which does not use this pitch. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_image.c | 5 - 1 file

[Mesa-dev] [PATCH 00/23] Compute queues for radv

Hi Dave, I finally got the compute queues working for me, tested with CTS, Talos and dota2. The most significant functional changes, besides just implementing different command formats for the MEC are: - Fixing a pitch bug that caused VM faults when storing a compressed texture as RGBA32.

[Mesa-dev] [PATCH 08/23] radv/meta: split clear image out into a separate layer clear function

From: Dave Airlie This will make it easier to add support for clears on compute queues. Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_clear.c | 245 --- 1 file changed, 128 insertions(+), 117

[Mesa-dev] [PATCH 06/23] radv: add a compute shader implementation for buffer to image

From: Dave Airlie This implements the reverse of the current buffer->image path and can be used when we need to do image transfer on compute queues This just adds the code turned off as we don't support separate computes queues yet, and we don't want to use this path on the

[Mesa-dev] [PATCH 01/23] radv/winsys: Expose number of compute/dma rings.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_radeon_winsys.h | 3 ++- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 14 +- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_radeon_winsys.h

[Mesa-dev] [PATCH] st/nine: Upload on secondary context for Draw*Up

Avoid synchronization by using the secondary context for uploading the vertex data for Draw*Up. Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/device9.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On 18/12/2016 18:34, Nicolai Hähnle wrote: Then again, why not just call flush unconditionally? If the flush was unnecessary, it should be a no-op, and the driver should already have a fast path for that anyway. I just looked at radeon source with amdgpu, and it looks like to me a flush

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On Sun, Dec 18, 2016 at 12:43 PM, Nicolai Hähnle wrote: > On 18.12.2016 17:40, Axel Davy wrote: >> >> On 18/12/2016 16:57, Nicolai Hähnle wrote: >>> >>> >>> >>> I'm happy to be convinced otherwise if I missed something, but using >>> multiple contexts from different threads,

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On 18/12/2016 18:34, Nicolai Hähnle wrote: On 18.12.2016 17:37, Axel Davy wrote: On 18/12/2016 16:57, Nicolai Hähnle wrote: On 18.12.2016 13:38, Axel Davy wrote: Currently there is no real specification on what is allowed for using different contexts in several threads, or when you map/unmap

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On 18.12.2016 17:40, Axel Davy wrote: On 18/12/2016 16:57, Nicolai Hähnle wrote: I'm happy to be convinced otherwise if I missed something, but using multiple contexts from different threads, or using Map/UnmapBuffer from one context but sourcing the buffer from draw calls in another context

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On 18.12.2016 17:37, Axel Davy wrote: On 18/12/2016 16:57, Nicolai Hähnle wrote: On 18.12.2016 13:38, Axel Davy wrote: Currently there is no real specification on what is allowed for using different contexts in several threads, or when you map/unmap a resource in a thread, but uses it in

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On 18/12/2016 16:57, Nicolai Hähnle wrote: I'm happy to be convinced otherwise if I missed something, but using multiple contexts from different threads, or using Map/UnmapBuffer from one context but sourcing the buffer from draw calls in another context are all perfectly supported OpenGL

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On 18/12/2016 16:57, Nicolai Hähnle wrote: On 18.12.2016 13:38, Axel Davy wrote: Currently there is no real specification on what is allowed for using different contexts in several threads, or when you map/unmap a resource in a thread, but uses it in another for draw calls. For the gallium

Re: [Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

On 18.12.2016 13:38, Axel Davy wrote: Currently there is no real specification on what is allowed for using different contexts in several threads, or when you map/unmap a resource in a thread, but uses it in another for draw calls. For the gallium nine CSMT patchset, I've figured out it would

[Mesa-dev] [PATCH 3/3 v2] gallium: add flag for transfers in a different context than draw calls

Add cap PIPE_CAP_BUFFER_TRANSFER_EXTERNAL_CONTEXT. See commit for detailed description of the flag. v2: Explicit flush behaviour. Signed-off-by: Axel Davy --- src/gallium/docs/source/screen.rst | 11 +++ src/gallium/drivers/freedreno/freedreno_screen.c

[Mesa-dev] [RFC] New gallium flags for using different contexts in several threads

Currently there is no real specification on what is allowed for using different contexts in several threads, or when you map/unmap a resource in a thread, but uses it in another for draw calls. For the gallium nine CSMT patchset, I've figured out it would be better to add flags to describe what

[Mesa-dev] [PATCH 2/3] radeon: enable PIPE_CAP_THREAD_SAFE

r600 and radeonsi are thread safe. Signed-off-by: Axel Davy --- src/gallium/drivers/r600/r600_pipe.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_pipe.c

[Mesa-dev] [PATCH 3/3] gallium: add flag for transfers in a different context than draw calls

Add cap PIPE_CAP_BUFFER_TRANSFER_EXTERNAL_CONTEXT. See commit for detailed description of the flag. Signed-off-by: Axel Davy --- src/gallium/docs/source/screen.rst | 9 + src/gallium/drivers/freedreno/freedreno_screen.c | 1 +

[Mesa-dev] [PATCH 1/3] gallium: add PIPE_CAP_THREAD_SAFE

Add flag indicating if the driver is thread safe or not. See commit for documentation on the meaning of the flag. Signed-off-by: Axel Davy --- src/gallium/docs/source/screen.rst | 3 +++ src/gallium/drivers/freedreno/freedreno_screen.c | 1 +

[Mesa-dev] [PATCH 84/84 v6] st/nine: Implement new buffer upload path

This new buffer upload path enables to lock faster than the normal path when using DISCARD/NOOVERWRITE. v2: Diverse cleanups and fixes. v3: Fix allocation size for 'lone' buffers and add more debug info. v4: Rewrite of the path to handle when DISCARD/NOOVERWRITE is not used anymore. The resource

[Mesa-dev] [PATCH 84/84 v5] st/nine: Implement new buffer upload path

This new buffer upload path enables to lock faster than the normal path when using DISCARD/NOOVERWRITE. v2: Diverse cleanups and fixes. v3: Fix allocation size for 'lone' buffers and add more debug info. v4: Rewrite of the path to handle when DISCARD/NOOVERWRITE is not used anymore. The resource

[Mesa-dev] [PATCH 57/84 v2] st/nine: Implement Fast path for dynamic buffers and csmt

Use the secondary pipe for DISCARD/NOOVERWRITE, which avoids stalling to get the pipe from the worker thread. v2: flush at unmap. This is required for example if the driver does hidden draw calls or copies. In the case of unsynchronized it is probably not required, but it is more safe.

[Mesa-dev] [PATCH] st/nine: Call GetPipe for implicit pipe usages

With csmt, every usage of the pipe in the main thread has to be protected by calling GetPipe. Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/device9.c| 6 ++ src/gallium/state_trackers/nine/swapchain9.c | 2 ++ 2 files changed, 8 insertions(+) diff --git