On Mon, 2017-01-09 at 16:18 -0800, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > From: Iago Toral Quiroga
> >
> > It seems to use 1 channel por DF, just like later hardware. The
> > docs say things
> > like:
> >
> > "Each DF operand uses a pair of channels and all masking a
Yeah, the set reg was clearly for all the regs at once.
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jan 10, 2017 at 5:50 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This set context req seq was in the wrong place.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/si_cmd_buffer.c | 4 ++--
>
Signed-off-by: Kenneth Graunke
---
src/intel/vulkan/anv_device.c | 2 +-
src/intel/vulkan/anv_pipeline.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index bd33f105fa6..f58d1ac24b5 100644
--- a/src/intel/vulka
When there are no framebuffer attachments, fb->width and fb->height will
be 0. Subtracting 1 results in 4294967295 which is too large for the
field, causing genxml assertions when trying to create the packet.
In this case, we can just program it to 1.
Caught by dEQP-VK.tessellation.tesscoord.tri
We need to:
- handle the extra array level for per-vertex varyings
- handle the patch qualifier correctly
- assign varying locations
Signed-off-by: Kenneth Graunke
Reviewed-by: Dave Airlie
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Jason Ekstrand
---
src/compiler/spirv/spirv_to_nir.c | 1
Signed-off-by: Kenneth Graunke
---
src/intel/vulkan/anv_device.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 219c6114083..bd33f105fa6 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/i
Signed-off-by: Kenneth Graunke
---
src/intel/vulkan/anv_private.h | 2 +
src/intel/vulkan/genX_pipeline.c | 89
src/intel/vulkan/genX_state.c| 4 --
3 files changed, 91 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_private.h b/sr
Signed-off-by: Kenneth Graunke
Reviewed-by: Iago Toral Quiroga
---
src/intel/vulkan/anv_pipeline.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 2c46ef5bf96..0dc7019efb1 100644
--- a/src/intel/
...when the capability bit is set.
Signed-off-by: Kenneth Graunke
Reviewed-by: Iago Toral Quiroga [v1]
---
src/compiler/spirv/nir_spirv.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 7 +--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/nir_spirv.h b/src/
Signed-off-by: Kenneth Graunke
---
src/intel/vulkan/genX_pipeline.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 5d63a394cc1..3f3eab5fe19 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_p
Iago suggested tidying this.
Signed-off-by: Kenneth Graunke
---
src/compiler/spirv/vtn_variables.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compiler/spirv/vtn_variables.c
index 4a6f9788af0..e564fb03cbe 100644
In Vulkan, we always have both the TCS and TES available in the same
pipeline, so we can simply use the TCS OutputVertices execution mode
value as the TES PatchVertices built-in.
For GLSL, we handle this in the linker. But we could use this pass
in the case when both TCS and TES are linked togeth
v2: Use info->tess.
Signed-off-by: Kenneth Graunke
Reviewed-by: Dave Airlie [v1]
Reviewed-by: Iago Toral Quiroga [v1]
Reviewed-by: Jason Ekstrand [v1]
---
src/compiler/spirv/spirv_to_nir.c | 45 +--
1 file changed, 39 insertions(+), 6 deletions(-)
diff --g
v2: Merge more TCS/TES info.
Signed-off-by: Kenneth Graunke
---
src/intel/vulkan/anv_pipeline.c | 189 +++-
1 file changed, 187 insertions(+), 2 deletions(-)
Jason and I figured out caching. It turns out I had a one line bug.
diff --git a/src/intel/vulkan/a
Annoyingly, SPIR-V lets you specify all of these fields in either the
TCS or TES, which means that we need to be able to store all of them
for either shader stage. Putting them in a union won't work.
Combining both is an easy solution, and given that the TCS struct only
had a single field, it's p
"Function Enable" is what the other stages use.
---
src/intel/genxml/gen7.xml | 2 +-
src/intel/genxml/gen75.xml | 2 +-
src/intel/genxml/gen8.xml | 2 +-
src/intel/genxml/gen9.xml | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxm
On 17-01-09 11:56:04, Jason Ekstrand wrote:
On Thu, Dec 1, 2016 at 2:09 PM, Ben Widawsky
wrote:
From: Ben Widawsky
This will be used by clients that need to know the number of planes
allocated for them on behalf of the GL or other API. The best current
example of this is when an extra "plane
https://bugs.freedesktop.org/show_bug.cgi?id=97879
--- Comment #49 from i...@posteo.net ---
(In reply to Jani Kärkkäinen from comment #48)
> Using AMDGPU-PRO the hangs are non-existent. So there must be SOMETHING in
> the whole mesa-driver stack, that causes the hangs, if not the GL drivers
> them
From: Dave Airlie
This set context req seq was in the wrong place.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/si_cmd_buffer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 15e520a..19dd063 100644
On Mon, Jan 9, 2017 at 6:57 PM, Dave Airlie wrote:
> On 10 January 2017 at 02:05, Jason Ekstrand wrote:
> > Also, we should probably consider converting it over to a system value
> one
> > of these days. That would make more sense from a theoretical model
> > perspective. Not sure if it makes
This comes in very handy on a SLES11 (or similar) based install.
Reviewed-by: Bruce Cherniak
> On Jan 6, 2017, at 7:27 AM, Chuck Atkins wrote:
>
> Cc: mesa-sta...@lists.freedesktop.org
> Cc: Bruce Cherniak
> Signed-of-by: Chuck Atkins
> ---
> configure.ac|
https://bugs.freedesktop.org/show_bug.cgi?id=98974
--- Comment #7 from Ernst Sjöstrand ---
Can't reproduce with Fiji, drm-next-4.10 and mesa
13.0-branchpoint-2089-g230b756
Running with multisample 4x, high, high.
Stellaris is now v1.4.1.
--
You are receiving this mail because:
You are the ass
On 10 January 2017 at 02:05, Jason Ekstrand wrote:
> Also, we should probably consider converting it over to a system value one
> of these days. That would make more sense from a theoretical model
> perspective. Not sure if it makes sense in any drivers though.
>
> On Mon, Jan 9, 2017 at 8:03 AM
On 09/01/17 08:08 PM, Christian König wrote:
> Am 09.01.2017 um 11:58 schrieb Marek Olšák:
>> On Mon, Jan 9, 2017 at 7:25 AM, Michel Dänzer wrote:
>>> On 09/01/17 03:13 PM, Michel Dänzer wrote:
On 07/01/17 11:46 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> ~/.drirc is created b
On Mon, 2017-01-09 at 16:13 +1100, Timothy Arceri wrote:
> ---
> src/compiler/glsl/linker.cpp| 63 +++--
>
> src/mesa/drivers/dri/i965/brw_tcs.c | 6 ++--
> src/mesa/main/shaderapi.c | 15 +++--
> 3 files changed, 39 insertions(+), 45 deletio
Is this code doing the 'downsize' for gen >= 8 as well?
-Jordan
On 2017-01-09 09:10:00, Juan A. Suarez Romero wrote:
> From: Alejandro Piñeiro
>
> gen < 8 doesn't support *64*PASSTHRU formats when emitting
> vertices. So in order to provide the equivalent functionality, we need
> to downsize th
Most of the brw_disasm.c file is rewritten to disassemble into a
string, and brw_disassemble_inst uses brw_disassemble_inst_str.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +
src/mesa/drivers/dri/i965/brw_disasm.c | 646 +---
2 fil
Signed-off-by: Jordan Justen
---
src/intel/tools/aubinator.c | 23 +--
src/intel/tools/disasm.c | 7 ++-
src/intel/tools/gen_disasm.h | 2 +-
3 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
i
Notably, json doesn't allow hexidecimal numbers. :\
Signed-off-by: Jordan Justen
---
src/intel/tools/aubinator.c | 4 ++--
src/intel/tools/decoder.c | 7 +--
src/intel/tools/decoder.h | 4 +++-
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/
Signed-off-by: Jordan Justen
---
src/intel/tools/aubinator.c | 571 +---
1 file changed, 485 insertions(+), 86 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index efd7c0496e3..a234e5a2cee 100644
--- a/src/intel/tools/a
Signed-off-by: Jordan Justen
---
src/intel/tools/disasm.c | 53 +---
1 file changed, 5 insertions(+), 48 deletions(-)
diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index 4ac7b902564..af914243750 100644
--- a/src/intel/tools/disasm.c
Signed-off-by: Jordan Justen
---
src/intel/tools/decoder.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/decoder.c b/src/intel/tools/decoder.c
index defb0873da0..0e6a139ddaa 100644
--- a/src/intel/tools/decoder.c
+++ b/src/intel/tools/decoder.c
@@
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +
src/mesa/drivers/dri/i965/brw_disasm.c | 65 +
2 files changed, 67 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index
git://people.freedesktop.org/~jljusten/mesa aubinator-json
I was recently trying to compare the output from aubinator on two
different aub files. After manually examining the output for a while,
and, unfortunately, making little progress I thought it might be
useful to be able to programically ana
Reviewed-by: Jason Ekstrand
and pushed... Thanks!
On Mon, Jan 9, 2017 at 1:45 PM, Thomas Hindoe Paaboel Andersen <
pho...@gmail.com> wrote:
> The foreach loop was called both in the else case
> and right after. The indentation seems to indicate
> that the extra call was from a previous version
On Mon, Jan 2, 2017 at 6:37 PM, Ben Widawsky wrote:
> The idea behind modifiers like this is that the user of GBM will have
> some mechanism to query what properties the hardware supports for its BO
> or surface. This information is directly passed in (and stored) so that
> the DRI implementation
LOCAL_C_INCLUDES need to include correct path of libelf,
which had exceptions for Android 5.0 (i.e external/elfutils/0.153/libelf)
and Android 6.0 (i.e. external/elfutils/src/libelf)
In Android 7.0 the path is again external/elfutils/libelf
Fixes the following building error:
external/mesa/src/ga
This is similar to commit 7420c9dab4aaf87e6b840410226c296c4668a48f
but for the i915 driver, as neeeded in android-x86.
In version v2, as per i965 implementation,
the extension GL_OES_EGL_image_external is not enabled by default.
The by-the-book way to enable the extension is mesa environment vari
Conditional libLLVMCore static library dependency is added,
for the case when MESA_ENABLE_LLVM is true
Fixes the following building error with Android 7.0:
In file included from
external/mesa/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp:62:
...
external/llvm/include/llvm/IR/Attributes.h:68:14: f
Integration of rules that set correct HAVE_LLVM value for Android 7.0
---
Android.common.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Android.common.mk b/Android.common.mk
index 1745b08..36a44bb 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -80,7 +80,7 @@ endi
LLVMInitializeAMDGPU* functions need to be explicitly declared
and mesa expects them via header,
but LLVM needs to be instructed to invoke its own LLVM_TARGET(AMDGPU) macro,
or the functions will not be available.
A new llvm cflag (-DFORCE_BUILD_AMDGPU) serves this purpose,
the same mechanism is
Removed as unnecessary
---
src/gallium/targets/dri/Android.mk | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/gallium/targets/dri/Android.mk
b/src/gallium/targets/dri/Android.mk
index 1564d9d..9067b32 100644
--- a/src/gallium/targets/dri/Android.mk
+++ b/src/gallium/targets/dri/Android.m
Fixes building errors due to multiple definition of ffs and ffsll
as they are provided by bionic in kitkat,
in later versions these definitions do no harm.
---
Android.common.mk | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Android.common.mk b/Android.common.mk
index 80cf572..1745b08 10064
Fixes a series of libz related building errors:
target SharedLib: gallium_dri_32
(out/target/prod...SHARED_LIBRARIES/gallium_dri_intermediates/LINKED/gallium_dri.so)
external/elfutils/libelf/elf_compress.c:117: error: undefined reference to
'deflateInit_'
...
external/elfutils/libelf/elf_compress
LLVMInitializeAMDGPU* functions need to be explicitly declared
and mesa expects them via header,
but LLVM needs to be instructed to invoke its own LLVM_TARGET(AMDGPU) macro,
or the functions will not be available.
A new llvm cflag (-DFORCE_BUILD_AMDGPU) serves this purpose,
the same mechanism is
LLVMInitializeAMDGPU* functions need to be explicitly declared
and mesa expects them via header,
but LLVM needs to be instructed to invoke its own LLVM_TARGET(AMDGPU) macro,
or the functions will not be available.
A new llvm cflag (-DFORCE_BUILD_AMDGPU) serves this purpose,
the same mechanism is
Fixes building error due to dependency on nir generated headers
---
src/mesa/Android.libmesa_st_mesa.mk | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/Android.libmesa_st_mesa.mk
b/src/mesa/Android.libmesa_st_mesa.mk
index 3905ddc..92df4ad 100644
--- a/src/mesa/And
---
src/gallium/state_trackers/dri/dri_screen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/dri/dri_screen.c
b/src/gallium/state_trackers/dri/dri_screen.c
index aa0ad09..a950f52 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/g
Hi,
I'm sending a series of 12 patches for android,
comprising fixes for build errors, LLVMInitializeAMDGPU* declarations,
Android 7 fixes and a (small) i915 patch for feature parity with i965.
Tested with nougat-x86 and marshmallow-x86
Mauro
Changelog:
[building errors/trailing whitespaces]
Somehow I didn't actually get the original e-mail so I'm replying via
git-send-email...
On 01/02, Ben Widawsky wrote:
> Modifiers will be obtains or guessed by the client and passed in during
> image creation/import.
>
> This requires bumping the DRIimage version.
>
> As of this patch, the modif
In parse_identifier, it doesn't stop copying '*pcur' untill
encounter the NULL. As the 'ret' has a fixed-size buffer, if
the '*pcur' has a long string, there will be a buffer overflow.
This patch avoid this.
Signed-off-by: Li Qiang
---
src/gallium/auxiliary/tgsi/tgsi_text.c | 6 +++---
1 file ch
In parse_identifier, it doesn't stop copying '*pcur'
untill encounter the NULL. As the 'ret' has a fixed-size
buffer, if the '*pcur' has a long string, there will be
a buffer overflow. This patch avoid this.
Signed-off-by: Li Qiang
---
src/gallium/auxiliary/tgsi/tgsi_text.c | 9 ++---
1 file
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> It seems to use 1 channel por DF, just like later hardware. The docs say
> things
> like:
>
> "Each DF operand uses a pair of channels and all masking and swizzling
> should be adjusted appropriately."
>
> "In Align16, all regio
On Mon, Jan 9, 2017 at 3:50 PM, Jason Ekstrand wrote:
> On Mon, Jan 2, 2017 at 6:36 PM, Ben Widawsky wrote:
>
>> Signed-off-by: Ben Widawsky
>> Reviewed-by: Eric Engestrom
>> Acked-by: Daniel Stone
>> ---
>> src/gbm/backends/dri/gbm_dri.c | 26 +-
>> src/gbm/gbm-symbo
Samuel Iglesias Gonsálvez writes:
> From: "Juan A. Suarez Romero"
>
> The execution data size is the biggest type size of any instruction
> operand.
>
> We will use it to know if the instruction deals with DF, because in Ivy
> we need to duplicate the execution size and regioning parameters.
> -
On Mon, Jan 2, 2017 at 6:36 PM, Ben Widawsky wrote:
> Signed-off-by: Ben Widawsky
> Reviewed-by: Eric Engestrom
> Acked-by: Daniel Stone
> ---
> src/gbm/backends/dri/gbm_dri.c | 26 +-
> src/gbm/gbm-symbols-check | 1 +
> src/gbm/main/gbm.c | 15 +
Samuel Iglesias Gonsálvez writes:
> From: "Juan A. Suarez Romero"
>
> In IVB/VLV, for instructions dealing with DF, execsize will be
> duplicated in the final code.
>
> So take this in account when checking if instructions should be split.
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +
On Wed, Jan 4, 2017 at 8:43 PM, Ben Widawsky wrote:
> v2: Make the error return be -1 instead of 0 because I think 0 is
> actually valid.
>
> Cc: Daniel Stone
> Signed-off-by: Ben Widawsky
> ---
> src/gbm/backends/dri/gbm_dri.c | 28
> src/gbm/gbm-symbols-check
Matt Turner writes:
> On 01/05, Samuel Iglesias Gonsálvez wrote:
>>From: Iago Toral Quiroga
>>
>>4-wide DF operations where NibCtrl applies require and execsize of 8
>>in IvyBridge/Valleyview.
>
> Wow, the documentation is bad in this area. The QtrCtrl description in
> IVB's Vol4 Part3 explicitl
On Thu, Jan 05, 2017 at 11:29:39AM -0800, Kenneth Graunke wrote:
> Predication needs cmd parser only on gen7. For newer platforms, it
> should be available without it.
>
> Signed-off-by: Rafael Antognolli
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
>
Ugh, will update the patch with these changes.
Thanks!
Rafael
On Thu, Jan 05, 2017 at 11:17:51AM -0800, Kenneth Graunke wrote:
> On Tuesday, December 13, 2016 2:50:57 PM PST Rafael Antognolli wrote:
> > Enable getting the results of a transform feedback overflow query with a
> > buffer object.
>
On Thu, Jan 05, 2017 at 11:22:51AM -0800, Kenneth Graunke wrote:
> On Tuesday, December 13, 2016 2:50:58 PM PST Rafael Antognolli wrote:
> > Enable the use of a transform feedback overflow query with
> > glBeginConditionalRender. The render commands will only execute if the
> > query is true (i.e.
The foreach loop was called both in the else case
and right after. The indentation seems to indicate
that the extra call was from a previous version
with an else section with out curly brackets.
---
Spotted due to the wrong indentation. The patch is untested
as I do not have the neccesary hardware.
Am 06.01.2017 um 10:42 schrieb Samuel Pitoiset:
> D3D always computes the absolute value while GLSL says that the
That should probably say "d3d9" - it is completely wrong for d3d10 and
later (which have it to be defined as a guaranteed NaN).
(Otherwise, I'm still not quite convinced it's the right
Am 07.01.2017 um 19:11 schrieb Marek Olšák:
> On Sat, Jan 7, 2017 at 5:23 PM, Roland Scheidegger wrote:
>> Am 07.01.2017 um 15:51 schrieb Marek Olšák:
>>> From: Marek Olšák
>>>
>>> This fixes broken depth texturing after:
>>>
>>> commit 22639a6e19f95902aef23474ad672bf489231ea7
>>> Author: Timothy
Reviewed-by: Bas Nieuwenhuizen
On Fri, Dec 30, 2016 at 6:22 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This just adds the nir->llvm support, enabling
> the extension causes some failures on llvm 3.9 at least,
> but this code seems fine.
>
> NIR passes the sampler in src[1].x, and we LLVM/SI
On Thu, Dec 1, 2016 at 2:09 PM, Ben Widawsky
wrote:
> From: Ben Widawsky
>
> This will be used by clients that need to know the number of planes
> allocated for them on behalf of the GL or other API. The best current
> example of this is when an extra "plane" is allocated to store
> compression
Hi Christian,
There's a few nitpicks. Note that neither is a blocker so feel free to
send patches in the week(s) to come.
On 23 December 2016 at 22:04, Christian Gmeiner
wrote:
> --- a/configure.ac
> +++ b/configure.ac
> @@ -76,6 +76,7 @@ LIBDRM_NVVIEUX_REQUIRED=2.4.66
> LIBDRM_NOUVEAU_REQUIRE
Hi Rob,
On 22 July 2016 at 17:22, Rob Herring wrote:
> Another version of common pipe_screen reference counting. Please help
> test on AMD and Nouveau as those are the more complicated ones and I
> don't have h/w to test.
>
> Changes in v4:
> - Move fd dup() back into driver winsys create screen
On 29 July 2016 at 20:08, Marek Olšák wrote:
> On Fri, Jul 29, 2016 at 8:01 PM, Rob Herring wrote:
>> On Fri, Jul 29, 2016 at 12:51 PM, Marek Olšák wrote:
>>> The fd table and reference counting in the winsys is required by the
>>> GL-VDPAU interop.
>>>
>>> radeon_drm_winsys_create and amdgpu_wi
On 22 July 2016 at 17:22, Rob Herring wrote:
> Use the common pipe_screen ref counting and fd hashing functions. The
> mutex can be dropped as the pipe loader protects the create_screen()
> calls.
>
> Signed-off-by: Rob Herring
> Cc: "Marek Olšák"
> Cc: Ilia Mirkin
> ---
> src/gallium/drivers/
Acked-by: Marek Olšák
Marek
On Fri, Jan 6, 2017 at 10:42 AM, Samuel Pitoiset
wrote:
> D3D always computes the absolute value while GLSL says that the
> result of inversesqrt() is undefined if x <= 0 (and undefined if
> x < 0 for sqrt()). But some apps rely on this specific behaviour
> which is
Assuming it still builds on newer GCC,
Acked-by: Jason Ekstrand
On Sun, Jan 8, 2017 at 9:26 AM, Vinson Lee wrote:
> Fix this build error with GCC 4.4.7.
>
> CC nir/nir_opt_copy_prop_vars.lo
> nir/nir_opt_copy_prop_vars.c: In function ‘copy_prop_vars_block’:
> nir/nir_opt_copy_prop_vars.c
On 22 July 2016 at 19:01, Rob Herring wrote:
> On Fri, Jul 22, 2016 at 11:46 AM, Ilia Mirkin wrote:
>> On Fri, Jul 22, 2016 at 12:22 PM, Rob Herring wrote:
>>> In order to prevent multiple pipe_screens being created in the same
>>> process, lookup of the DRM FD and reference counting of the pipe
On 28 July 2016 at 13:45, Marek Olšák wrote:
> On Fri, Jul 22, 2016 at 6:22 PM, Rob Herring wrote:
>> In order to prevent multiple pipe_screens being created in the same
>> process, lookup of the DRM FD and reference counting of the pipe_screen
>> are needed. Several implementations of this exist
On Mon, Jan 9, 2017 at 10:07 AM, Kenneth Graunke
wrote:
> On Monday, January 9, 2017 8:26:34 AM PST Jason Ekstrand wrote:
> > On Sun, Jan 8, 2017 at 9:26 PM, Kenneth Graunke
> > wrote:
> >
> > > Signed-off-by: Kenneth Graunke
> > > ---
> > > src/intel/vulkan/anv_pipeline.c | 9 +++--
> > >
On Mon, Jan 9, 2017 at 12:37 PM, Marek Olšák wrote:
> On Mon, Jan 9, 2017 at 12:16 PM, Edmondo Tommasina
> wrote:
>> Could be a patch like this useful for power users?
>>
>> Load custom drirc only when specified in env variable.
>
> Yes, that sounds like a good alternative.
Patch sent to the mai
Define a new MESA_CUSTOM_DRIRC environment variable to load
a drirc custom file, instead of blindly using the hardcoded
${HOME}/.drirc file created the driconf tool.
Some more discussion about the driconf issues can be found
in reading following mesa-dev thread:
https://lists.freedesktop.org/archi
On Monday, January 9, 2017 8:26:34 AM PST Jason Ekstrand wrote:
> On Sun, Jan 8, 2017 at 9:26 PM, Kenneth Graunke
> wrote:
>
> > Signed-off-by: Kenneth Graunke
> > ---
> > src/intel/vulkan/anv_pipeline.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/src
GL_ARB_vertex_attrib_64bit was the last piece missing.
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i
Those not supporting 64 bit input vertex attributes will have the
dual_slot value as false.
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Juan A. Suarez Romero
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dr
From: Alejandro Piñeiro
---
src/mesa/drivers/dri/i965/intel_extensions.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 915797a..ac877cc 100644
--- a/src/mesa/drivers/dri/i9
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Juan A. Suarez Romero
---
src/mesa/drivers/dri/i965/intel_extensions.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/d
From: Alejandro Piñeiro
Doubles needs more that one slot per attribute. So when filling the
attribute_map we check if it is a double in order to allocate one
extra register.
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Juan A. Suarez Romero
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 +
From: Alejandro Piñeiro
Doubles need extra space, so we would need to do a remapping for vec4
too in order to take that into account. We reuse the already
existing remap_vs_attrs, but passing is_scalar, so they could
remap accordingly.
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Juan A. Sua
For dvec3 and dvec4 types, a single GRF do not have enough space to
allocate two inputs from two different vertices (SIMD4x2).
So the GRF only contains first two components for the two vertices, and
the next GRF has the remaining components.
We want to put all the components for the same vertex i
From: Alejandro Piñeiro
Although gen7 doesn't include surface types as a valid conversion format,
we return it, as it reflects what we want to achieve, even if we need
to workaround it on gen < 8.
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ++--
1 file changed, 6 insertions(+), 2 de
From: Alejandro Piñeiro
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 5ddbe58..f80162d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b
From: Alejandro Piñeiro
gen < 8 doesn't support *64*PASSTHRU formats when emitting
vertices. So in order to provide the equivalent functionality, we need
to downsize the format to equivalent *32*FLOAT, and in some cases
(R64G64B64 and R64G64B64A64) submit two 3DSTATE_VERTEX_ELEMENTS for
each vert
Hi,
This series implements the support for Haswell 64bit vertex attributes. With it,
we can enable OpenGL 4.2 in Haswell.
This work covers partially https://bugs.freedesktop.org/show_bug.cgi?id=94442.
These patches are available in our repository for testing. You can clone it
using the following
woohoo
Reviewed-by: Jason Ekstrand
On Mon, Jan 9, 2017 at 2:38 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> docs/relnotes/13.1.0.html | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/docs/relnotes/13.1.0.html b/docs/re
On Sun, Jan 8, 2017 at 9:26 PM, Kenneth Graunke
wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/compiler/spirv/spirv_to_nir.c | 28 ++--
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> One totally bogus thing here: we set CCW backwards. In all three driver
>
On Mon, Jan 9, 2017 at 6:34 AM, Boyan Ding wrote:
> 2016-11-23 21:20 GMT+08:00 Boyan Ding :
>> 2016-11-07 20:27 GMT+08:00 Boyan Ding :
>>> 2016-11-05 3:23 GMT+08:00 Matt Turner :
On Sun, Oct 30, 2016 at 11:45 PM, Boyan Ding
wrote:
> According to OpenGL Shading Language 4.50 spec, S
On Sun, Jan 8, 2017 at 9:26 PM, Kenneth Graunke
wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/intel/vulkan/anv_pipeline.c | 156 ++
> +-
> 1 file changed, 154 insertions(+), 2 deletions(-)
>
> There's one majorly bogus thing here: caching is totally dis
On Mon, Jan 9, 2017 at 8:40 AM, Jason Ekstrand wrote:
> For similar compute-related things (workgroup sizes) we handle this
> directly in nir_lower_system_values.
>
Doing so would probably require adding a vertices_in thing to tes... I
don't know how strongly I feel about doing it one way vs. an
For similar compute-related things (workgroup sizes) we handle this
directly in nir_lower_system_values.
On Sun, Jan 8, 2017 at 9:39 PM, Dave Airlie wrote:
> On 9 January 2017 at 15:26, Kenneth Graunke wrote:
> > In Vulkan, we always have both the TCS and TES available in the same
> > pipeline,
On Sun, Jan 8, 2017 at 9:26 PM, Kenneth Graunke
wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/intel/vulkan/anv_private.h | 2 +
> src/intel/vulkan/genX_pipeline.c | 87 ++
> ++
> src/intel/vulkan/genX_state.c| 4 --
> 3 files changed, 89 inserti
On Sun, Jan 8, 2017 at 9:26 PM, Kenneth Graunke
wrote:
> Signed-off-by: Kenneth Graunke
> ---
> src/intel/vulkan/anv_pipeline.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_
> pipeline.c
> index 17491e34
On Sun, Jan 8, 2017 at 9:38 PM, Dave Airlie wrote:
> On 9 January 2017 at 15:26, Kenneth Graunke wrote:
> > This is all implemented now.
>
> Do we want to key these off the nir_spirv_supported_extensions thing I
> added?
>
I think we do unless Dave thinks he can get tess support landed for radv
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