This commit, out of necessity, makes a number of changes at once:
1) Changes intel_mipmap_tree to store the clear color for both color
and depth as an isl_color_value.
2) Changes the depth/stencil emit code to do the format conversion of
the depth clear value on Haswell and earlier inst
---
src/intel/blorp/blorp_genX_exec.h| 2 +-
src/intel/isl/isl_emit_depth_stencil.c | 19
src/mesa/drivers/dri/i965/brw_blorp.c| 18 +++-
src/mesa/drivers/dri/i965/brw_clear.c| 15 ++-
src/mesa/drivers/dri/i965/brw_meta_util.c
https://bugs.freedesktop.org/show_bug.cgi?id=99116
--- Comment #11 from jr ---
(In reply to Boyan Ding from comment #9)
> JFYI, https://patchwork.freedesktop.org/patch/134178/ is the most recent
> version, but somehow got stuck in review.
Thanks, testing that version I can confirm that it also f
On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote:
> The main change is that we now use round*() instead of IROUND*() which only
> worked for signed integer cases. I have also made it so we write
> converted unsigned values the unsigned field in the destination union and to
> cast the resu
On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote:
> These were correct since they were used only in conversions to signed
> integers,
> however this makes the implementation a bit more is more consistent and
> reduces
> chances of propagating use of these macros to unsigned cases in the
On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote:
> As we do for all other cases of float/double conversions to integers.
>
> v2: use round() instead of IROUND() macros
> ---
> src/mesa/main/uniform_query.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/me
On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote:
> v2:
> - need unsigned rounding for double->uint64 conversion (Nicolai)
> - use round() instead of IROUND() macros
> ---
> src/mesa/main/uniform_query.cpp | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/src/m
On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote:
> Like we do for the 32-bit case.
>
> v2:
> - need unsigned rounding for float->uint64 conversion (Nicolai)
> - use roundf() instead of IROUND() macros
> ---
> src/mesa/main/uniform_query.cpp | 46
> ++
On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote:
> From: Kenneth Graunke
>
> Section 2.2.2 (Data Conversions For State Query Commands) of the
> OpenGL 4.5 October 24th 2016 specification says:
>
> "If a command returning unsigned integer data is called, such as
> GetSamplerParameterIui
On Sat, May 20, 2017 at 10:46:00PM +0200, Kai Wasserbäch wrote:
> Hey,
> John Brooks wrote on 15.05.2017 07:47:
> > This fixes the long-standing problem with Dying Light where the game would
> > produce a black screen when running under Mesa. This happened because the
> > game's vertex shaders rede
Hey,
John Brooks wrote on 15.05.2017 07:47:
> This fixes the long-standing problem with Dying Light where the game would
> produce a black screen when running under Mesa. This happened because the
> game's vertex shaders redeclare gl_VertexID, which is a GLSL builtin.
> Mesa's GLSL compiler is a li
On Sat, May 20, 2017 at 10:29:53PM +0300, Topi Pohjolainen wrote:
> In case of gen < 6 stencil (if present) is always combined with
> depth. Both stencil and depth attachments point to the same
> physical surface.
> Alignment workaround starts by considering depth and updates
> stencil accordingly.
There is no separate stencil on gen < 6.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
i
In case of gen < 6 stencil (if present) is always combined with
depth. Both stencil and depth attachments point to the same
physical surface.
Alignment workaround starts by considering depth and updates
stencil accordingly. Current logic continues with stencil and
in vain considers the case where d
Effectively there is the same code twice, once for depth and
again for stencil.
Only the current version fails to set depthstencil.depth_offset
when there is only stencil attachment (it does set the intra
tile offsets though). Hence this fixes piglits:
g45,g965,ilk: depthstencil-render-miplevel
CC: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 85050ce..fe021b0 100644
--- a/src/mesa/driv
First this series removes logic considering separate stencil
gen < 6 only code paths (where we always use combined
depth-stencil).
Then patch 5 simplifies the workaround we need for aligning
depth buffer. On gen < 6 there is no support for telling which
mip-level to draw and hence the driver need
In brw_workaround_depthstencil_alignment() corresponding
renderbuffers are always set to refer to the same temp miptrees.
There is no need to carry them in context.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h| 3 ---
src/mesa/drivers/dri/i965/brw_misc_state.c
Separate stencil and hiz are only enabled for gen6+.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h| 6 +-
src/mesa/drivers/dri/i965/brw_misc_state.c | 119 +++--
2 files changed, 13 insertions(+), 112 deletions(-)
diff --git a/src/mesa
On 19.05.2017 18:52, Samuel Pitoiset wrote:
Hi,
This series implements ARB_bindless_texture for RadeonSI.
Reminder: the GLSL compiler part is already upstream.
This series has been mainly tested with Feral games, here's the list of
existing games that use ARB_bindless_texture (though not by de
Hi Philipp,
On 19 May 2017 at 23:07, Philipp Zabel wrote:
> Before the swapchain event queue is destroyed, all proxy objects that
> reference
> it must be dropped. Otherwise we risk a use-after-free if a frame callback
> event
> or buffer release events are received afterwards.
> This happens w
Fixes building errors in radeon drivers and winsys:
target C: libmesa_amd_common <= external/mesa/src/amd/common/ac_gpu_info.c
...
target C: libmesa_amd_common <= external/mesa/src/amd/common/ac_surface.c
...
target C: libmesa_pipe_r300 <=
external/mesa/src/gallium/drivers/r300/r300_blit.c
...
On 05/20/2017 07:05 AM, Timothy Arceri wrote:
Potentially more efficient as is may avoid the struct being initialised
twice.
---
src/compiler/glsl/ir.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/compiler/glsl/ir.cpp b/src/compiler/glsl/ir.cpp
index 123de99..e
On May 20, 2017 12:24:53 AM Kenneth Graunke wrote:
This will let us initialize the constant buffers with loops.
---
src/intel/genxml/gen7.xml | 14 ++
src/intel/genxml/gen75.xml| 14 ++
src/intel/genxml/gen8.xml
Fixes linking error in libOSmesa when using libunwind.
Signed-off-by: Alexandre Demers
---
src/gallium/targets/osmesa/Makefile.am | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/targets/osmesa/Makefile.am
b/src/gallium/targets/osmesa/Makefile.am
index 6d340f1d9
https://bugs.freedesktop.org/show_bug.cgi?id=99467
Pavel Bordukov changed:
What|Removed |Added
CC||pa5h...@inbox.ru
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https://bugs.freedesktop.org/show_bug.cgi?id=99467
--- Comment #23 from Pavel Bordukov ---
Does this branch work still? I've tried to use it and got green screen.
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On 20/05/17 19:21, Timothy Arceri wrote:
On 26/10/16 02:53, Daniel Vetter wrote:
On Wed, Oct 19, 2016 at 03:34:12PM -0700, Ian Romanick wrote:
On 10/19/2016 12:58 PM, Matt Turner wrote:
On Wed, Oct 19, 2016 at 12:06 PM, Jan Ziak
<0xe2.0x9a.0...@gmail.com> wrote:
This patch removes locks aro
On 26/10/16 02:53, Daniel Vetter wrote:
On Wed, Oct 19, 2016 at 03:34:12PM -0700, Ian Romanick wrote:
On 10/19/2016 12:58 PM, Matt Turner wrote:
On Wed, Oct 19, 2016 at 12:06 PM, Jan Ziak <0xe2.0x9a.0...@gmail.com> wrote:
This patch removes locks around reference counts in favor of atomic in
If you have something like:
We would reset ctx->group_count to 0 after processing the first field,
so the second would not have a group count.
This is largely untested, as the only groups with multiple fields are
packets we don't emit in Mesa. Found by inspection.
---
s
Previously we'd print things like:
0xfffbb568: 0x0001 : Dword 1
ReadLength: 0
ReadLength: 1
0xfffbb568: 0x0001 : Dword 1
ReadLength: 1
ReadLength: 0
instead of the more obvious:
0xfffbb568: 0x0001 : Dword 1
ReadLength[0]: 0
ReadLe
This will let us initialize the constant buffers with loops.
---
src/intel/genxml/gen7.xml | 14 ++
src/intel/genxml/gen75.xml| 14 ++
src/intel/genxml/gen8.xml | 14 ++
src/intel/genxml/gen9.xml
If you had a group as the first element of a struct, i.e.
...
we would get a group_offset of 0, causing create_field() to think the
field wasn't in a group, and fail to offset forward for successive array
elements. So we'd mark all the array elements as offset 0.
Usin
For example,
used to generate:
const uint64_t v2_address =
__gen_combine_address(data, &dw[2], values->Pointer, 0);
...
const uint64_t v4_address =
__gen_combine_address(data, &dw[4], values->Pointer, 0);
...
but now generates code with proper subscripts
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