On Tue, Jun 13, 2017 at 2:17 AM, Roland Scheidegger wrote:
> I am actually also thinking this should be different.
>
> e.g. imho MAD means the operation can be either fused or unfused.
> This is the "traditional" definition of MAD - opencl for instance will
> follow this too, albeit this isn't men
Reviewed-by: Timothy Arceri
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_sampler.c
b/src/mesa/state_tracker/st_atom_
Should we add some asserts here to catch invalid values passed to these
functions?
Either way:
Reviewed-by: Timothy Arceri
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 79 +---
1 file changed, 31 inser
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
AMD SI-VI use this. GFX9 doesn't. We can stop doing this for SI-VI since
border color swizzling is broken there anyway. The only other user of this
code is nouveau.
Maybe move this comment into the code as a TODO? I was a little confus
On 06/12/2017 04:30 PM, Eric Engestrom wrote:
On Monday, 2017-06-12 09:39:15 +0300, Tapani Pälli wrote:
Hi Eric;
EGL_KHR_swap_buffers_with_damage is implemented by Android's EGL wrapper
library so these tests are passing already, no implementation required in
Mesa side.
Right, I keep forget
Reviewed-by: Timothy Arceri
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_sampler.c
b/src/mesa/state_tracker/
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
The GLSL linker takes care of it.
It seems the purpose was to unbind the states of samplers with an index
higher than the new highest value in samplers used, but it seems
cso_set_samplers() takes care of doing that for us anyway.
Rev
On 13/06/17 15:32, Timothy Arceri wrote:
On 13/06/17 04:23, Ilia Mirkin wrote:
On Mon, Jun 12, 2017 at 2:18 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st
On 13/06/17 04:23, Ilia Mirkin wrote:
On Mon, Jun 12, 2017 at 2:18 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_atom_sampler.c
b/src/mesa/state_tracker/
1-5:
Reviewed-by: Timothy Arceri
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_shader.c | 91 ++---
1 file changed, 28 insertions(+), 63 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_shader.c
b/src/mesa/
On Mon, Jun 12, 2017 at 7:38 PM, Connor Abbott wrote:
> On Mon, Jun 12, 2017 at 7:19 PM, Jason Ekstrand
> wrote:
> > On Mon, Jun 12, 2017 at 11:58 AM, Nicolai Hähnle
> wrote:
> >>
> >> On 12.06.2017 20:50, Connor Abbott wrote:
> >>>
> >>> On Mon, Jun 12, 2017 at 2:17 AM, Nicolai Hähnle
> >>> w
Lost track of this. People interested?
On 17-04-24 12:09:49, Emil Velikov wrote:
On 24 April 2017 at 11:56, Tapani Pälli wrote:
On 04/24/2017 01:52 PM, Emil Velikov wrote:
Hi Ben,
Just realised that the CrOS team might be interested in this as well -
adding Tomasz.
On 21 April 2017 at 18
On 13/06/17 01:31 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/gallium/auxiliary/util/u_threaded_context.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
> b/src/gallium/auxiliary/util/u_threaded_con
On Mon, Jun 12, 2017 at 7:19 PM, Jason Ekstrand wrote:
> On Mon, Jun 12, 2017 at 11:58 AM, Nicolai Hähnle wrote:
>>
>> On 12.06.2017 20:50, Connor Abbott wrote:
>>>
>>> On Mon, Jun 12, 2017 at 2:17 AM, Nicolai Hähnle
>>> wrote:
On 10.06.2017 01:44, Connor Abbott wrote:
>
>
On Mon, Jun 12, 2017 at 11:58 AM, Nicolai Hähnle wrote:
> On 12.06.2017 20:50, Connor Abbott wrote:
>
>> On Mon, Jun 12, 2017 at 2:17 AM, Nicolai Hähnle
>> wrote:
>>
>>> On 10.06.2017 01:44, Connor Abbott wrote:
>>>
From: Connor Abbott
These are properties of the instruction
Reviewed-by: Timothy Arceri
On 13/06/17 02:31, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
b/src/gallium/auxiliary/util
On 13/06/17 02:55, Marek Olšák wrote:
From: Marek Olšák
For the default framebuffer, _mesa_resize_framebuffer updates it.
For FBOs, _mesa_test_framebuffer_completeness updates it.
This code is redundant.
Everything in the series besides this patch is:
Reviewed-by: Timothy Arceri
You might
From: Dave Airlie
This allows us to skip cache flushing in the predicated area.
This gets about 10fps more on the deferred demo. (670->680)
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
src/amd/vulkan/radv_device.c | 3 +++
src/amd/vulkan/radv_private.h|
Humble ping for this one.
--Aaron
On Sun, Jun 4, 2017 at 7:32 PM, Aaron Watry wrote:
> clinfo no longer reports my discrete GCN card as unified memory
>
> Signed-off-by: Aaron Watry
> ---
> src/gallium/state_trackers/clover/api/device.cpp | 2 +-
> src/gallium/state_trackers/clover/core/devic
Am 13.06.2017 um 02:05 schrieb Ilia Mirkin:
> On Mon, Jun 12, 2017 at 7:57 PM, Roland Scheidegger
> wrote:
>> FWIW surely on nv50 you could keep a single mad instruction for umad
>> (sad maybe too?). (I'm actually wondering if the hw really can't do
>> unfused float multiply+add as a single instr
We can promote INVALIDATE_RANGE_BIT to INVALIDATE_BUFFER_BIT if the
range contains the only valid data in the buffer. This allows us to
orphan the storage, instead of doing stall avoidance blits.
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 7 +++
1 file changed, 7 insertions(+)
I
When writing a region of a buffer via glBufferSubData(), we can write
the data asynchronously if the destination doesn't contain any data.
Even if it's busy, the data was undefined, so the new data is fine too.
Decreases the number of stall avoidance blits in Manhattan 3.1:
- Skylake GT4: -18.3544
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 41 +---
src/mesa/drivers/dri/i965/intel_buffer_objects.h | 11 +++
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
b/src/mesa/drivers/dri/i965/intel_buf
This doesn't do anything yet, but soon we'll want to know whether an
access to a buffer section may write that data, or simply reads it.
---
src/mesa/drivers/dri/i965/brw_compute.c | 2 +-
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
src/mesa/drivers/dri/i965/brw_draw_upload
From: Dave Airlie
When using DCC some clear values don't require a cmask eliminate
step. This patch adds support for black and black with alpha 1,
there are other values, but I don't have access to a comprehensive list.
This works by setting the cmask eliminate predicate when doing the
fast clea
I am actually also thinking this should be different.
e.g. imho MAD means the operation can be either fused or unfused.
This is the "traditional" definition of MAD - opencl for instance will
follow this too, albeit this isn't mentioned in the gallium docs (it
probably should be).
(OpenCL says: "Wh
On Mon, Jun 12, 2017 at 7:57 PM, Roland Scheidegger wrote:
> FWIW surely on nv50 you could keep a single mad instruction for umad
> (sad maybe too?). (I'm actually wondering if the hw really can't do
> unfused float multiply+add as a single instruction but I know next to
> nothing about nvidia hw.
Am 13.06.2017 um 01:57 schrieb Roland Scheidegger:
> This looks like the right idea to me too. It may sound a bit weird to do
> that per instruction, but d3d11 does that as well. (Some d3d versions
> just have a global flag basically forbidding or allowing any such fast
> math optimizations in the
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jun 13, 2017 at 1:53 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> coverity complains about the deref before NULL check.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
With the unrelated line removed,
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jun 13, 2017 at 1:54 AM, Dave Airlie wrote:
> On 13 June 2017 at 09:53, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> has_hw_decode is assigned twice.
>>
>> Pointed out by coverity.
>>
>> Signed-off-by: Dave Airlie
>> --
This looks like the right idea to me too. It may sound a bit weird to do
that per instruction, but d3d11 does that as well. (Some d3d versions
just have a global flag basically forbidding or allowing any such fast
math optimizations in the assembly, but I'm not actually sure everybody
honors that w
On 13 June 2017 at 09:53, Dave Airlie wrote:
> From: Dave Airlie
>
> has_hw_decode is assigned twice.
>
> Pointed out by coverity.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_gpu_info.c | 1 -
> src/amd/vulkan/radv_cmd_buffer.c | 2 +-
> 2 files changed, 1 insertion(+), 2 delet
On Mon, Jun 12, 2017 at 7:53 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> has_hw_decode is assigned twice.
>
> Pointed out by coverity.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_gpu_info.c | 1 -
> src/amd/vulkan/radv_cmd_buffer.c | 2 +-
> 2 files changed, 1 insertion(+),
I found some patches on the git mailing list but looks like none of them
have been merged
http://git.661346.n2.nabble.com/PATCH-send-mail-Add-option-to-sleep-between-sending-each-email-td6769476.html
On Mon, 12 Jun 2017 at 23:22 Connor Abbott wrote:
> On Mon, Jun 12, 2017 at 2:30 AM, Nicolai Hä
From: Dave Airlie
has_hw_decode is assigned twice.
Pointed out by coverity.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_gpu_info.c | 1 -
src/amd/vulkan/radv_cmd_buffer.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/comm
From: Dave Airlie
coverity complains about the deref before NULL check.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b08f218..9f3
Am 12.06.2017 um 21:19 schrieb Brian Paul:
> On 06/12/2017 11:50 AM, Nicolai Hähnle wrote:
>> On 12.06.2017 19:37, Brian Paul wrote:
>>> For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render
>>> target queries, range of postion values, swizzling, etc. We basically
>>> follow the
On 11 June 2017 at 21:56, Marek Olšák wrote:
> On Sun, Jun 11, 2017 at 8:25 PM, Henri Verbeet wrote:
>> As someone downstream of this, I have to say I find the "family" names
>> much more informative than whatever marketing came up with. More
>> importantly however, this commit changes the GL_REN
Hi,
Edmondo on IRC reported that this series improves Civilization 5
performance and the improvement is not just tiny.
Marek
On Mon, Jun 12, 2017 at 6:55 PM, Marek Olšák wrote:
> Hi,
>
> This series only affects st/mesa, but other drivers can optionally
> be switched to this.
>
> I realized we
On Mon, Jun 12, 2017 at 3:28 PM, Francisco Jerez wrote:
> Anuj Phogat writes:
>
>> On Mon, Jun 12, 2017 at 12:22 PM, Francisco Jerez
>> wrote:
>>> Anuj Phogat writes:
>>>
On Mon, Jun 12, 2017 at 11:10 AM, Francisco Jerez
wrote:
> Anuj Phogat writes:
>
>> The new table
I can't say I like this neither.
This just seems to add complexity to the gallium interface for
questionable reasons. Reducing the srgb weirdness all different apis
have (and there's PLENTY of that all around) to just using different
formats everywhere is imho a very nice property I'd like to keep
https://bugs.freedesktop.org/show_bug.cgi?id=101397
Bug ID: 101397
Summary: [EGL] Surfaceless lacks swrast support
Product: Mesa
Version: 17.0
Hardware: All
OS: All
Status: NEW
Severity: normal
P
Woah... Coverity was useful.
Reviewed-by: Jason Ekstrand
On Mon, Jun 12, 2017 at 3:49 PM, Ian Romanick wrote:
> On 06/12/2017 02:37 AM, Lionel Landwerlin wrote:
> > Pretty obvious missing break statement.
>
> Right... it looks like the code may have been structured differently at
> one time.
>
On 06/12/2017 02:37 AM, Lionel Landwerlin wrote:
> Pretty obvious missing break statement.
Right... it looks like the code may have been structured differently at
one time.
Reviewed-by: Ian Romanick
>
> CID: 1412564
> Fixes: 641405f797 "i965: Use the new tracking mechanism for HiZ"
> Signed-of
Anuj Phogat writes:
> On Mon, Jun 12, 2017 at 12:22 PM, Francisco Jerez
> wrote:
>> Anuj Phogat writes:
>>
>>> On Mon, Jun 12, 2017 at 11:10 AM, Francisco Jerez
>>> wrote:
Anuj Phogat writes:
> The new table added in this patch matches with the table
> in gfxspecs. We were
On Mon, Jun 12, 2017 at 2:30 AM, Nicolai Hähnle wrote:
> FYI, somehow your mails don't show up in a single thread for me. They're in
> groups of 00-04, 05-09, 10-14, 15-17. Not sure what's up with that.
For some reason, the server at Valve rate-limits sending email, so git
send-email failed when
On Mon, Jun 12, 2017 at 10:43 PM, Jose Fonseca wrote:
> On 12/06/17 21:25, Marek Olšák wrote:
>>
>> On Mon, Jun 12, 2017 at 9:51 PM, Jose Fonseca wrote:
>>>
>>> How does this help exactly?
>>>
>>> Are applications actually rendering to the same FBO w/ and w/o SRGB
>>> decoding?
>>>
>>> Or is the
From: Nicolai Hähnle
si_build_shader_variant can actually be called directly from one of
normal-priority compiler threads. In that case, the thread_index is
only valid for the normal tm array.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101384 (maybe)
Fixes: 86cc8097266c ("radeonsi: u
Signed-off-by: Pierre Moreau
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index e03225517
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jun 12, 2017 at 9:49 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> Coverity pointed out this was returning uninitialised.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_device.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jun 12, 2017 at 9:54 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> Coverity warned about dead code below, as meta_va was being shadowed.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_image.c | 2 +-
> 1 file changed, 1 insertion(+), 1 delet
On 12/06/17 21:25, Marek Olšák wrote:
On Mon, Jun 12, 2017 at 9:51 PM, Jose Fonseca wrote:
How does this help exactly?
Are applications actually rendering to the same FBO w/ and w/o SRGB
decoding?
Or is the problem here GL_SRGB_WRITE state getting spuriously dirtied by the
application?
And e
Reviewed-by: Thomas Helland
On Jun 12, 2017 21:50, "Dave Airlie" wrote:
> From: Dave Airlie
>
> >>> Ignoring storage allocated by "reralloc_size(buf->mem_ctx,
> buf->data, buf->size)" leaks it.
>
> Signed-off-by: Dave Airlie
> ---
> src/util/u_dynarray.h | 2 +-
> 1 file changed, 1 insert
On Mon, Jun 12, 2017 at 9:51 PM, Jose Fonseca wrote:
> How does this help exactly?
>
> Are applications actually rendering to the same FBO w/ and w/o SRGB
> decoding?
>
> Or is the problem here GL_SRGB_WRITE state getting spuriously dirtied by the
> application?
>
> And even if they do, why is tog
Reviewed-by: Samuel Pitoiset
On 06/12/2017 09:50 PM, Dave Airlie wrote:
From: Dave Airlie
Ignoring storage allocated by "reralloc_size(buf->mem_ctx, buf->data,
buf->size)" leaks it.
Signed-off-by: Dave Airlie
---
src/util/u_dynarray.h | 2 +-
1 file changed, 1 insertion(+), 1 del
Reviewed-by: Samuel Pitoiset
On 06/12/2017 09:41 PM, Dave Airlie wrote:
From: Dave Airlie
Just use a temporary 16-bit index.
This fixes coverity issue, pointed to me by Ilia.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 9 ++---
1 file changed, 6 inser
On Mon, Jun 12, 2017 at 2:25 AM, Nicolai Hähnle wrote:
> On 10.06.2017 01:47, Connor Abbott wrote:
>>
>> From: Connor Abbott
>>
>> We're about to bump the number of system values above 32. The
>> system_values_read bitfield itself is 64 bits, but some users weren't
>> taking that into account. Fi
For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render
target queries, range of postion values, swizzling, etc. We basically
follow the DX10.1 conventions.
For the TXQS opcode and TGSI_SEMANTIC_SAMPLEID, clarify return value
and type.
For the TGSI_SEMANTIC_SAMPLEPOS system value
I've since discovered the fragment shader sample mask system value (which
corresponds to gl_SampleMaskIn).
v2: It's a system value, not a shader input.
---
src/gallium/docs/source/tgsi.rst | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/gallium/docs/source
From: Dave Airlie
Coverity warned about dead code below, as meta_va was being shadowed.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_image.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 91c7e5f..b08abf
On Mon, Jun 12, 2017 at 11:12 AM, Francisco Jerez wrote:
> Anuj Phogat writes:
>
>> Adding this variable better explains the computation for L3 way
>> size in the function.
>>
>> Signed-off-by: Anuj Phogat
>> Cc: Francisco Jerez
>> ---
>> src/intel/common/gen_l3_config.c | 11 ---
>> 1
How does this help exactly?
Are applications actually rendering to the same FBO w/ and w/o SRGB
decoding?
Or is the problem here GL_SRGB_WRITE state getting spuriously dirtied by
the application?
And even if they do, why is toggling surface views in framebuffer state
so expensive?
I don'
On Mon, Jun 12, 2017 at 12:22 PM, Francisco Jerez wrote:
> Anuj Phogat writes:
>
>> On Mon, Jun 12, 2017 at 11:10 AM, Francisco Jerez
>> wrote:
>>> Anuj Phogat writes:
>>>
The new table added in this patch matches with the table
in gfxspecs. We were programming the wrong values earli
From: Dave Airlie
>>> Ignoring storage allocated by "reralloc_size(buf->mem_ctx, buf->data,
>>> buf->size)" leaks it.
Signed-off-by: Dave Airlie
---
src/util/u_dynarray.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
inde
From: Dave Airlie
Coverity pointed out this was returning uninitialised.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_device.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 1ea6960..427d357 10064
From: Nicolai Hähnle
This fixes a bug when lowering ballotARB: previously, using writemask 0xf,
emit_asm would create TGSI_OPCODE_BALLOT instructions that span two registers
to cover 4 64-bit channels. This could trample over other a neighbouring
temporary.
Bugzilla: https://bugs.freedesktop.org
From: Dave Airlie
Just use a temporary 16-bit index.
This fixes coverity issue, pointed to me by Ilia.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.
On 12.06.2017 21:38, Dieter Nützel wrote:
'Undefined' or/equal as 'don't care'
which is much more useful for 'tricks'
like 'we' learned in chip design clause 3 decades ago?
But GL didn't allow 'don't care' I think?
GL should never see those fields. They only exist because everything's a
vec4
On 06/12/2017 01:38 PM, Dieter Nützel wrote:
'Undefined' or/equal as 'don't care'
which is much more useful for 'tricks'
like 'we' learned in chip design clause 3 decades ago?
But GL didn't allow 'don't care' I think?
gl_SampleID, for example, is a 1-component int in GLSL so the other
three c
'Undefined' or/equal as 'don't care'
which is much more useful for 'tricks'
like 'we' learned in chip design clause 3 decades ago?
But GL didn't allow 'don't care' I think?
Sorry, that I step in...;-)
Dieter
Am 12.06.2017 21:22, schrieb Ilia Mirkin:
That's actually stronger than saying that y
From: Nicolai Hähnle
Port of the corresponding fix in sid_tables.py.
---
src/gallium/drivers/r600/egd_tables.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/egd_tables.py
b/src/gallium/drivers/r600/egd_tables.py
index 4c60602..d7b78c7 100644
--- a
From: Nicolai Hähnle
st/mesa creates a surface that reinterprets the compressed blocks as
RGBA16UI or RGBA32UI. We have to adjust width0 & height0 accordingly to
avoid out-of-bounds memory accesses by CB.
Cc: 17.1
---
src/gallium/drivers/radeon/r600_texture.c | 7 ++-
1 file changed, 6 ins
From: Nicolai Hähnle
The very last entry in the sid_strings_offsets table ended up missing,
leading to out-of-bounds reads and potential crashes.
---
src/amd/common/sid_tables.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/sid_tables.py b/src/amd/common/sid
Anuj Phogat writes:
> On Mon, Jun 12, 2017 at 11:10 AM, Francisco Jerez
> wrote:
>> Anuj Phogat writes:
>>
>>> The new table added in this patch matches with the table
>>> in gfxspecs. We were programming the wrong values earlier.
>>>
>>> Signed-off-by: Anuj Phogat
>>> Cc: Francisco Jerez
>>
I think Ken is looking at some optimizations around push constants.
Maybe his work will replace this patch.
Any comment Ken?
Cheers,
-
Lionel
On 12/06/17 14:44, Alejandro Piñeiro wrote:
Gentle ping.
We have a patch, and a review, but it is not on master yet. An
oversight? Is there any reason
Or say they're undefined: sample pos = (x, y, undef, undef), for example.
I'd be OK with that. You?
-Brian
On 06/12/2017 11:47 AM, Ilia Mirkin wrote:
Perhaps this is wrong in the grand scheme of things, but at least
nouveau will *only* set the defined components of dst, not the
undefined ones
That's actually stronger than saying that you'll leave them alone...
and probably better. Undefined sounds great to me!
On Mon, Jun 12, 2017 at 3:13 PM, Brian Paul wrote:
> Or say they're undefined: sample pos = (x, y, undef, undef), for example.
>
> I'd be OK with that. You?
>
> -Brian
>
>
> On
On 06/12/2017 11:50 AM, Nicolai Hähnle wrote:
On 12.06.2017 19:37, Brian Paul wrote:
For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render
target queries, range of postion values, swizzling, etc. We basically
follow the DX10.1 conventions.
For the TXQS opcode and TGSI_SEMANTI
Oops, yes, I misread the code. I'll fix that. Thanks.
-Brian
On 06/12/2017 11:49 AM, Ilia Mirkin wrote:
It's actually a sysval, not an input.
On Mon, Jun 12, 2017 at 1:37 PM, Brian Paul wrote:
I've since discovered the fragment shader sample mask input (which
corresponds to gl_SampleMaskIn
On 06/12/2017 11:49 AM, Nicolai Hähnle wrote:
On 12.06.2017 19:37, Brian Paul wrote:
I've since discovered the fragment shader sample mask input (which
corresponds to gl_SampleMaskIn).
---
src/gallium/docs/source/tgsi.rst | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
On 12.06.2017 20:58, Connor Abbott wrote:
On Mon, Jun 12, 2017 at 2:21 AM, Nicolai Hähnle wrote:
On 10.06.2017 01:44, Connor Abbott wrote:
From: Connor Abbott
These optimizations happened to work with derivatives, but they won't
with upcoming shader_ballot and group_vote instructions.
Sign
On Mon, Jun 12, 2017 at 11:10 AM, Francisco Jerez wrote:
> Anuj Phogat writes:
>
>> The new table added in this patch matches with the table
>> in gfxspecs. We were programming the wrong values earlier.
>>
>> Signed-off-by: Anuj Phogat
>> Cc: Francisco Jerez
>> Cc: "17.1"
>> ---
>> src/intel/
On 12.06.2017 20:52, Nicolai Hähnle wrote:
On 12.06.2017 14:34, Gert Wollny wrote:
Am Montag, den 12.06.2017, 12:28 +0200 schrieb Nicolai Hähnle:
On 10.06.2017 01:15, Gert Wollny wrote:
Plenty of style issues aside, can you explain where and why you get
tighter lifetimes?
In the original c
On 12.06.2017 20:50, Connor Abbott wrote:
On Mon, Jun 12, 2017 at 2:17 AM, Nicolai Hähnle wrote:
On 10.06.2017 01:44, Connor Abbott wrote:
From: Connor Abbott
These are properties of the instruction that must be respected when
moving it around, in addition to the usual SSA dominance guarant
On Mon, Jun 12, 2017 at 2:21 AM, Nicolai Hähnle wrote:
> On 10.06.2017 01:44, Connor Abbott wrote:
>>
>> From: Connor Abbott
>>
>> These optimizations happened to work with derivatives, but they won't
>> with upcoming shader_ballot and group_vote instructions.
>>
>> Signed-off-by: Connor Abbott
On 12.06.2017 14:34, Gert Wollny wrote:
Am Montag, den 12.06.2017, 12:28 +0200 schrieb Nicolai Hähnle:
On 10.06.2017 01:15, Gert Wollny wrote:
Plenty of style issues aside, can you explain where and why you get
tighter lifetimes?
In the original code if a temporary is used within a loop it
On Mon, Jun 12, 2017 at 2:17 AM, Nicolai Hähnle wrote:
> On 10.06.2017 01:44, Connor Abbott wrote:
>>
>> From: Connor Abbott
>>
>> These are properties of the instruction that must be respected when
>> moving it around, in addition to the usual SSA dominance guarantee.
>> Previously, we only had
On Mon, Jun 12, 2017 at 2:18 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/mesa/state_tracker/st_atom_sampler.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_atom_sampler.c
> b/src/mesa/state_tracker/st_atom_sampler.c
> index f33e3
all subexpression inside an ir_assignment needs to be tagged as precise.
v2: make precise handling more global inside the visitor
Signed-off-by: Karol Herbst
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/state_tracker/
Anuj Phogat writes:
> Adding this variable better explains the computation for L3 way
> size in the function.
>
> Signed-off-by: Anuj Phogat
> Cc: Francisco Jerez
> ---
> src/intel/common/gen_l3_config.c | 11 ---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/src/i
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 5c09fed05c..6835c4fa8c 100644
--- a/src/gallium/drivers/nouveau/co
Signed-off-by: Karol Herbst
Reviewed-by: Nicolai Hähnle
---
src/gallium/auxiliary/tgsi/tgsi_build.c| 1 +
src/gallium/include/pipe/p_shader_tokens.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c
b/src/gallium/auxiliary/tgsi/tg
fixes
KHR-GL44.gpu_shader5.precise_qualifier
KHR-GL45.gpu_shader5.precise_qualifier
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.
fixes missrendering in TombRaider
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 1264dd4834..c633185893 10064
v2: use str_match_no_case to fix _SAT_PRECISE detection
Signed-off-by: Karol Herbst
---
src/gallium/auxiliary/tgsi/tgsi_text.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c
b/src/gallium/auxiliary/tgsi/tgsi_text.c
i
Only implemented for glsl->tgsi. Other converters just set precise to 0.
v2: remove precise paramter from ureg_tex_insn and ureg_memory_insn
Signed-off-by: Karol Herbst
---
src/gallium/auxiliary/tgsi/tgsi_build.c | 3 +++
src/gallium/auxiliary/tgsi/tgsi_ureg.c| 8 +-
src/gal
Signed-off-by: Karol Herbst
Reviewed-by: Nicolai Hähnle
---
src/gallium/auxiliary/tgsi/tgsi_dump.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c
b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index f6eba7424b..b58e64511c 100644
--- a/src/gallium/auxili
Anuj Phogat writes:
> The new table added in this patch matches with the table
> in gfxspecs. We were programming the wrong values earlier.
>
> Signed-off-by: Anuj Phogat
> Cc: Francisco Jerez
> Cc: "17.1"
> ---
> src/intel/common/gen_device_info.c | 1 +
> src/intel/common/gen_device_info.h
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_texture.c | 16 +---
src/mesa/state_tracker/st_sampler_view.c | 23 ---
src/mesa/state_tracker/st_sampler_view.h | 2 +-
src/mesa/state_tracker/st_texture.h | 2 +-
4 files changed, 23 insertions(+), 20 d
1 - 100 of 240 matches
Mail list logo
