On June 13, 2017 23:19:28 Chad Versace wrote:
On Thu 08 Jun 2017, Daniel Stone wrote:
From: Chad Versace
It converts a DRM format modifier to and from enum isl_tiling and
aux_usage. That's all.
Signed-off-by: Daniel Stone
---
src/intel/Makefile.isl.am | 1 +
src/intel/isl/isl.c | 5
On Thu 08 Jun 2017, Jason Ekstrand wrote:
> On Thu, Jun 8, 2017 at 11:43 AM, Daniel Stone wrote:
>
> > Hi,
> > With full support for modifiers in DRIimage, this patch series adds
> > support for fully plumbing them through X11. A patchset proposing
> > an extension to DRI3 to support multiple pla
Jason, I recall that you disliked this patch. Is that correct? If so,
why did you dislike it?
On Thu 08 Jun 2017, Daniel Stone wrote:
> From: Chad Versace
>
> make_ccs_surface_maybe() correctly handles failure
> isl_surf_get_ccs_surf(). When it fails, the resultant VkImage is still
> valid, just
Am Dienstag, den 13.06.2017, 11:07 +0200 schrieb Nicolai Hähnle:
>
>
> I'm curious what you'd suggest for getting rid of allocations anyway.
As the refactoring goes I think I will end up with a hybrid approach:
In the temporaries I will not keep the full time line, but the
important read/write
On Thu 08 Jun 2017, Daniel Stone wrote:
> From: Chad Versace
>
> It converts a DRM format modifier to and from enum isl_tiling and
> aux_usage. That's all.
>
> Signed-off-by: Daniel Stone
> ---
> src/intel/Makefile.isl.am | 1 +
> src/intel/isl/isl.c | 59
>
On Friday, June 9, 2017 7:04:38 AM PDT Topi Pohjolainen wrote:
> On gen < 6 one doesn't have level or layer specifiers available
> for render and depth targets. In order to support rendering to
> specific level/layer, driver needs to manually offset the surface
> to the desired slice.
> There are,
The storage was once used by get_sampler_uniform_value() but that
was fixed long ago to use the uniform storage assigned by the
linker.
By not assigning storage for images/samplers the constant buffer
for gallium drivers will be reduced which could result in small
perf improvements.
---
This wil
On 14/06/17 07:36 AM, Marek Olšák wrote:
> On Tue, Jun 13, 2017 at 5:18 AM, Michel Dänzer wrote:
>> On 13/06/17 01:31 AM, Marek Olšák wrote:
>>> From: Marek Olšák
>>>
>>> ---
>>> src/gallium/auxiliary/util/u_threaded_context.c | 9 +++--
>>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
On 13/06/17 08:08 PM, Gustaw Smolarczyk wrote:
> 2017-06-13 12:07 GMT+02:00 Michel Dänzer :
>> On 13/06/17 06:51 PM, Timothy Arceri wrote:
>>> On 13/06/17 19:22, Michel Dänzer wrote:
From: Michel Dänzer
It calling itself recursively prevented it from being inlined, resulting
in
From: Michel Dänzer
It calling itself recursively prevented it from being inlined, resulting
in a copy being generated in every compilation unit referencing it. This
bloated the text segment of the Gallium mega-driver *_dri.so by ~4%,
and might also have impacted performance.
Fixes: ecd6fce2611e
On Fri, Jun 9, 2017 at 7:04 AM, Topi Pohjolainen
wrote:
> On gen < 6 one doesn't have level or layer specifiers available
> for render and depth targets. In order to support rendering to
> specific level/layer, driver needs to manually offset the surface
> to the desired slice.
> There are, howeve
From: Marek Olšák
---
src/mesa/state_tracker/st_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_context.c
b/src/mesa/state_tracker/st_context.c
index b99a53b..0d376e4 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tr
On Tue, Jun 13, 2017 at 05:50:04PM +0300, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/dr
On Tue, Jun 13, 2017 at 4:54 PM, Jason Ekstrand
wrote:
> Looking through your code, I believe it is correct. I'm a bit concerned,
> however, because we're now copying back to the main surface on every draw
> call. If an app ever happens to hit this path, it will be correct, but
> it's performan
Looking through your code, I believe it is correct. I'm a bit concerned,
however, because we're now copying back to the main surface on every draw
call. If an app ever happens to hit this path, it will be correct, but
it's performance will tank. Unfortunately, a better implementation would
be a
That was fun to read through... So much code just goes away. :-) I made a
couple of fairly minor suggestions. The one semi-major concern I have is
that I don't see where you convert CCS over. Am I just missing it or is it
in another patch series?
--Jason
On Tue, Jun 13, 2017 at 7:53 AM, Topi P
On Tue, Jun 13, 2017 at 05:49:59PM +0300, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29
> +--
> 1 file changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipma
For patches 10-16:
Reviewed-by: Marek Olšák
Marek
On Sat, Jun 10, 2017 at 1:50 AM, Connor Abbott
wrote:
> From: Connor Abbott
>
> Ported from radeonsi. Needed for emitting optimization barriers, which
> contain inline asm.
>
> Signed-off-by: Connor Abbott
> ---
> src/amd/common/ac_llvm_util
I think I agree with the content of this patch but it needs a new commit
message. :-)
On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> because buffers get unconditionally initialised by cpu writing.
>
> Reviewed-by: Jason Ekstrand
> Signed-off-by: Topi Poh
On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Reviewed-by: Jason Ekstrand
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c| 2 +
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +-
> src/mesa/driver
On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Reviewed-by: Jason Ekstrand (v1)
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 64
> +--
> 1 file changed, 41 insertions(+), 23 deletions(
On Tue, Jun 13, 2017 at 4:14 PM, Jason Ekstrand
wrote:
> On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen <
> topi.pohjolai...@gmail.com> wrote:
>
>> Signed-off-by: Topi Pohjolainen
>> ---
>> src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++--
>> src/mesa/drivers/dri/i965/gen6_depth_stat
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f24b0b5..7991f81 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_t
---
src/mesa/drivers/dri/i965/brw_bufmgr.c| 6 ++--
src/mesa/drivers/dri/i965/brw_bufmgr.h| 12 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46 +--
src/mesa/drivers/dri/i965/intel_screen.c | 24 +++---
4 files changed, 44 insertions
ISL already has all of the complexity required to figure out the correct
surface pitch and size taking tile alignment into account. When we get
a surface out of ISL, the pitch and size are already correct and using
brw_bo_alloc_tiled_2d doesn't actually gain us anything other than extra
asserts we
On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++--
> src/mesa/drivers/dri/i965/gen6_depth_state.c | 12 +++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c
On Mon, Jun 12, 2017 at 11:26 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> si_build_shader_variant can actually be called directly from one of
> normal-priority compiler threads. In that case, the thread_index is
> only valid for the normal tm array.
>
> Bugzilla: https://bugs.freedesktop
On Tue, Jun 13, 2017 at 12:10 PM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_blit.c | 62
> ++
> 1 file changed, 48 insertions(+), 14 deletions(-)
>
> diff --git a/src/mesa/driver
Reviewed-by: Marek Olšák
Marek
On Mon, Jun 12, 2017 at 9:45 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> This fixes a bug when lowering ballotARB: previously, using writemask 0xf,
> emit_asm would create TGSI_OPCODE_BALLOT instructions that span two registers
> to cover 4 64-bit channe
Hi Lucas,
On Tue, Jun 13, 2017 at 7:20 PM, Fabio Estevam wrote:
> Excellent! This fixes the segfault. Thanks a lot!
Got a different segfault now. Please see below.
Thanks
[ideas] speed=duration:[ 218.073898] etnaviv-gpu 13.gpu: hangcheck detected
gpu lockup!
[ 218.080195] etnaviv-gpu 1
For the series:
Reviewed-by: Marek Olšák
Thanks for fixing this VM fault / hang!
Marek
On Mon, Jun 12, 2017 at 9:33 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> st/mesa creates a surface that reinterprets the compressed blocks as
> RGBA16UI or RGBA32UI. We have to adjust width0 & he
On Wed, Jun 14, 2017 at 12:12 AM, Miklós Máté wrote:
> On 05/06/17 18:50, Marek Olšák wrote:
>>
>> From: Marek Olšák
>>
>> so that LLVM IR looks like CSE has been run on it. It's also recommended
>> by the instruction combining pass.
>>
>> This also fixes:
>> - GL45-CTS.arrays_of_arrays_gl.Intera
On Tue, Jun 13, 2017 at 1:08 PM, Gustaw Smolarczyk wrote:
> 2017-06-13 12:07 GMT+02:00 Michel Dänzer :
>> On 13/06/17 06:51 PM, Timothy Arceri wrote:
>>> On 13/06/17 19:22, Michel Dänzer wrote:
From: Michel Dänzer
It calling itself recursively prevented it from being inlined, resul
On Tue, Jun 13, 2017 at 5:18 AM, Michel Dänzer wrote:
> On 13/06/17 01:31 AM, Marek Olšák wrote:
>> From: Marek Olšák
>>
>> ---
>> src/gallium/auxiliary/util/u_threaded_context.c | 9 +++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/util/u_thr
The swr driver uses vertex_buffer->stride to determinine the number
of elements in a VBO. A recent change to the state-tracker made it
possible for VBO's with stride=0. This resulted in a divide by zero
crash in the driver. The solution is to use the pre-calculated vertex
element stream_pitch in th
Hi Lucas,
On Tue, Jun 13, 2017 at 7:10 PM, Lucas Stach wrote:
> Hi Fabio,
>
> the attached patch should fix the issue. I should really try to get
> this upstream, as some people complained about this already...
Excellent! This fixes the segfault. Thanks a lot!
___
On 05/06/17 18:50, Marek Olšák wrote:
From: Marek Olšák
so that LLVM IR looks like CSE has been run on it. It's also recommended
by the instruction combining pass.
This also fixes:
- GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2 (crash)
- piglit/spec/arb_shader_ballot/execution/fs-rea
Tapani Pälli writes:
> On 06/12/2017 09:52 AM, Tapani Pälli wrote:
>>
>>
>> On 05/18/2017 09:39 PM, Eric Anholt wrote:
>>> Eric Anholt writes:
>>>
This series came out of fixing dEQP failures on vc4's GLES2 context.
Mesa was allowing RGB565 textures, which is only valid with
GL_
Hi Fabio,
the attached patch should fix the issue. I should really try to get
this upstream, as some people complained about this already...
Regards,
Lucas
Am Dienstag, den 13.06.2017, 16:20 -0300 schrieb Fabio Estevam:
> Hi,
>
> I am running kernel 4.11.4 with Etnaviv 17.1.2 on a imx6qsabresd
Reviewed-by: Marek Olšák
Marek
On Tue, Jun 13, 2017 at 11:26 PM, Samuel Pitoiset
wrote:
> When the current bound shaders don't use any bindless textures
> or images, it's useless to decompress the resident resources.
>
> v5: - fix conditionals
> v4: - inline si_*_uses_bindless_*()
> v3: - rebas
On Tue, Jun 13, 2017 at 3:46 AM, Timothy Arceri wrote:
> On 13/06/17 02:55, Marek Olšák wrote:
>>
>> From: Marek Olšák
>>
>> For the default framebuffer, _mesa_resize_framebuffer updates it.
>> For FBOs, _mesa_test_framebuffer_completeness updates it.
>>
>> This code is redundant.
>
>
> Everythin
According to the docs, a simple CS stall is insufficient to ensure that
the memory from the flush is visible and an end-of-pipe sync is needed.
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_p
From: Topi Pohjolainen
v2 (Jason Ekstrand):
- Take a flags parameter to control the flushes
- Refactoring
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_pipe_control.c | 96 +++-
2 files changed,
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 32 +
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 2 +-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 79b
These two functions contain almost identical logic except for one SNB
workaround required for render target cache flushes. They may as well
call into the same code so we only have to handle the work-arounds in
one place.
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 137 +
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 97b6bbf..df52165 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_sta
As I've been working on converting more things in the GL driver over to
blorp, I've been highly annoyed by all of the hangs on Haswell. About one
in 3-5 Jenkins runs would hang somewhere. After looking at about a
half-dozen error states, I noticed that all of the hangs seemed to be on
fast-clear
It's a 64-bit value. Splitting it up just makes the function arguments
awkward.
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_pipe_control.c | 22 ++
src/mesa/drivers/dri/i965/brw_queryobj.c | 5 ++---
src/mesa/drivers/dri/i965/ge
---
src/mesa/drivers/dri/i965/brw_blorp.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index e9745ef..f47e837 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/dr
When the current bound shaders don't use any bindless textures
or images, it's useless to decompress the resident resources.
v5: - fix conditionals
v4: - inline si_*_uses_bindless_*()
v3: - rebased and updated check for compute
Signed-off-by: Samuel Pitoiset
Reviewed-by: Marek Olšák (v2)
---
s
On 06/13/2017 11:13 PM, Marek Olšák wrote:
On Mon, Jun 12, 2017 at 2:36 PM, Samuel Pitoiset
wrote:
When the current bound shaders don't use any bindless textures
or images, it's useless to decompress the resident resources.
v4: - inline si_*_uses_bindless_*()
v3: - rebased and updated check
On Mon, Jun 12, 2017 at 2:36 PM, Samuel Pitoiset
wrote:
> When the current bound shaders don't use any bindless textures
> or images, it's useless to decompress the resident resources.
>
> v4: - inline si_*_uses_bindless_*()
> v3: - rebased and updated check for compute
>
> Signed-off-by: Samuel P
Ignore my previous question.
Reviewed-by: Marek Olšák
Marek
On Mon, Jun 12, 2017 at 2:35 PM, Samuel Pitoiset
wrote:
> This adds some new helper functions to know if the current draw
> call (or dispatch compute) is using bindless samplers/images,
> based on TGSI analysis.
>
> v4: - rename si_bi
On Mon, Jun 12, 2017 at 2:37 PM, Samuel Pitoiset
wrote:
> Please ignore this one.
So which one can I review?
Marek
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Fri, Jun 9, 2017 at 3:35 PM, Samuel Pitoiset
wrote:
> Similar to the existing decompression code path except that it
> loops over the list of resident textures/images.
>
> v3: - move the blitter check back to si_decompress_textures()
> - decompress resident textures directly in si_decompres
Looks good to me.
For the series:
Reviewed-by: Samuel Pitoiset
On 06/11/2017 03:52 PM, Boyan Ding wrote:
Some performance counters in nouveau uses non-integer type in AMD_perfmon,
but they are currently returning int values. One reason behind this is
that gallium hud, which is one of the user
Rb, anyone?
Thanks,
Marek
On Wed, Jun 7, 2017 at 10:09 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/mesa/state_tracker/st_cb_strings.c | 4 +---
> src/mesa/state_tracker/st_context.h| 2 --
> 2 files changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/src/mesa/state_tracke
On 14/06/17 02:15, Eero Tamminen wrote:
Hi,
On 13.06.2017 18:35, Ernst Sjöstrand wrote:
does GfxBench v4 work on RadeonSI at all?
GfxBench Manhattan, CarChase and tessellation tests require GL 4.x, its
other tests (like Driver2) work with GL 3.x. Public GUI version is
build with Qt.
Why
Hello Fabio,
Can you get a traceback using gdb?
That'd be very useful to find out where in the driver this crash happens.
Regards,
Wladimir
On Tue, Jun 13, 2017 at 04:20:23PM -0300, Fabio Estevam wrote:
> Hi,
>
> I am running kernel 4.11.4 with Etnaviv 17.1.2 on a imx6qsabresd board
> and when
Hi,
I am running kernel 4.11.4 with Etnaviv 17.1.2 on a imx6qsabresd board
and when I try to run glmark I am getting a segmentation fault:
# glmark2-es2-drm
** Failed to set swap interval. Results may be bounded above by refresh rate.
===
gl
Aaron Watry writes:
> Humble ping for this one.
>
Thanks for CC'ing me on this -- Patch is:
Reviewed-by: Francisco Jerez
> --Aaron
>
> On Sun, Jun 4, 2017 at 7:32 PM, Aaron Watry wrote:
>> clinfo no longer reports my discrete GCN card as unified memory
>>
>> Signed-off-by: Aaron Watry
>> --
Depth buffers are always Y-tiled. In brw_miptree_choose_tiling()
driver opts to use linear buffers for small and 1D but this does
not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT
are considered first.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_misc_state.c
Current logic calls intel_renderbuffer_set_draw_offset() which in
turn tries to calculate x and y offset against layer/level settings
that are against the original miptree actually having sufficient
levels/layers. This returns correctly x=0 y=0 regardless of the given
layer/level only because one c
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_misc_state.c| 9 +-
src/mesa/drivers/dri/i965/gen6_depth_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 5 +-
src/mesa/drivers/dri/i965/intel_fbo.c
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 20 ++-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 26 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 ---
3 files changed, 37 insertions(+), 45 del
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 ++--
2 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/dr
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a2d4fa9d92..c513a
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4472f822ea..9fdd56eaf2
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_fbo.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index e49f6df408..04ca480dfa 100644
--- a/src/mesa/drivers/dri/i965/in
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_blit.c | 62 ++
1 file changed, 48 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index e79e02a075..456c5e56bc 100644
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 871559edf9..3b68b437
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a401af0423..9c15c1071e 100644
--- a/s
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 103 +--
1 file changed, 57 insertions(+), 46 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f6b0d368de
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 9fdd56eaf2..a2d4fa9d92 100644
--- a/src/mesa/drivers/dri/i96
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 35 ++-
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 9c15c1071e..4472
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c6cac22e3b..6b05e
Building on top of hiz and stencil isl, this series first moves gen7+
stencil and then all depth surfaces on top of isl.
Topi Pohjolainen (15):
i965: Prepare blit engine for isl based miptrees
i965: Refactor miptree to isl converter and adjustment
i965: Prepare tex, img and rt state emission
On Fri 09 Jun 2017, Tapani Pälli wrote:
>
>
> On 06/08/2017 09:27 PM, Chad Versace wrote:
> > On Thu 08 Jun 2017, Tomasz Figa wrote:
> > > On Thu, Jun 8, 2017 at 4:08 PM, Tapani Pälli
> > > wrote:
> > > >
> > > > On 06/08/2017 09:36 AM, Tapani Pälli wrote:
> > > > >
> > > > >
> > > > >
> >
Marek Olšák writes:
> From: Marek Olšák
>
> If you want to keep it for your driver, please raise your hand.
> The prefix will probably have to be added into the driver instead of here.
>
> I cringe when I look at my long renderer string:
> Gallium 0.4 on AMD Radeon R9 Fury Series (DRM 3.17.0 /
Signed-off-by: Nanley Chery
---
src/intel/blorp/blorp_clear.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 3d5c41cc71..f43d05ad19 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -308,6
A GPU memcpy function could alternatively be implemented using MI_*
commands. Provide more detail into how this one operates in case another
memcpy function is created.
v2: Update the commit message.
Suggested-by: Jason Ekstrand
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_genX.h
In the future, we plan on using this method to resolve images whose
surface state fast-clear value is dynamically updated during command
buffer execution. Start using it now for testing and to reduce churn
later on.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_blorp.c | 29 ++
Reflect the fact that an image view or subresource range with the color
aspect cannot have any other aspect.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/in
This will be used in the next patch.
v2:
- Omit BLORP_BATCH_NO_EMIT_DEPTH_STENCIL (Jason Ekstrand)
- Update commit message.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_blorp.c | 41 +
src/intel/vulkan/anv_private.h | 6 ++
2 files changed,
Splitting out these fields will make the color buffer transitioning
function simpler when it gains more features.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_blorp.c | 33
src/intel/vulkan/anv_private.h | 4 ++--
src/intel/vulkan/genX_cmd_buff
For 3D image subresources undergoing a layout transition via
PipelineBarrier, we increase the number of fast-cleared layers to match
the intended behaviour of KHR_maintenance1. When such subresources
undergo layout transitions between subpasses, we don't do this to avoid
failing incorrect CTS tests
This series implements refactors and behavioral changes to make the
follow-on series which implements layout-based CCS resolves a lot
clearer.
Cc: Jason Ekstrand
Nanley Chery (13):
intel/blorp: Assert on subresource in surface_info_init
intel/blorp: Assert on gen7 fast-cleared subresource
Signed-off-by: Nanley Chery
---
src/intel/blorp/blorp.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 9c88658e8a..993b42fa85 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -66,6 +66,8 @@ brw_blorp_surface_inf
v2:
- Do layered resolves.
(Jason Ekstrand):
- Replace "bt" suffix with "attachment".
- Rename helper function to prepare_ccs_resolve.
- Move blorp_params_init() into helper function.
Signed-off-by: Nanley Chery
---
Looks like layered CCS resolves actually do work. I must have had a bug
in my in
v2: Omit the commit message.
Reviewed-by: Jason Ekstrand (v1)
Signed-off-by: Nanley Chery
---
src/intel/isl/isl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index b593e153dc..ccc8e16824 100644
--- a/src/intel/isl/isl.c
+++ b/src
Signed-off-by: Nanley Chery
---
src/intel/isl/isl.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 860fc28b27..b593e153dc 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1714,14 +1714,19 @@ isl_surf_get_c
Make the function take in an image instead of an image view. This
enables us to record relocations for surfaces states created outside of
the anv_CreateImageView path.
v2 (Jason Ekstrand):
- Use image->offset instead of surf_offset in aux_offset calculation.
Signed-off-by: Nanley Chery
---
src/
v2:
- Check for aux levels in layer helper (Jason Ekstrand)
- Don't assert aux is present, return 0 if it isn't.
- Use the helpers.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_blorp.c | 4
src/intel/vulkan/anv_private.h | 39 +++
2 files chang
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen10.xml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 04d89cb..64041c1 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3386,8 +3386,
Few of the fields in this register are changed as compared
to gen9.xml.
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen10.xml | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index d2bb130..e8776c7 100644
---
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_private.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index fe6ac3b..e5d88f2 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
This patch just enables building Vulkan libs for gen10. We
still don't have gen 10 support enabled on Vulkan.
Signed-off-by: Anuj Phogat
---
src/intel/Makefile.sources | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index a877ff2..2
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen10.xml | 69 +++---
1 file changed, 65 insertions(+), 4 deletions(-)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index ebeb5da8f..26dba22 100644
--- a/src/intel/genxml/gen10.xml
++
This field is removed from CACHE_MODE_1 register in gen10.
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_state.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 00c4105..7a16ec0 100644
--- a/s
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen10.xml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 64041c1..06260cf 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -900,7 +900,7 @@
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