Re: [Mesa-dev] [PATCH 12/16] i965: drop brw->must_use_separate_stencil in favor of devinfo's

On 30/08/17 11:38, Emil Velikov wrote: On 30 August 2017 at 11:07, Lionel Landwerlin wrote: @@ -249,6 +249,7 @@ static mesa_format intel_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat) { struct brw_context *brw = brw_context(ctx); +

Re: [Mesa-dev] [PATCH 15/16] i965: drop brw->has_surface_tile_offset in favor of devinfo's

On 30/08/17 11:40, Emil Velikov wrote: On 30 August 2017 at 11:07, Lionel Landwerlin wrote: --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -79,6 +79,7 @@ get_isl_surf(struct brw_context *brw,

Re: [Mesa-dev] [PATCH 15/16] i965: drop brw->has_surface_tile_offset in favor of devinfo's

On 30 August 2017 at 11:07, Lionel Landwerlin wrote: > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > @@ -79,6 +79,7 @@ get_isl_surf(struct brw_context *brw, struct > intel_mipmap_tree *mt, > >

Re: [Mesa-dev] [PATCH 12/16] i965: drop brw->must_use_separate_stencil in favor of devinfo's

On 30 August 2017 at 11:07, Lionel Landwerlin wrote: > @@ -249,6 +249,7 @@ static mesa_format > intel_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat) > { > struct brw_context *brw = brw_context(ctx); > + const struct gen_device_info

Re: [Mesa-dev] [PATCH 00/16] anv/i965: Cleanup copies of devinfo fields in brw_context

On Wed, 2017-08-30 at 11:10 +0100, Lionel Landwerlin wrote: > You can find this series on github :  > https://github.com/djdeath/mesa/tree/wip/djdeath/drop-is-has-brw > > (One paches got caught by the mailing list's size limit) > Assuming there is no regressions on Intel CI, series is:

Re: [Mesa-dev] [PATCH 00/16] anv/i965: Cleanup copies of devinfo fields in brw_context

You can find this series on github : https://github.com/djdeath/mesa/tree/wip/djdeath/drop-is-has-brw (One paches got caught by the mailing list's size limit) On 30/08/17 11:07, Lionel Landwerlin wrote: Hi all, Following a quick discussion on IRC, Matt reminded me we still had some

Re: [Mesa-dev] V2 radeonsi use STD430 packing of UBOs by default

If LLVM was fixed to do the correct thing, we could enable CONSTBUF LOAD for LLVM 6.0 and later. Marek On Wed, Aug 30, 2017 at 9:18 AM, Timothy Arceri wrote: > On 30/08/17 10:25, Marek Olšák wrote: >> >> I have to conclude that I don't see a way to use LOAD with CONSTBUF

[Mesa-dev] [PATCH 16/16] i965: drop unused brw->needs_unlit_centroid_workaround

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 2 -- src/mesa/drivers/dri/i965/brw_context.h | 9 - 2 files changed, 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] [PATCH 13/16] i965: drop unused brw->has_pln

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index

[Mesa-dev] [PATCH 11/16] i965: drop unused brw->has_negative_rhw_bug

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index

[Mesa-dev] [PATCH 12/16] i965: drop brw->must_use_separate_stencil in favor of devinfo's

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++- 4 files

[Mesa-dev] [PATCH 14/16] i965: drop unused brw->no_simd8

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 02ba0948cf8..d6fb9146129 100644 ---

[Mesa-dev] [PATCH 08/16] i965: drop brw->is_broxton

We need to take some take here as brw->is_broxton has been used to check whether the device is a low power gen9 (aka Atom gen9 platform). Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 -

[Mesa-dev] [PATCH 15/16] i965: drop brw->has_surface_tile_offset in favor of devinfo's

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_misc_state.c | 3 ++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7

[Mesa-dev] [PATCH 10/16] i965: drop unused brw->has_compr4

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index

[Mesa-dev] [PATCH 04/16] i965: drop brw->is_g4x in favor of devinfo->is_g4x

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_blorp.c| 2 +- src/mesa/drivers/dri/i965/brw_context.c | 3 +-- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_curbe.c| 2 +-

[Mesa-dev] [PATCH 05/16] i965: drop brw->is_baytrail in favor of devinfo->is_baytrail

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +- src/mesa/drivers/dri/i965/gen7_l3_state.c | 6 +++---

[Mesa-dev] [PATCH 06/16] i965: drop brw->is_haswell in favor of devinfo->is_haswell

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 5 ++--- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_cs.c| 2 +- src/mesa/drivers/dri/i965/brw_draw.c

[Mesa-dev] [PATCH 07/16] i965: drop brw->is_cherryview in favor of devinfo->is_cherryview

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 3 +-- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/genX_state_upload.c | 4 +++- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH 03/16] i965: drop brw->gt in favor of devinfo->gt

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c | 1 - src/mesa/drivers/dri/i965/brw_context.h | 2 -- src/mesa/drivers/dri/i965/brw_queryobj.c | 4 ++-- src/mesa/drivers/dri/i965/gen7_urb.c | 4 ++--

[Mesa-dev] [PATCH 09/16] i965: drop brw->has_llc in favor of devinfo->has_llc

Signed-off-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_context.c| 1 - src/mesa/drivers/dri/i965/brw_context.h| 1 - src/mesa/drivers/dri/i965/intel_batchbuffer.c | 6 -- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-

[Mesa-dev] [PATCH 01/16] anv: use device->info instead of brw->is_*

Signed-off-by: Lionel Landwerlin --- src/intel/vulkan/genX_pipeline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 83c4487bf9b..6dfa49b8737 100644 ---

[Mesa-dev] [PATCH 00/16] anv/i965: Cleanup copies of devinfo fields in brw_context

Hi all, Following a quick discussion on IRC, Matt reminded me we still had some duplicated fields on brw_context which just hold the same values as gen_device_info. Let's just use gen_device_info instead. Cheers, Lionel Landwerlin (16): anv: use device->info instead of brw->is_* i965: drop

Re: [Mesa-dev] [PATCH 8/8] fix test makefile

Hi Thomas, Analogous to 7/8 please squash this with 2/8. On 29 August 2017 at 20:56, Thomas Helland wrote: > --- > src/util/tests/string_buffer/Makefile.am | 16 ++-- > 1 file changed, 10 insertions(+), 6 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 7/8] port to gtest

On 29 August 2017 at 20:56, Thomas Helland wrote: > --- > src/util/tests/string_buffer/append_and_print.c | 99 -- > src/util/tests/string_buffer/append_and_print.cpp | 221 > ++ > 2 files changed, 221 insertions(+), 99 deletions(-) >

Re: [Mesa-dev] [PATCH 2/8] util: Add tests for the string buffer

On 29 August 2017 at 20:56, Thomas Helland wrote: > -SUBDIRS = xmlpool . tests/hash_table > +SUBDIRS = . tests/hash_table \ > + . tests/string_buffer > xmlpool disappeared here and current directory (.) is seen multiple times. To minimise this kind of issues I

Re: [Mesa-dev] [PATCH 0/8] Resend of preprocessor series

Hi Thomas, On 29 August 2017 at 20:56, Thomas Helland wrote: > This is a resend of the string buffer implementation and > related patches sent out back in May. I've done one more > change to the string buffer; using u_string.h for a compatible > vsnprintf version to

Re: [Mesa-dev] [PATCH 1/2] gallium/radeon: sort DBG shader flags according to pipe_shader_type

On Wed, Aug 30, 2017 at 11:19 AM, Emil Velikov wrote: > Hi Marek, > > There's a couple of subtle changes in the patch. If intentional, could > you mention that in the commit message? > > On 29 August 2017 at 23:25, Marek Olšák wrote: > >> static void

Re: [Mesa-dev] [PATCH 3/6] vl/compositor: make vl_compositor_set_yuv_layer() static

On 29 August 2017 at 04:23, Leo Liu wrote: > Since it's no longer being called outside of compositor > Thanks Leo, for the split. There's a vl_compositor_set_yuv_layer reference loose in the header. Please remove that one with the patch, but don't bother resending. -Emil

Re: [Mesa-dev] [PATCH 1/2] gallium/radeon: sort DBG shader flags according to pipe_shader_type

Hi Marek, There's a couple of subtle changes in the patch. If intentional, could you mention that in the commit message? On 29 August 2017 at 23:25, Marek Olšák wrote: > static void r600_disk_cache_create(struct r600_common_screen *rscreen) > { > /* Don't use the

Re: [Mesa-dev] [PATCH] llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSOR

Am 30.08.2017 um 04:49 schrieb Brian Paul: > On 08/29/2017 06:17 PM, Roland Scheidegger wrote: >> Looks good to me, thanks. >> >> Reviewed-by: Roland Scheidegger >> >> Albeit I'm not quite sure why it is never set here? > > This particular test sets a 0 x 0 scissor region. 

Re: [Mesa-dev] [PATCH 1/2] gallium/radeon: sort DBG shader flags according to pipe_shader_type

Reviewed-by: Samuel Pitoiset On 08/30/2017 12:25 AM, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/r600/r600_pipe.c | 2 +- src/gallium/drivers/radeon/r600_pipe_common.c | 20 ++--

[Mesa-dev] [Bug 102318] Mesa3D Scons build - LLVM 5.0 not supported

https://bugs.freedesktop.org/show_bug.cgi?id=102318 --- Comment #1 from Emil Velikov --- Based on the error message, it seems that the HAVE_LLVM does not end up with the correct version (0x0500). To fix this you want to look at the way llvm_version is handled in

[Mesa-dev] [Bug 102318] Mesa3D Scons build - LLVM 5.0 not supported

https://bugs.freedesktop.org/show_bug.cgi?id=102318 Alex Granni changed: What|Removed |Added See Also|

[Mesa-dev] [Bug 100201] Windows scons build with MSVC toolchain and LLVM 4.0 fails

https://bugs.freedesktop.org/show_bug.cgi?id=100201 Alex Granni changed: What|Removed |Added See Also|

Re: [Mesa-dev] Question about implementing viewport transfer and const load in nir

> btw, does lima have some way to write to memory from cmdstream (ie. > without setting up a full blown draw)? If so perhaps you could get > away with leaving some extra space at the end of your uniform buffer > that you copy driver internal uniforms into before kicking the draw? Unfortunately

Re: [Mesa-dev] V2 radeonsi use STD430 packing of UBOs by default

On 30/08/17 10:25, Marek Olšák wrote: I have to conclude that I don't see a way to use LOAD with CONSTBUF and keep the same performance as before. It looks like there are some deficiencies in our compiler stack that are unfixable in Mesa alone. Well that's frustrating :( Pretty much makes

Re: [Mesa-dev] Question about implementing viewport transfer and const load in nir

> In my case, VC4 has lots of custom state-dependent uniforms, and uniform > upload is where we spend most of our CPU time (basically each draw call > needs to re-upload the uniform stream, and the stream has to be in the > order they will be used by instructions, rather than where they appear >

Re: [Mesa-dev] [PATCH 2/2] i965: Implement ARB_indirect_parameters

So as a random drive-by review, I think the risk in this implementation is that apps just set maxdrawcount to some high value . If I'm reading the spec correctly there is no real bound on the value except for the max-representable value for the integer. Also AFAIK the AMD and NVidia

Re: [Mesa-dev] Question about implementing viewport transfer and const load in nir

Thanks Kenneth, here attach my RFC prototype patch implementing these, and comments follows. >> When working on lima gp compiler, I come across two problems about >> inserting extra uniform >> and instructions in nir for the driver and don't know where's the >> right place to do it. So I'd like

[Mesa-dev] [PATCH v2] i965/fs: Add remove_extra_rounding_modes optimization

Although from SPIR-V point of view, rounding modes are attached to the operation/destination, on i965 it is a status, so we don't need to explicitly set the rounding mode if the one we want is already set. v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate with the rounding

[Mesa-dev] [PATCH v2] i965/fs: Enable rounding mode on f2f16 ops

By default we don't set the rounding mode. We only set round-to-near-even or round-to-zero mode if explicitly set from nir. v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate with the rounding mode (Curro) Signed-off-by: Jose Maria Casanova Crespo

[Mesa-dev] [PATCH v2] i965/fs: Define new shader opcode to set rounding modes

Although it is possible to emit them directly as AND/OR on brw_fs_nir, having a specific opcode makes it easier to remove duplicate settings later. v2: (Curro) - Set thread control to 'switch' when using the control register - Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate

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