[Mesa-dev] [PATCH] intel: Always set Cube Face Enables for all surfaces.

These shouldn't matter for non-cubes, and we always enable them all for cubes, so we may as well set them all the time. We can just mark the fields "mbo" (must be one) and genxml will automatically set them for us, and we never even have to think about them. --- src/intel/genxml/gen10.xml

[Mesa-dev] [Bug 101397] [EGL] Surfaceless lacks swrast support

https://bugs.freedesktop.org/show_bug.cgi?id=101397 Carlos Alberto Lopez Perez changed: What|Removed |Added See Also|

[Mesa-dev] [PATCH] glsl/ast: Stop processing a switch-statement after an error in the init-expression

From: Ian Romanick This happens to work now because ir_binop_all_equal is used. This causes vector typed init-expressions to produce scalar Boolean values after comparison. The next commit changes ir_binop_all_equal to ir_binop_equal. Vector typed init-expressions

[Mesa-dev] [PATCH v2] meson: change vulkan icd config to - instead of _

Just to be consistent. v2: - update meson.build too Signed-off-by: Dylan Baker --- meson.build | 2 +- meson_options.txt | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index add27b5dbac..2e1de2b2e20 100644 ---

Re: [Mesa-dev] [PATCH 13/13] i965/fs: Don't apply POW/FDIV workaround on Gen10+

Matt Turner writes: > The documentation says it applies only to Gens 8 and 9. Patch 10 & 13: Reviewed-by: Scott D Phillips > --- > src/intel/compiler/brw_fs_generator.cpp | 1 + > 1 file changed, 1 insertion(+) > > diff --git

Re: [Mesa-dev] [PATCH 12/13] i965/fs: Use align1 mode on ternary instructions on Gen10+

Matt Turner writes: > Align1 mode offers some nice features over align16, like access to more > data types and the ability to use a 16-bit immediate. This patch does > not start using any new features. It just emits ternary instructions in > align1 mode. > --- >

Re: [Mesa-dev] [PATCH 11/13] i965: Add align1 ternary instruction emission support

Matt Turner writes: > --- > src/intel/compiler/brw_eu_emit.c | 196 > --- > 1 file changed, 143 insertions(+), 53 deletions(-) > > diff --git a/src/intel/compiler/brw_eu_emit.c > b/src/intel/compiler/brw_eu_emit.c > index

Re: [Mesa-dev] [PATCH 10/13] i965: Add align1 ternary instruction disassembler support

Matt Turner writes: > --- > src/intel/compiler/brw_disasm.c | 399 > +--- > src/intel/compiler/brw_eu_defines.h | 11 - > 2 files changed, 322 insertions(+), 88 deletions(-) > > diff --git a/src/intel/compiler/brw_disasm.c

Re: [Mesa-dev] [PATCH 09/13] i965: Add align1 ternary instruction-word support

Matt Turner writes: > --- > src/intel/compiler/brw_inst.h | 114 > ++ > 1 file changed, 114 insertions(+) > > diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h > index e6169057e3..b9c03fa88f 100644 > ---

Re: [Mesa-dev] [PATCH 08/13] i965: Add align1 ternary instruction support to conversion functions

Matt Turner writes: > --- > src/intel/compiler/brw_disasm.c | 12 --- > src/intel/compiler/brw_inst.h | 4 +-- > src/intel/compiler/brw_reg_type.c | 76 > --- > src/intel/compiler/brw_reg_type.h | 7 ++-- > 4 files changed, 79

Re: [Mesa-dev] [PATCH 03/13] i965: Print subreg in units of type-size on ternary instructions

Matt Turner writes: > The instruction word contains SubRegNum[4:2] so it's in units of dwords > (hence the * 4 to get it in terms of bytes). Before this patch, the > subreg would have been wrong for DF arguments. Trying to grok the subregnum stuff here, in brw_eu_emit.c I

[Mesa-dev] [PATCH] egl/surfaceless: Use KMS swrast fallback

From: Gurchetan Singh The kms_swrast extension is an actively developed software fallback, and platform_surfaceless can use it if there are no available hardware drivers. --- src/egl/drivers/dri2/platform_surfaceless.c | 77 ++--- 1 file

[Mesa-dev] [PATCH] anv: Implement VK_ANDROID_native_buffer (v8.1)

This implementation is correct (afaict), but takes two shortcuts regarding the import/export of Android sync fds. Shortcut 1. When Android calls vkAcquireImageANDROID to import a sync fd into a VkSemaphore or VkFence, the driver instead simply blocks on the sync fd, then puts the

Re: [Mesa-dev] [PATCH 6/7] i965: Reported supported context priorities to EGL/DRI

On Friday, September 29, 2017 1:03:14 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2017-09-29 20:55:53) > > On Friday, September 29, 2017 3:25:09 AM PDT Chris Wilson wrote: > > > Hook up the RendererQuery for __DRI2_RENDERER_HAS_CONTEXT_PRIORITY to > > > report the available

Re: [Mesa-dev] Using --enable-opencl-icd by default and deprecating the toggle

Aaron Watry writes: > On Fri, Sep 29, 2017 at 10:14 AM, Emil Velikov > wrote: >> Hi all, >> >> Currently nearly all the distributions I've seen* enable and use the ICD. >> Only Gentoo does not use it, but manages the OpenCL.so conflicts via eselect.

Re: [Mesa-dev] [PATCH 1/4] egl/dri2: don't use the template keyword

For the series, Reviewed-by: Brian Paul On 09/29/2017 03:27 PM, Marek Olšák wrote: From: Marek Olšák for C++ editors --- src/egl/drivers/dri2/platform_wayland.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH] st/mesa: don't use pipe_surface for passing information about EGLImage

From: Marek Olšák Use st_egl_image instead. radeonsi doesn't like when we create a pipe_surface with PIPE_FORMAT_NV12. This fixes NV12 texturing on radeonsi using kmscube. Cc: 17.1 17.2 --- src/mesa/state_tracker/st_cb_eglimage.c | 96

[Mesa-dev] [PATCH 2/4] gallium/vl: don't use the template keyword

From: Marek Olšák for C++ editors --- src/gallium/auxiliary/vl/vl_winsys_dri.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri.c b/src/gallium/auxiliary/vl/vl_winsys_dri.c index

[Mesa-dev] [PATCH 1/4] egl/dri2: don't use the template keyword

From: Marek Olšák for C++ editors --- src/egl/drivers/dri2/platform_wayland.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/egl/drivers/dri2/platform_wayland.c b/src/egl/drivers/dri2/platform_wayland.c index dc6fcc1..ae33477 100644 ---

[Mesa-dev] [PATCH 4/4] radeonsi: don't use the template keyword

From: Marek Olšák for C++ editors --- src/gallium/drivers/radeonsi/si_uvd.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c index 9f5daad..758e5cb 100644 ---

[Mesa-dev] [PATCH 3/4] glx: don't use the template keyword

From: Marek Olšák for C++ editors --- src/glx/dri_glx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/glx/dri_glx.c b/src/glx/dri_glx.c index 2d435f0..5c4346c 100644 --- a/src/glx/dri_glx.c +++ b/src/glx/dri_glx.c @@ -551,28 +551,28 @@

[Mesa-dev] [PATCH 18/21] ralloc: Allow reparenting to a NULL context

Reviewed-by: Tapani Pälli Reviewed-by: Ian Romanick --- src/util/ralloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/util/ralloc.c b/src/util/ralloc.c index 9cce9e0..42cfa2e 100644 --- a/src/util/ralloc.c +++

[Mesa-dev] [PATCH 15/21] anv/pipeline: Whack nir->num_uniforms to MAX_PUSH_CONSTANT_SIZE

This way any image uniforms end up having locations higher than MAX_PUSH_CONSTANT_SIZE. There's no bug here at the moment, but this consistency will make the next commit easier. Also, because nir_apply_pipeline_layout properly increments nir->num_uniforms when it expands the param array, we no

[Mesa-dev] [PATCH 09/21] intel/compiler: Add a flag for pull constant support

The Vulkan driver does not support pull constants. It simply limits things such that we can always push everything. Previously, we were determining whether or not to push things based on whether or not the prog_data::pull_param array is non-null. This is rather hackish and about to stop

[Mesa-dev] [PATCH 12/21] intel/compiler: Add a helper for growing the prog_data::param array

--- src/intel/compiler/brw_compiler.h | 13 + 1 file changed, 13 insertions(+) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 1ec79f6..f9679a3 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -28,6

[Mesa-dev] [PATCH 13/21] intel/cs: Grow prog_data::param on-demand for thread_local_id_index

Instead of making the caller of brw_compile_cs add something to the param array for thread_local_id_index, just add it on-demand in brw_nir_intrinsics and grow the array. This is now safe to do because everyone is now using ralloc for prog_data::param. --- src/intel/compiler/brw_fs.cpp

[Mesa-dev] [PATCH 20/21] intel/compiler: Allocate pull_param in assign_constant_locations

Now that everything is nicely ralloc'd, we can allocate the pull_param array in assign_constant_locations instead of higher up. We can also re-allocate the param array so that it's exactly the needed size. This should save us some memory because we're not allocating the total needed param space

[Mesa-dev] [PATCH 17/21] anv/pipeline: Refactor setup of the prog_data::param array

Now that the only thing we put in the array up-front are client push constants, we can simplify anv_pipeline_compile a bit. --- src/intel/vulkan/anv_pipeline.c | 23 +-- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c

[Mesa-dev] [PATCH 21/21] intel/cs: Make thread_local_id a regular builtin param

This is a lot more natural than special casing it all over the place. We still have to do a bit of special-casing in assign_constant_locations but it's not special-cased quite as bad as it was before. --- src/intel/compiler/brw_compiler.h | 3 +- src/intel/compiler/brw_fs.cpp

[Mesa-dev] [PATCH 19/21] intel: Allocate prog_data::[pull_]param deeper inside the compiler

Now that we're always growing the param array as-needed, we can allocate the param array in common code and stop repeating the allocation everywere. In order to keep things sane, we ralloc the [pull_]param array off of the compile context and then steal it back to a NULL context later. This

[Mesa-dev] [PATCH 16/21] anv/pipeline: Grow the param array for images

Before, we were calculating up-front and then filling in later. Now we just grow as needed in anv_nir_apply_pipeline_layout. --- src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 5 - src/intel/vulkan/anv_pipeline.c | 7 +-- 2 files changed, 5 insertions(+), 7

[Mesa-dev] [PATCH 14/21] intel/vs: Grow the param array for clip planes

Instead of requiring the caller of brw_compile_vs to figure it out, just grow the param array on-demand. --- src/intel/compiler/brw_fs_visitor.cpp | 7 +++ src/intel/compiler/brw_vec4_vs_visitor.cpp | 7 +++ src/mesa/drivers/dri/i965/brw_vs.c | 5 - 3 files changed, 14

[Mesa-dev] [PATCH 07/21] anv/pipeline: Add a mem_ctx parameter to anv_pipeline_compile

This lets us avoid some of the manual ralloc stealing and prepares for future commits in which we will want to ralloc prog_data::param. --- src/intel/vulkan/anv_pipeline.c | 72 ++--- 1 file changed, 39 insertions(+), 33 deletions(-) diff --git

[Mesa-dev] [PATCH 08/21] anv/pipeline: Ralloc prog_data::param of the compile mem_ctx

This way we stop leaking it. This is completely safe because, when we hand it off to anv_shader_bin_create or anv_pipeline_cache_upload_kernel, they make a copy of the entire param array. --- src/intel/vulkan/anv_pipeline.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 05/21] i965: Use prog->info.num_images for needs_dc computation

This should be just as good as looking in prog_data but removes our one state setup dependency on brw_stage_prog_data::nr_image_param. --- src/mesa/drivers/dri/i965/gen7_l3_state.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c

[Mesa-dev] [PATCH 10/21] i965: Only add the wpos state reference if we lowered something

Otherwise, in the ARB program case _mesa_add_state_reference may grow the parameter array which will cause brw_nir_setup_arb_uniforms to write past the end of the param array because it only looks at the parameter list length but the parma array is allocated based on nir->num_uniforms. The only

[Mesa-dev] [PATCH 11/21] intel/compiler: Stop adding params for texture sizes

We haven't needed this ever since we started using NIR for lowering rectangle textures. --- src/mesa/drivers/dri/i965/brw_cs.c | 3 --- src/mesa/drivers/dri/i965/brw_wm.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_cs.c

[Mesa-dev] [PATCH 04/21] intel: Rewrite the world of push/pull params

This moves us away to the array of pointers model and onto a model where each param is represented by a generic uint32_t handle. We reserve 2^16 of these handles for builtins that get generated by somewhere inside the compiler and have well-defined meanings. Generic params have handles whose

[Mesa-dev] [PATCH 03/21] i965: Get rid of gen7_cs_state.c

The only thing it was handling was push constants. We pull the actual constant upload code into gen6_constant_state.c and the atoms into genX_state_upload.c. --- src/mesa/drivers/dri/i965/Makefile.sources | 1 - src/mesa/drivers/dri/i965/brw_state.h | 5 +

[Mesa-dev] [PATCH 06/21] i965: Store image_param in brw_context instead of prog_data

This burns an extra 10k of memory or so in the case where you don't have any images. However, if you have several shaders which use images, this should be much less memory. It also gets rid of a part of prog_data that really has nothing to do with the compiler. ---

[Mesa-dev] [PATCH 00/21] intel/compiler: Rework the world of push/pull params

This little series reworks basically the entire world of push/pull params. This refactor has been on my ToDo list ever since I hooked up push constants in Vulkan over two years ago. Recently, thanks to some up-and-coming Vulkan features, the pain of the old system increased enough to finally push

[Mesa-dev] [PATCH 02/21] i965: Add a helper for populating constant buffers

--- src/mesa/drivers/dri/i965/brw_curbe.c | 12 ++-- src/mesa/drivers/dri/i965/brw_state.h | 7 +++ src/mesa/drivers/dri/i965/gen6_constant_state.c | 26 +++-- 3 files changed, 33 insertions(+), 12 deletions(-) diff --git

[Mesa-dev] [PATCH 01/21] i965: Move brw_upload_pull_constants to gen6_constant_state.c

--- src/mesa/drivers/dri/i965/brw_state.h| 2 +- src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 63 --- src/mesa/drivers/dri/i965/gen6_constant_state.c | 64 3 files changed, 65 insertions(+), 64 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 7/7] wayland-egl: rework and simplify wl_egl_window initialization

> Miguel I believe the comment correctly describes the design plan, while > addressing Dan's comment that things look a bit ugly. Yes. Thank you. Also, the whole series: Reviewed-by: Miguel A. Vico Thanks. On Fri, 29 Sep 2017 14:48:58 +0100 Daniel Stone

Re: [Mesa-dev] [PATCH 6/7] i965: Reported supported context priorities to EGL/DRI

Quoting Chris Wilson (2017-09-29 21:03:14) > Quoting Kenneth Graunke (2017-09-29 20:55:53) > > Typically we wait to pull in new headers until the kernel patches land > > in airlied's drm-next tree. > > drm-intel is a non-rebasing tree, once the commit lands there, it is > stable all the way

Re: [Mesa-dev] [PATCH 6/7] i965: Reported supported context priorities to EGL/DRI

Quoting Kenneth Graunke (2017-09-29 20:55:53) > On Friday, September 29, 2017 3:25:09 AM PDT Chris Wilson wrote: > > Hook up the RendererQuery for __DRI2_RENDERER_HAS_CONTEXT_PRIORITY to > > report the available DRM_I915_GEM_CONTEXT_SETPARAM options based on the > > the default context. The kernel

Re: [Mesa-dev] [PATCH 6/7] i965: Reported supported context priorities to EGL/DRI

On Friday, September 29, 2017 3:25:09 AM PDT Chris Wilson wrote: > Hook up the RendererQuery for __DRI2_RENDERER_HAS_CONTEXT_PRIORITY to > report the available DRM_I915_GEM_CONTEXT_SETPARAM options based on the > the default context. The kernel will validate the request to change the > property,

Re: [Mesa-dev] [PATCH 5/7] i965: Pass the EGL/DRI context priority through to the kernel

On Friday, September 29, 2017 3:25:08 AM PDT Chris Wilson wrote: > Decode the EGL/DRI priority enum into the [-1023, 1023] range as > interpreted by the kernel and call DRM_I915_GEM_CONTEXT_SETPARAM to > adjust the priority. We use 0 as the default medium priority (also the > kernel default) and

Re: [Mesa-dev] [PATCH 4/7] i965: Record the presence of the kernel scheduler

On Friday, September 29, 2017 3:25:07 AM PDT Chris Wilson wrote: > Mention to the debug log if the kernel scheduler is enabled; and in > particular if it has preemption enabled. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen >

Re: [Mesa-dev] Mesa 17.2.2 release candidate

On 29.09.2017 21:31, Juan A. Suarez Romero wrote: Hello list, The candidate for the Mesa 17.2.2 is now available. Currently we have: - 43 queued - 7 nominated (outstanding) - and 3 rejected patches In the current queue we have: In build and integration system, we add a dependency on

[Mesa-dev] [AppVeyor] mesa 17.2 #5652 completed

Build mesa 5652 completed Commit b78c664115 by Jason Ekstrand on 9/26/2017 4:42 PM: vulkan/wsi/wayland: Return better error messages\n\nReviewed-by: Daniel Stone \nCc: mesa-sta...@lists.freedesktop.org\n(cherry picked from commit

Re: [Mesa-dev] [PATCH v3] i965: skip reading unused slots at the begining of the URB for the FS

On Friday, September 29, 2017 4:08:17 AM PDT Iago Toral wrote: > On Fri, 2017-09-29 at 03:53 -0700, Kenneth Graunke wrote: > > On Friday, September 29, 2017 3:36:34 AM PDT Iago Toral Quiroga > > wrote: > > > We can start reading the URB at the first offset that contains > > > varyings > > > that

[Mesa-dev] Mesa 17.2.2 release candidate

Hello list, The candidate for the Mesa 17.2.2 is now available. Currently we have: - 43 queued - 7 nominated (outstanding) - and 3 rejected patches In the current queue we have: In build and integration system, we add a dependency on libunwind when running make distcheck, as this is

Re: [Mesa-dev] [PATCH V2] radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bb

Thanks. I'm keeping my patch and adding yours on top as a separate cleanup commit. I will push this after I get Rb tags for my patch from other guys. Marek On Fri, Sep 29, 2017 at 9:09 PM, Benedikt Schemmer wrote: > From: Benedikt Schemmer > Date: Fri, 29 Sep 2017

[Mesa-dev] [Bug 99856] OpenCL Hello world returns "unsupported call to function get_local_size"

https://bugs.freedesktop.org/show_bug.cgi?id=99856 Jan Vesely changed: What|Removed |Added Status|REOPENED|RESOLVED

[Mesa-dev] [PATCH V2] radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bb

From: Benedikt Schemmer Date: Fri, 29 Sep 2017 21:02:13 +0200 Subject: [PATCH V2] radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bb V2: remove code duplication and one unnessecary variable, minor whitespace fix --- src/gallium/drivers/radeonsi/si_uvd.c

[Mesa-dev] [AppVeyor] mesa master #5651 failed

Build mesa 5651 failed Commit d5e7ce28b5 by Kamil Páral on 9/22/2017 9:31 PM: drirc: whitelist glthread for Outlast\n\nFPS increase 10-20% in starting locations on Core i5-4570 +\nRadeon R9 270. Configure your notification preferences

Re: [Mesa-dev] [PATCH] radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bb

On Fri, Sep 29, 2017 at 7:54 PM, Benedikt Schemmer wrote: > Would it be ok to rewrite the patch like below? > Avoids code duplication and one variable. Yes, I'll commit it if send me a proper git patch. > > Otherwise your original patch works fine so FWIW you have my > >

[Mesa-dev] [PATCH] radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bb

Would it be ok to rewrite the patch like below? Avoids code duplication and one variable. Otherwise your original patch works fine so FWIW you have my Tested-by: Benedikt Schemmer Cheers, Benedikt diff --git a/src/gallium/drivers/radeonsi/si_uvd.c

Re: [Mesa-dev] [PATCH 08/11] glsl_to_tgsi: fix instruction order for bindless textures

The 17.1 tag should be removed, bindless is a thing only for the latest release. On 09/29/2017 07:32 PM, Samuel Pitoiset wrote: Missed that. Reviewed-by: Samuel Pitoiset On 09/29/2017 02:25 PM, Marek Olšák wrote: From: Marek Olšák We

Re: [Mesa-dev] [PATCH 08/11] glsl_to_tgsi: fix instruction order for bindless textures

Missed that. Reviewed-by: Samuel Pitoiset On 09/29/2017 02:25 PM, Marek Olšák wrote: From: Marek Olšák We emitted instructions loading the bindless handle after the memory instruction. Cc: 17.1 17.2 ---

Re: [Mesa-dev] [PATCH 02/12] i965/fs: Rewrite fsign64 to skip the float -> double conversion

On Fri, Sep 29, 2017 at 4:48 AM, Iago Toral wrote: > On Thu, 2017-09-28 at 23:05 -0700, Matt Turner wrote: >> ... without the float -> double conversion. Low power parts have >> additional restrictions when it comes to operating on 64-bit types, >> and >> the instruction used

Re: [Mesa-dev] [PATCH v2 3/7] travis: Add clover build using llvm-3.7

On Mon, 2017-09-18 at 16:46 +0100, Eric Engestrom wrote: > On Monday, 2017-09-18 11:10:37 -0400, Jan Vesely wrote: > > On Mon, 2017-09-18 at 11:13 +0100, Eric Engestrom wrote: > > > On Sunday, 2017-09-17 02:02:33 -0400, Jan Vesely wrote: > > > > v2: Use direct llvm repo link instead of alias > > >

Re: [Mesa-dev] [PATCH 3/3] Revert "gallium/radeon: consolidate PIPE_BIND_SHARED/SCANOUT handling"

On 09/29/2017 11:37 AM, Leo Liu wrote: On 09/29/2017 10:45 AM, Andy Furniss wrote: Marek Olšák wrote: Can you test this? My mpv test case is fixed by radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bb With Andy's information that this happens on newer MPV,

[Mesa-dev] [Bug 102463] SpaceEngine can't render main scenery properly

https://bugs.freedesktop.org/show_bug.cgi?id=102463 --- Comment #2 from Hi-Angel --- @Fabian Maurer on aside note I wanted to mention that it's your right to demand from the original author to get SpaceEngine working at least in Wine. The donations SpaceEngine got long time

[Mesa-dev] [PATCH 2/2] meson: change vulkan icd config to - instead of _

Just to be consistent. Signed-off-by: Dylan Baker --- meson_options.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meson_options.txt b/meson_options.txt index 082ade7f480..d0f7cc9c7ed 100644 --- a/meson_options.txt +++ b/meson_options.txt

[Mesa-dev] [PATCH 1/2] meson: check for python2 mako

Signed-off-by: Dylan Baker --- meson.build | 4 1 file changed, 4 insertions(+) diff --git a/meson.build b/meson.build index 5353a417484..add27b5dbac 100644 --- a/meson.build +++ b/meson.build @@ -53,6 +53,10 @@ if _vulkan_drivers != '' endif prog_python2 =

Re: [Mesa-dev] Using --enable-opencl-icd by default and deprecating the toggle

On Fri, Sep 29, 2017 at 10:14 AM, Emil Velikov wrote: > Hi all, > > Currently nearly all the distributions I've seen* enable and use the ICD. > Only Gentoo does not use it, but manages the OpenCL.so conflicts via eselect. > > They have the ocl-icd library as a separate

Re: [Mesa-dev] [PATCH 11/11] radeonsi: adjust clip discard based on line width / point size

For the series: Reviewed-by: Marek Olšák Marek On Fri, Sep 29, 2017 at 1:01 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > --- > src/gallium/drivers/radeonsi/si_state.c| 7 ++- >

Re: [Mesa-dev] [PATCH mesa] meson: fix version typo + grammar

I had this exact same change in my wip tree, Reviewed-by: Dylan Baker Quoting Eric Engestrom (2017-09-29 08:06:39) > Signed-off-by: Eric Engestrom > --- > meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [Mesa-dev] MESA and KOTOR

On 09/28/2017 11:25 AM, Federico Dossena wrote: Sorry if I insist on this again, but can someone who knows the internals of Mesa better than me please tell me which files implement pbuffers in gallium llvmpipe? Specifically, the parts that are involved in creating a pbuffer, its texture,

Re: [Mesa-dev] [PATCH] etnaviv: fix bogus flush requests in transfer handling

On Fri, Sep 29, 2017 at 03:40:11PM +0200, Lucas Stach wrote: > The logic to decide if we need to flush the GPU command stream was broken > and hard to reason about. Fix and clarify this. > > Fixes the data sync subtests from piglit arb_vertex_buffer_object. > > Signed-off-by: Lucas Stach

Re: [Mesa-dev] feature levels in clover (was: Re: [PATCH 2/2] clover: Query and export int64 atomics)

On Wed, 2017-09-27 at 11:25 -0700, Francisco Jerez wrote: > Jan Vesely writes: > > > On Tue, 2017-09-26 at 14:51 -0700, Francisco Jerez wrote: > > > Jan Vesely writes: > > > > > > > On Wed, 2017-09-20 at 19:10 -0500, Aaron Watry wrote: > > > > >

[Mesa-dev] [PATCH] etnaviv: Do GC3000 resolve-in-place when possible

If an RS blit is done with source exactly the same as destination, and the hardware supports this, do an in-place resolve. This is the same as the blob does and potentially saves significant bandwidth when doing i.MX6qp scanout using PRE, and when rendering to textures (though here using sampler

Re: [Mesa-dev] [PATCH 07/11] radeonsi: move and rename scissor and viewport state and functions

GET_MAX_SCISSOR(rctx) occurs twice where rctx doesn't exist. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 02/19] radv: do not allocate CMASK for unsupported 128 bit formats

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_image.c | 3 ++- src/amd/vulkan/radv_meta_clear.c | 5 - 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index

[Mesa-dev] [PATCH 11/19] radv: remove unused param in radv_handle_{cmask, dcc}_image_transition()

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f13979cc9e..f0c49f9ab4 100644 ---

[Mesa-dev] [PATCH 12/19] radv: add radv_attachment_needs_clear() helper

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 70 ++-- 1 file changed, 31 insertions(+), 39 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index

[Mesa-dev] [PATCH 19/19] radv: remove unused radv_meta_state::btoi::render_pass handle

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_private.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 6927942550..4a10af91ed 100644 --- a/src/amd/vulkan/radv_private.h +++

[Mesa-dev] [PATCH 15/19] radv: drop useless param in emit_depth_decomp()

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_decompress.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c index fedcfad3ae..ff5a8404cc 100644 ---

[Mesa-dev] [PATCH 16/19] radv: select the pipeline outside of emit_fast_clear_flush()

It can't change during the decompression pass. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_fast_clear.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/src/amd/vulkan/radv_meta_fast_clear.c

[Mesa-dev] [PATCH 05/19] radv: use pipeline handles instead of objects for meta clear operations

To be consistent with other meta operations. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 72 ++-- src/amd/vulkan/radv_private.h| 8 ++--- 2 files changed, 36 insertions(+), 44 deletions(-) diff --git

[Mesa-dev] [PATCH 18/19] radv: do not check the number of levels when doing fast htile

We shouldn't reach this point because HTILE is only enabled when the number of levels is 1. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c

[Mesa-dev] [PATCH 14/19] radv: drop useless check in depth_view_can_fast_clear()

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 458e2b8186..72efe4608e 100644 ---

[Mesa-dev] [PATCH 13/19] radv: add radv_subpass_clear_attachment() helper

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 52 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index

[Mesa-dev] [PATCH 09/19] radv: remove radv_layout_is_htile_compressed()

Similar to radv_layout_has_htile(). Also remove an assertion which was always false. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 12 +--- src/amd/vulkan/radv_image.c | 10 -- src/amd/vulkan/radv_meta_clear.c | 4 ++--

[Mesa-dev] [PATCH 04/19] radv: inline blit2d_unbind_dst()

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_blit2d.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c index 461d097d05..f7809b4486 100644 ---

[Mesa-dev] [PATCH 17/19] radv: cleanup radv_device_finish_meta_XXX() helpers

Unnecessary to double check that handles are not NULL. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_blit.c | 91 ++--- src/amd/vulkan/radv_meta_blit2d.c | 49 -- src/amd/vulkan/radv_meta_buffer.c

[Mesa-dev] [PATCH 08/19] radv: remove the resummarize decompress depth state

It's unused. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta.h| 3 -- src/amd/vulkan/radv_meta_decompress.c | 69 +-- src/amd/vulkan/radv_pipeline.c| 1 - src/amd/vulkan/radv_private.h | 2 - 4

[Mesa-dev] [PATCH 06/19] radv: inline destroy_render_pass()

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 9cb9506b81..8b3745d6d7 100644 ---

[Mesa-dev] [PATCH 10/19] radv: add radv_vi_dcc_enabled() helper

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 2 +- src/amd/vulkan/radv_image.c | 2 +- src/amd/vulkan/radv_private.h | 5 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH 01/19] radv: skip the decompression color pass when CMASK/FMASK/DCC are disabled

This should be a no-op. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_fast_clear.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index b92fb7cd5a..7e0738f44f 100644

[Mesa-dev] [PATCH 03/19] radv: rework DCC/CMASK/FMASK/HTILE allocations

Add helpers and some comments to make the thing more readable. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_image.c | 85 ++--- 1 file changed, 57 insertions(+), 28 deletions(-) diff --git

[Mesa-dev] [PATCH 07/19] radv: do not need to double zero-init the meta state structures

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_blit.c | 1 - src/amd/vulkan/radv_meta_blit2d.c | 2 -- src/amd/vulkan/radv_meta_buffer.c | 2 -- src/amd/vulkan/radv_meta_bufimage.c | 8 src/amd/vulkan/radv_meta_clear.c | 2 --

[Mesa-dev] [PATCH 00/19] radv: meta operations & decompression cleanups

Hi, After glancing at this code a lot, it appears that some cleanups are needed. I think it's also definitely possible to reduce the meta-related code, I have something in mind but not yet finished. Please review, Thanks! Samuel Pitoiset (19): radv: skip the decompression color pass when

Re: [Mesa-dev] [PATCH 05/11] radeonsi: move r600_viewport.c to si_viewport.c

si_state_viewport.c maybe? Marek On Fri, Sep 29, 2017 at 1:01 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > This is purely a file-move + #include fixup + build system changes. > Other cleanups will follow in subsequent commits. > --- >

Re: [Mesa-dev] [PATCH 3/3] Revert "gallium/radeon: consolidate PIPE_BIND_SHARED/SCANOUT handling"

On 09/29/2017 10:45 AM, Andy Furniss wrote: Marek Olšák wrote: Can you test this? My mpv test case is fixed by radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bb With Andy's information that this happens on newer MPV, and with Marek's fixes, we know MPV is

Re: [Mesa-dev] [PATCH 2/4] mesa/main: R10G10B10_(A2) formats are not color renderable in ES

On 29.09.2017 17:01, Marek Olšák wrote: I think it can still be renderable in desktop OpenGL. The function has an early exit for desktop OpenGL. Cheers, Nicolai Marek On Fri, Sep 29, 2017 at 1:30 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle

Re: [Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

I think it's kind of a pity that there's no "intermediate" step here - I think just about every modern driver doesn't want to see UARL / address reg, but I'd assume not everybody can use _any_ 1d reg for addressing. d3d10 only supports temp registers as addressing operands which looks quite

Re: [Mesa-dev] [PATCH 3/4] gallium: add PIPE_FORMAT_R10G10B10X2_UNORM

On 09/29/2017 05:30 AM, Nicolai Hähnle wrote: From: Nicolai Hähnle --- src/gallium/auxiliary/util/u_format.csv | 1 + src/gallium/auxiliary/util/u_format_tests.c | 6 ++ src/gallium/include/pipe/p_format.h | 2 ++ 3 files changed, 9 insertions(+)

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