[Mesa-dev] [PATCH] intel/common: Improve the comments for sample positions

These are pulled directly from brw_multisample_state.h --- src/intel/common/gen_sample_positions.h | 65 + 1 file changed, 65 insertions(+) diff --git a/src/intel/common/gen_sample_positions.h b/src/intel/common/gen_sample_positions.h index b86a7d8..f0ce95d

[Mesa-dev] [PATCH] anv: Get rid of gen fall-through

In the early days of the Vulkan driver, we thought it would be a good idea to just make genN just fall back to the genN-1 code if it didn't need to be any different for genN. While this seemed like a good idea, it ultimately ended up being far simpler to just recompile everything. We haven't been

[Mesa-dev] [PATCH v2 50/52] spirv: Rework barriers

Our previous handling of barriers always used the big hammer and didn't correctly emit memory barriers when specified along with a control barrier. This commit completely reworks the way we emit barriers to make things both more precise and more correct. --- src/compiler/spirv/spirv_to_nir.c |

[Mesa-dev] [PATCH v2 47/52] nir/lower_subgroups: Lower ballot intrinsics to the specified bit size

Ballot intrinsics return a bitfield of subgroups. In GLSL and some SPIR-V extensions, they return a uint64_t. In SPV_KHR_shader_ballot, they return a uvec4. Also, some back-ends would rather pass around 32-bit values because it's easier than messing with 64-bit all the time. To solve this mess,

[Mesa-dev] [PATCH v2 51/52] nir: Validate base types on array dereferences

We were already validating that the parent type goes along with the child type but we weren't actually validating that the parent type is reasonable. This fixes that. --- src/compiler/nir/nir_validate.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2 52/52] compiler/nir_types: Handle vectors in glsl_get_array_element

Most of NIR doesn't allow doing array indexing on a vector (though it does on a matrix). However, nir_lower_io handles it just fine and this behavior is needed for shared variables in Vulkan. This commit makes glsl_get_array_element do something sensible for vector types and makes nir_validate

[Mesa-dev] [PATCH v2 49/52] spirv: Add a vtn_constant_value helper

--- src/compiler/spirv/vtn_private.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h index 8458462..e7a7c36 100644 --- a/src/compiler/spirv/vtn_private.h +++ b/src/compiler/spirv/vtn_private.h @@ -557,6 +557,12 @@

[Mesa-dev] [PATCH v2 44/52] nir: Add a ssa_dest_init_for_type helper

This would be useful a number of places --- src/compiler/nir/nir.h | 9 + 1 file changed, 9 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 1154c42..17efc9b 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -2227,6 +2227,15 @@ void

[Mesa-dev] [PATCH v2 42/52] nir/opt_intrinsics: Rework progress

This commit fixes two issues: First, we were returning false regardless of whether or not the function made progress. Second, we were calling nir_metadata_preserve far more often than needed; we only need to call it once per impl. --- src/compiler/nir/nir_opt_intrinsics.c | 14 +- 1

[Mesa-dev] [PATCH v2 43/52] nir: Add a new subgroups lowering pass

This commit pulls nir_lower_read_invocations_to_scalar along with most of the guts of nir_opt_intrinsics (which mostly does subgroup lowering) into a new nir_lower_subgroups pass. There are various other bits of subgroup lowering that we're going to want to do so it makes a bit more sense to keep

[Mesa-dev] [PATCH v2 48/52] nir, intel/compiler: Use a fixed subgroup size

The GL_ARB_shader_ballot spec says that gl_SubGroupSizeARB is declared as a uniform. This means that it cannot change across an invocation such as a draw call or a compute dispatch. For compute shaders, we're ok because we only ever use one dispatch size. For fragment, however, the hardware

[Mesa-dev] [PATCH v2 46/52] nir/lower_system_values: Lower SUBGROUP_*_MASK based on type

The SUBGROUP_*_MASK system values are uint64_t when coming in from GLSL but uvec4 when coming in from SPIR-V. Lowering based on type allows us to nicely handle both. --- src/compiler/nir/nir_lower_system_values.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2 39/52] nir/lower_wpos_ytransform: Support system value intrinsics

--- src/compiler/nir/nir_lower_wpos_ytransform.c | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_lower_wpos_ytransform.c b/src/compiler/nir/nir_lower_wpos_ytransform.c index 771c6ff..425e4b8 100644 --- a/src/compiler/nir/nir_lower_wpos_ytransform.c +++

[Mesa-dev] [PATCH v2 40/52] i965/program: Move nir_lower_system_values higher up

We want this to get called before nir_lower_subgroups which is going in brw_preprocess_nir. Now that nir_lower_wpos_ytransform can handle system values, this should be safe to do. --- src/mesa/drivers/dri/i965/brw_program.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH v2 45/52] nir: Make ballot intrinsics variable-size

This way they can return either a uvec4 or a uint64_t. At the moment, this is a no-op since we still always return a uint64_t. --- src/compiler/glsl/glsl_to_nir.cpp | 1 + src/compiler/nir/nir_intrinsics.h | 12 ++-- src/compiler/nir/nir_lower_system_values.c | 1 + 3

[Mesa-dev] [PATCH v2 41/52] intel/compiler: Call nir_lower_system_values in brw_preprocess_nir

--- src/intel/compiler/brw_nir.c| 2 ++ src/intel/vulkan/anv_pipeline.c | 2 -- src/mesa/drivers/dri/i965/brw_program.c | 2 -- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index a04f4af..0a41768

[Mesa-dev] [PATCH v2 38/52] anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir

We currently have a bug where nir_lower_system_values gets called before nir_lower_var_copies so it will miss any system value uses which come from a copy_var intrinsic. Moving it to after brw_preprocess_nir fixes this problem. Cc: mesa-sta...@lists.freedesktop.org ---

[Mesa-dev] [PATCH v2 33/52] intel/eu: Explicitly set EXECUTE_1 where needed

--- src/intel/compiler/brw_eu_emit.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 679832a..0146770 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -1896,6 +1896,7 @@

[Mesa-dev] [PATCH v2 35/52] intel/fs: Don't use automatic exec size inference

The automatic exec size inference can accidentally mess things up if we're not careful. For instance, if we have add(4)g38.2<4>Dg38.1<8,2,4>Dg38.2<8,2,4>D then the destination register will end up having a width of 2 with a horizontal stride of 4 and a vertical stride of 8. The EU

[Mesa-dev] [PATCH v2 34/52] intel/fs: Explicitly set EXECUTE_1 where needed

--- src/intel/compiler/brw_fs.cpp | 2 +- src/intel/compiler/brw_fs_generator.cpp | 7 +++ src/intel/compiler/brw_fs_nir.cpp | 8 src/intel/compiler/brw_fs_visitor.cpp | 7 +++ 4 files changed, 15 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [PATCH v2 37/52] anv/pipeline: Drop nir_lower_clip_cull_distance_arrays

We already handle it in brw_preprocess_nir --- src/intel/vulkan/anv_pipeline.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index e08bdd9..9645d68 100644 --- a/src/intel/vulkan/anv_pipeline.c +++

[Mesa-dev] [PATCH v2 28/52] intel/cs: Push subgroup ID instead of base thread ID

We're going to want subgroup ID for SPIR-V subgroups eventually anyway. We really only want to push one and calculate the other from it. It makes a bit more sense to push the subgroup ID because it's simpler to calculate and because it's a real API thing. The only advantage to pushing the base

[Mesa-dev] [PATCH v2 36/52] anv/pipeline: Dump shader immedately after spirv_to_nir

--- src/intel/vulkan/anv_pipeline.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 7bfdb5c..e08bdd9 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -83,6 +83,15 @@

[Mesa-dev] [PATCH v2 29/52] intel/compiler/fs: Set up subgroup invocation as a system value

Subgroup invocation is computed using a vector immediate and some dispatch-aware arithmetic. Unfortunately, due to the vector arithmetic, and the fact that it's frequently read 16-wide, it's not something that can easily be CSEd by the back-end compiler. There are a few different possible

[Mesa-dev] [PATCH v2 32/52] intel/eu: Make automatic exec sizes a configurable option

We have had a feature in codegen for some time that tries to automatically infer the execution size of an instruction from the width of its destination. For things such as fixed function GS, clipper, and SF programs, this is very useful because they tend to have lots of hand-rolled register setup

[Mesa-dev] [PATCH v2 27/52] intel/cs: Re-run final NIR optimizations for each SIMD size

With the advent of SPIR-V subgroup operations, compute shaders will have to be slightly different depending on the SIMD size at which they execute. In order to allow us to do dispatch-width specific things in NIR, we re-run the final NIR stages for each sIMD width. As a side-effect of this

[Mesa-dev] [PATCH v2 30/52] intel/fs: Rework zero-length URB write handling

Originally we tried to handle this case based on slots_valid. However, there are a number of ways that this can go wrong. For one, we throw away any trailing slots which either aren't written or are set to VARYING_SLOT_PAD. Second, even if PSIZ is a valid slot, we may not actually write

[Mesa-dev] [PATCH v2 21/52] intel/cs: Drop min_dispatch_width checks from compile_cs

The only things that adjust min_dispatch_width are render target writes which don't happen in compute shaders so they're pointless. --- src/intel/compiler/brw_fs.cpp | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp

[Mesa-dev] [PATCH v2 31/52] intel/eu: Use EXECUTE_1 for JMPI

The PRM says "The execution size must be 1." In 73137997e23ff6c11, the execution size was set to 1 when it should have been BRW_EXECUTE_1 (which maps to 0). Later, in dc2d3a7f5c217a7cee9, JMPI was used for line AA on gen6 and earlier and we started manually stomping the exeution size to

[Mesa-dev] [PATCH v2 23/52] intel/cs: Ignore runtime_check_aads_emit for CS

It's only set on gen4-5 which clearly don't support compute shaders. --- src/intel/compiler/brw_fs.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 78998fd..385f500 100644 ---

[Mesa-dev] [PATCH v2 25/52] intel/cs: Rework the way thread local ID is handled

Previously, brw_nir_lower_intrinsics added the param and then emitted a load_uniform intrinsic to load it directly. This commit switches things over to use a specific NIR intrinsic for the thread id. The one thing I don't like about this approach is that we have to copy thread_local_id over to

[Mesa-dev] [PATCH v2 22/52] intel/cs: Stop setting dispatch_grf_start_reg

Nothing ever reads it for compute shaders because it's always 1. --- src/intel/compiler/brw_compiler.h | 1 - src/intel/compiler/brw_fs.cpp | 2 -- 2 files changed, 3 deletions(-) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 014202d..508d4ba

[Mesa-dev] [PATCH v2 24/52] intel/fs: Mark 64-bit values as being contiguous

This isn't often a problem , when we're in a compute shader, we must push the thread local ID so we decrement the amount of available push space by 1 and it's no longer even and 64-bit data can, in theory, span it. By marking those uniforms contiguous, we ensure that they never get split in half

[Mesa-dev] [PATCH v2 13/52] i965/fs: Return a fs_reg from shuffle_64bit_data_for_32bit_write

All callers of this function allocate a fs_reg expressly to pass into it. It's much easier if we just let the helper allocate the register. While we're here, we switch it to doing the MOVs with an integer type so that we don't accidentally canonicalize floats on half of a double. ---

[Mesa-dev] [PATCH v2 17/52] intel/fs: Uniformize the index in readInvocation

The index is any value provided by the shader and this can be called in non-uniform control flow so we can't just take component 0. Found by inspection. --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp

[Mesa-dev] [PATCH v2 19/52] intel/fs: Assign constant locations if they haven't been assigned

Before, we bailing in assign_constant_locations based on the minimum dispatch size. The more direct thing to do is simply to check for whether or not we have constant locations and bail if we do. For nir_setup_uniforms, it's completely safe to do it multiple times because we just copy a value

[Mesa-dev] [PATCH v2 16/52] intel/fs: Protect opt_algebraic from OOB BROADCAST indices

--- src/intel/compiler/brw_fs.cpp | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index c72ed17..e96b077 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -2422,8 +2422,14

[Mesa-dev] [PATCH v2 20/52] intel/fs: Remove min_dispatch_width from fs_visitor

It's 8 for everything except compute shaders. For compute shaders, there's no need to duplicate the computation and it's just a possible source of error. --- src/intel/compiler/brw_fs.cpp | 42 +++ src/intel/compiler/brw_fs.h | 5 ++---

[Mesa-dev] [PATCH v2 18/52] intel/fs: Retype dest to match value in read[First]Invocation

This is what we really wanted all along. Always retyping to D works because that's what get_nir_src() always gives us, at least for 32-bit types. The SPIR-V variants of these operations accept arbitrary types and we need this if we're going to handle 64 or 16-bit values. ---

[Mesa-dev] [PATCH v2 26/52] intel/cs: Re-run final NIR optimizations for each SIMD size

With the advent of SPIR-V subgroup operations, compute shaders will have to be slightly different depending on the SIMD size at which they execute. In order to allow us to do dispatch-width specific things in NIR, we re-run the final NIR stages for each sIMD width. One side-effect of this change

[Mesa-dev] [PATCH v2 14/52] i965/fs/nir: Minor refactor of store_output

Stop retyping the output of shuffle_64bit_data_for_32bit_write. It's always BRW_REGISTER_TYPE_D which is perfectly fine for writing out. Also, when we change get_nir_src to return something with a 64-bit type for 64-bit values, the retyping will not be at all what we want. Also, retyping the

[Mesa-dev] [PATCH v2 10/52] i965/fs/nir: Use the nir_src_bit_size helper

Reviewed-by: Lionel Landwerlin --- src/intel/compiler/brw_fs_nir.cpp | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index e331637..35a9828 100644 ---

[Mesa-dev] [PATCH v2 15/52] i965/fs/nir: Don't stomp 64-bit values to D in get_nir_src

--- src/intel/compiler/brw_fs_nir.cpp | 33 + 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 138d292..653d6d8 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH v2 08/52] i965/fs: Extend the live ranges of VGRFs which leave loops

No Shader-db changes. Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_fs_live_variables.cpp | 55 1 file changed, 55 insertions(+) diff --git a/src/intel/compiler/brw_fs_live_variables.cpp b/src/intel/compiler/brw_fs_live_variables.cpp index

[Mesa-dev] [PATCH v2 01/52] intel/fs: Pass builders instead of blocks into emit_[un]zip

This makes it far more explicit where we're inserting the instructions rather than the magic "before and after" stuff that the emit_[un]zip helpers did based on block and inst. Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_fs.cpp | 50

[Mesa-dev] [PATCH v2 06/52] intel/fs: Use an explicit D type for vote any/all/eq intrinsics

They return a boolean so this is the right type. Unfortunately, get_nir_dest has the annoying behavior of giving us a float type by default. This is mostly to work around the fact that gen7 has 64-bit float but no Q types. Cc: mesa-sta...@lists.freedesktop.org ---

[Mesa-dev] [PATCH v2 11/52] i965/fs: Add brw_reg_type_from_bit_size utility method

From: Alejandro Piñeiro Returns the brw_type for a given ssa.bit_size, and a reference type. So if bit_size is 64, and the reference type is BRW_REGISTER_TYPE_F, it returns BRW_REGISTER_TYPE_DF. The same applies if bit_size is 32 and reference type is BRW_REGISTER_TYPE_HF

[Mesa-dev] [PATCH v2 07/52] intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all

For some reason, the any/all predicates don't work properly with SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H doesn't read the correct subset of the flag register and you end up getting garbage in the second half. Work around this by using a pair of 1-wide MOVs and scattering

[Mesa-dev] [PATCH v2 03/52] intel/fs: Handle flag read/write aliasing in needs_src_copy

In order to implement the ballot intrinsic, we do a MOV from flag register to some GRF. If that GRF is used in a SEL, cmod propagation helpfully changes it into a MOV from the flag register with a cmod. This is perfectly valid but when lower_simd_width comes along, it simply splits into two

[Mesa-dev] [PATCH v2 12/52] i965/fs/nir: Simplify 64-bit store_output

The swizzles weren't doing any good because swiz is just XYZW. Also, we were emitting an extra set of MOVs because shuffle_64bit_data_for_32bit already does a MOV for us. Finally, the temporary was only ever used inside the inner loop so there's no need for it to actually be an array. ---

[Mesa-dev] [PATCH v2 02/52] intel/fs: Be more explicit about our placement of [un]zip

Before, we were careful to place the zip after the last of the split instructions but did unzip on-demand. This changes things so that the unzips go before all of the split instructions and the unzip comes explicitly after all the split instructions. As a side-effect of this change, we now emit

[Mesa-dev] [PATCH v2 05/52] intel/fs: Don't stomp f0.1 in SIMD16 ballot

In fragment shaders f0.1 is used for discards so doing ballot after a discard can potentially cause the discard to not happen. Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_fs_nir.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2 04/52] intel/fs: Use ANY/ALL32 predicates in SIMD32

We have ANY/ALL32 predicates and, for the most part, they work just fine. (See the next commit for more details.) Also, due to the way that flag registers are handled in hardware, instruction splitting is able to split the CMP correctly. Specifically, that hardware looks at the execution group

[Mesa-dev] [PATCH v2 09/52] intel/fs: Restrict live intervals to the subset possibly reachable from any definition.

From: Francisco Jerez Currently the liveness analysis pass would extend a live interval up to the top of the program when no unconditional and complete definition of the variable is found that dominates all of its uses. This can lead to a serious performance problem in

[Mesa-dev] [PATCH v2 00/52] nir, intel: Prerequisites for subgroups

A little over a month ago, I sent a 44 patch series with a bunch of the prerequisite patches for implementing SPIR-V subgroup support. This is a re-spin of that series with a few more patches. Most of the new fixes are either because of rebasing on top of my uniform reworks or are fixes for

[Mesa-dev] [AppVeyor] mesa master #5788 failed

Build mesa 5788 failed Commit b8ab78d1af by Jason Ekstrand on 10/11/2017 7:13 PM: anv/pipeline_cache: Rework to use multialloc and blob\n\nThis gets rid of all of our hand-rolled size calculation and\nserialization code and replaces it with safe "standards"

Re: [Mesa-dev] [PATCH 08/11] compiler/blob: Make some parameters void instead of uint8_t

On Wed, Oct 11, 2017 at 11:26 PM, Nicolai Hähnle wrote: > I've sent some minor comments on patches #3, #5, and #6. Also, spot the > typo in the title of patch #4 :) > > With those addressed, patches 1-8 are: > > Reviewed-by: Nicolai Hähnle > Thanks!

Re: [Mesa-dev] [PATCH 03/11] compiler: Move blob up a level

On Thu, Oct 12, 2017 at 3:27 PM, Jordan Justen wrote: > Didn't you have the same patch written by Connor in your nir-serialize > series? :) > Yes. but I didn't figure "move some files" was worth cherry-picking. Besides, mine now has meson fixes. :P --Jason >

Re: [Mesa-dev] [PATCH 03/11] compiler: Move blob up a level

On Wed, Oct 11, 2017 at 11:21 PM, Nicolai Hähnle wrote: > On 11.10.2017 22:38, Jason Ekstrand wrote: > >> We're going to want to use the blob for Vulkan pipeline caching so it >> makes sense to have it in libcompiler not libglsl. >> --- >> src/compiler/Makefile.sources

Re: [Mesa-dev] [PATCH 00/11] anv: Convert the pipeline cache to use blob

On Thu, Oct 12, 2017 at 5:52 PM, Jordan Justen wrote: > I think my requests to split 2 patches should be pretty easy, so even > with those changes: > > Series Reviewed-by: Jordan Justen > Thanks! > On 2017-10-11 13:38:40, Jason Ekstrand

Re: [Mesa-dev] [PATCH] mesa/bufferobj: fix atomic offset/size get

On 10/12/2017 11:14 PM, Dave Airlie wrote: On 12 October 2017 at 18:22, Tapani Pälli wrote: On 10/12/2017 11:14 AM, Dave Airlie wrote: On 12 Oct. 2017 15:40, "Tapani Pälli" > wrote: On 10/12/2017

Re: [Mesa-dev] [PATCH 00/11] anv: Convert the pipeline cache to use blob

I think my requests to split 2 patches should be pretty easy, so even with those changes: Series Reviewed-by: Jordan Justen On 2017-10-11 13:38:40, Jason Ekstrand wrote: > I started trying to debug a random segfault in the pipeline cache that I > was seeing in some of

Re: [Mesa-dev] [PATCH] include: Revert out the update of the Khronos GLX extension header.

Tested-by: Mark Janes Reviewed-by: Mark Janes I'd like to get this pushed right away, because Mesa CI is basically offline due to the subsequent build failures. Eric Anholt writes: > They made a mistake in the MESA_swap_control

Re: [Mesa-dev] [PATCH] i965: Fix src0 vs src1 typo

On Tue, Oct 10, 2017 at 4:43 AM, Eero Tamminen wrote: > Hi, > > On 03.10.2017 08:20, Matt Turner wrote: >> >> A typo caused us to copy src0's reg file to src1 rather than reading >> src1's as intended. This caused us to fail to compact instructions like >> >> mov(8)

Re: [Mesa-dev] [PATCH 00/21] intel/compiler: Rework the world of push/pull params

On Friday, October 6, 2017 10:27:02 AM PDT Jordan Justen wrote: > Series Reviewed-by: Jordan Justen > > Although, I think you said you might rewrite patch 13 (the > thread_local_id_index patch). If you just add the small stage check I > mentioned then you can add my

Re: [Mesa-dev] [PATCH 15/21] anv/pipeline: Whack nir->num_uniforms to MAX_PUSH_CONSTANT_SIZE

On Friday, September 29, 2017 2:25:15 PM PDT Jason Ekstrand wrote: > This way any image uniforms end up having locations higher than > MAX_PUSH_CONSTANT_SIZE. There's no bug here at the moment, but this > consistency will make the next commit easier. Also, because > nir_apply_pipeline_layout

Re: [Mesa-dev] [PATCH 2/3] meta: Unset the textures_used_by_txf bitfield.

On Wed, Oct 11, 2017 at 12:15 PM, Kenneth Graunke wrote: > Drivers that use Meta are happily using blitting data using texelFetch > and GL_SKIP_DECODE_EXT, but the GL_EXT_texture_sRGB spec unfortunately > makes GL_SKIP_DECODE_EXT not necessarily work with texelFetch. > >

Re: [Mesa-dev] [PATCH 06/11] compiler/blob: make blob_reserve_bytes() more useful

On 2017-10-11 13:38:46, Jason Ekstrand wrote: > From: Connor Abbott > > Despite the name, it could only be used if you immediately wrote to the > pointer. Noboby was using it outside of one test, so clearly this > behavior wasn't that useful. Instead, make it return an

Re: [Mesa-dev] [PATCH 05/11] compiler/blob: Add a concept of a fixed-allocation blob

I think the commit message should include something like: With a fixed allocation blob, the data buffer is managed by the caller, and can't be grown by blob writes. I also think it'd be better to add the NULL fixed allocation blob support in a separate patch. (It looks like the real motivation

Re: [Mesa-dev] [PATCH v2 17/21] meson: build nouveau (gallium) driver

Quoting Eric Anholt (2017-10-12 15:33:43) > Dylan Baker writes: > > > [ Unknown signature status ] > > Quoting Eric Anholt (2017-10-12 12:47:19) > >> Dylan Baker writes: > >> > >> > Tested with a GK107. > >> > > >> > v2: - Add target for nouveau

Re: [Mesa-dev] [PATCH 2/4] radv: update ia_multi_vgt when executing secondary buffers

Why don't we use the approach from patch 3 for this? Otherwise the series is r-b? On Wed, Oct 11, 2017 at 10:25 AM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 1 + > 1 file changed, 1

[Mesa-dev] [PATCH] include: Revert out the update of the Khronos GLX extension header.

They made a mistake in the MESA_swap_control XML, which I'm pursuing in their github. Until then, we can just back this piece out. --- include/GL/glxext.h | 12 +--- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/include/GL/glxext.h b/include/GL/glxext.h index

Re: [Mesa-dev] [PATCH] radv: do not allocate CMASK for non-MSSA images with 128 bit formats

r-b On Thu, Oct 12, 2017 at 4:55 PM, Samuel Pitoiset wrote: > This saves some useless CMASK initializations/eliminations in > the Vulkan SSAO demo. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 2 +- >

Re: [Mesa-dev] [PATCH v2 4/11] compiler/blob: Switch to init/finsih instead of create/destroy

Typo 'finsih' in subject. On 2017-10-11 13:52:17, Jason Ekstrand wrote: > > /** > * Destroy a blob and free its memory. Function comment needs an update. -Jordan > */ > static inline void > -blob_destroy(struct blob *blob) > +blob_finish(struct blob *blob) > { > free(blob->data);

Re: [Mesa-dev] [PATCH v2 17/21] meson: build nouveau (gallium) driver

Dylan Baker writes: > [ Unknown signature status ] > Quoting Eric Anholt (2017-10-12 12:47:19) >> Dylan Baker writes: >> >> > Tested with a GK107. >> > >> > v2: - Add target for nouveau standalone compiler. This target is not >> > built by

Re: [Mesa-dev] [PATCH v2 18/21] meson: build softpipe

Dylan Baker writes: > [ Unknown signature status ] > Quoting Eric Anholt (2017-10-12 12:27:21) >> Dylan Baker writes: >> >> > This doesn't include llvmpipe. >> > >> > v2: - Fix inconsistent use of with_gallium_swrast and >> >

Re: [Mesa-dev] [PATCH 03/11] compiler: Move blob up a level

Didn't you have the same patch written by Connor in your nir-serialize series? :) -Jordan On 2017-10-11 13:38:43, Jason Ekstrand wrote: > We're going to want to use the blob for Vulkan pipeline caching so it > makes sense to have it in libcompiler not libglsl. > --- >

Re: [Mesa-dev] Mesa 17.3.0 release plan

Hi Emil 2017-10-12 15:47 GMT+02:00 Emil Velikov : > Hi all, > > As you've know the Mesa 17.3.0 release plan has been available for a while > on the mesa3d.org website [1]. > > In case you've missed it here it is: > > Oct 20 2017 - Feature freeze/Release candidate 1 >

Re: [Mesa-dev] [PATCH v2 18/21] meson: build softpipe

Quoting Eric Anholt (2017-10-12 12:27:21) > Dylan Baker writes: > > > This doesn't include llvmpipe. > > > > v2: - Fix inconsistent use of with_gallium_swrast and > > with_gallium_softpipe. > > > > Signed-off-by: Dylan Baker > > --- > > >

Re: [Mesa-dev] [PATCH v2 17/21] meson: build nouveau (gallium) driver

Quoting Eric Anholt (2017-10-12 12:47:19) > Dylan Baker writes: > > > Tested with a GK107. > > > > v2: - Add target for nouveau standalone compiler. This target is not > > built by default. > > Looks like this missed the update of meson_options.txt. I configured it

Re: [Mesa-dev] [PATCH v2 10/21] meson: split and simplify depdendncies

Quoting Eric Anholt (2017-10-12 12:23:19) > Dylan Baker writes: > > > Rather than group dependencies in complex groups, use a flatter > > structure with split dependencies to avoid checking for the same > > dependencies twice. > > meson's going to be caching the dependency

[Mesa-dev] [PATCH] radv: do not allocate CMASK for non-MSSA images with 128 bit formats

This saves some useless CMASK initializations/eliminations in the Vulkan SSAO demo. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_image.c | 8 src/amd/vulkan/radv_meta_clear.c | 5 - 3 files changed,

Re: [Mesa-dev] [PATCH 2/2] meson: Build i915

Both patches are: Reviewed-by: Dylan Baker Quoting Ville Syrjala (2017-10-12 09:34:55) > From: Ville Syrjälä > > Build i915 with meson. More or less copied from i965, with all > the unneeded cruft removed, and the libdrm_intel dependency

Re: [Mesa-dev] [PATCH] mesa: Disallow GL_RED/GL_RG with half-floats on GLES2.

Tested-by: Mark Janes Eric Anholt writes: > Sure, you'd think that the combination of GL_OES_texture_half_float and > GL_EXT_texture_rg would mean that GL_RG16F exists, but it doesn't. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103227 >

Re: [Mesa-dev] [PATCH] mesa/bufferobj: fix atomic offset/size get

On 12 October 2017 at 18:22, Tapani Pälli wrote: > > > On 10/12/2017 11:14 AM, Dave Airlie wrote: >> >> >> On 12 Oct. 2017 15:40, "Tapani Pälli" > > wrote: >> >> >> >> On 10/12/2017 02:34 AM, Dave Airlie wrote: >>

Re: [Mesa-dev] [PATCH v2 17/21] meson: build nouveau (gallium) driver

Dylan Baker writes: > Tested with a GK107. > > v2: - Add target for nouveau standalone compiler. This target is not > built by default. Looks like this missed the update of meson_options.txt. signature.asc Description: PGP signature

Re: [Mesa-dev] [PATCH v2 18/21] meson: build softpipe

Dylan Baker writes: > This doesn't include llvmpipe. > > v2: - Fix inconsistent use of with_gallium_swrast and > with_gallium_softpipe. > > Signed-off-by: Dylan Baker > --- > diff --git a/meson_options.txt b/meson_options.txt > index

Re: [Mesa-dev] [PATCH v2 10/21] meson: split and simplify depdendncies

Dylan Baker writes: > Rather than group dependencies in complex groups, use a flatter > structure with split dependencies to avoid checking for the same > dependencies twice. meson's going to be caching the dependency checks in the future, so I wouldn't go out of your way

[Mesa-dev] CI for Android builds

I've made some improvements to my mesa Android CI job[1]. Previously, it just built using master twice a day and only emailed me. Now anyone (with commit rights) can push to mesa branches master or android/* and it will trigger a build emailing the last commit's author/committer on failure. It's

Re: [Mesa-dev] [PATCH v2 07/21] meson: Add option to toggle LLVM

Dylan Baker writes: > Signed-off-by: Dylan Baker 5-7 are Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH 15/20] meson: build radeonsi gallium driver

Dylan Baker writes: > This hooks up the bits necessary to build gallium dri drivers, with > radeonSI as the first example driver. This isn't tested yet. > --- > src/gallium/meson.build | 3 +- > src/gallium/targets/dri/meson.build | 90 >

Re: [Mesa-dev] [PATCH 09/20] meson: split and simplify depdendncies

Dylan Baker writes: > Rather than group dependencies in complex groups, use a flatter > structure with split dependencies to avoid checking for the same > dependencies twice. In the subject: *dependencies* signature.asc Description: PGP signature

[Mesa-dev] [PATCH v3 40/43] i965/fs: Use untyped_surface_read for 16-bit load_ssbo

SSBO loads were using byte_scattered read messages as they allow reading 16-bit size components. byte_scattered messages can only operate one component at a time so we needed to emit as many messages as components. But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the

[Mesa-dev] [PATCH v3 42/43] anv: Enable SPV_KHR_16bit_storage on gen 8+

From: Eduardo Lima Mitev v2: minor changes after rebase against recent master (Alejandro) --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index b35bad1050..82ed4ecc1d

[Mesa-dev] [PATCH v3 41/43] i965/fs: Predicate byte scattered writes if needed

From: Alejandro Piñeiro While on Untyped Surface messages the bits of the execution mask are ANDed with the corresponding bits of the Pixel/Sample Mask, that is not the case for byte scattered writes. That is needed to avoid ssbo stores writing on helper invocations. So

[Mesa-dev] [PATCH v3 39/43] i965/fs: Enables 16-bit load_ubo with sampler

load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit surface format defined. So when reading 16-bit components with the sampler we need to unshuffle two 16-bit components from each 32-bit component. Using the sampler avoids the use of the byte_scattered_read message that needs one

[Mesa-dev] [PATCH v3 43/43] anv: Enable VK_KHR_16bit_storage

From: Alejandro Piñeiro It uses VK_KHR_get_physical_device_properties2 functionality to expose if the extension is supported or not. v2: update due rebase against master (Alejandro) Signed-off-by: Jose Maria Casanova Crespo Signed-off-by: Alejandro

[Mesa-dev] [PATCH v3 38/43] i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg

From: Eduardo Lima Mitev Currently, we use byte-scattered write messages for storing 16-bit into an SSBO. This is because untyped surface messages have a fixed 32-bit size. This patch optimizes these 16-bit writes by combining 2 values (e.g, two consecutive components) into a

[Mesa-dev] [PATCH v3 37/43] i965/fs: Enable 16-bit render target write on SKL and CHV

Once the infrastruture to support Render Target Messages with 16-bit payload is available, this patch enables it on SKL and CHV platforms. Enabling it allows 16-bit payload that use half of the register on SIMD16 and avoids the spurious conversion from 16-bit to 32-bit needed on BDW, just to be

[Mesa-dev] [PATCH v3 30/43] i965/fs: Support 16-bit types at load_input and store_output

Enables the support of 16-bit types on load_input and store_outputs intrinsics intra-stages. The approach was based on re-using the 32-bit URB read and writes between stages, shuffling pairs of 16-bit values into 32-bit values at load_store intrinsic and un-shuffling the values at load_inputs.

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