Re: [Mesa-dev] [RFC] r600/evergreen compute shader + glsl 4.30 support

On 30 November 2017 at 17:20, Gert Wollny wrote: > Am Donnerstag, den 30.11.2017, 09:30 +1000 schrieb Dave Airlie: >> On 29 November 2017 at 22:46, Gert Wollny >> wrote: >> > >> > >> > I run the arb_compute_shader piglits on BARTS, the piglits >> > >> >basic-texelfetch >> >border-color >>

Re: [Mesa-dev] [RFC] r600/evergreen compute shader + glsl 4.30 support

Am Donnerstag, den 30.11.2017, 09:30 +1000 schrieb Dave Airlie: > On 29 November 2017 at 22:46, Gert Wollny > wrote: > > > > > > I run the arb_compute_shader piglits on BARTS, the piglits > > > >    basic-texelfetch > >    border-color > >    multiple-workgroups > >    basic-uniform-access > >

Re: [Mesa-dev] [PATCH] intel/isl: Declare private array as static const

Reviewed-by: Tapani Pälli On 11/29/2017 09:10 PM, Chad Versace wrote: It's array isl_drm.c:modifier_info[] . --- src/intel/isl/isl_drm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c index eb3c6f59138..31895e15e16 100644

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On 11/29/2017 01:10 PM, Rob Clark wrote: On Wed, Nov 29, 2017 at 12:33 PM, Jason Ekstrand wrote: On Sat, Nov 25, 2017 at 1:20 PM, Rob Clark wrote: On Sat, Nov 25, 2017 at 12:46 PM, Jason Ekstrand wrote: On November 24, 2017 09:29:43 Rob Clark wrote: On Mon, Nov 20, 2017 at 8:11 PM, Jam

Re: [Mesa-dev] [PATCH] egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

On 11/30/2017 06:13 AM, Tomasz Figa wrote: On Thu, Nov 30, 2017 at 3:43 AM, Robert Foss wrote: Hey, On Tue, 2017-11-28 at 11:49 +, Emil Velikov wrote: On 28 November 2017 at 10:45, Tapani Pälli wrote: Hi; On 11/27/2017 04:14 PM, Robert Foss wrote: From: Tomasz Figa There is no A

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On 11/29/2017 04:09 PM, Miguel Angel Vico wrote: On Wed, 29 Nov 2017 16:28:15 -0500 Rob Clark wrote: On Wed, Nov 29, 2017 at 2:41 PM, Miguel Angel Vico wrote: Many of you may already know, but James is going to be out for a few weeks and I'll be taking over this in the meantime. Sorry fo

Re: [Mesa-dev] V2 Initial GS NIR support for radeonsi

On 30/11/17 14:00, Dieter Nützel wrote: Hello Timo, do you have a V3 handy...? ;-) I haven't run piglit yet after rebasing so run at your own risk. https://github.com/tarceri/Mesa.git radeonsi_nir_final Greetings, Dieter Am 23.11.2017 06:31, schrieb Timothy Arceri: On 23/11/17 15:09, Di

Re: [Mesa-dev] [PATCH] radv: do not allocate CMASK or DCC for small surfaces

Tested-by: Dieter Nützel on RX580 with F1 2017 Dieter Am 29.11.2017 14:48, schrieb Samuel Pitoiset: The idea is ported from RadeonSI, but using 512x512 instead of 256x256 seems slightly better. This improves dota2 performance by +2%. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_

Re: [Mesa-dev] [RFC] r600/evergreen compute shader + glsl 4.30 support

On 29 November 2017 at 14:36, Dave Airlie wrote: > This set of patches enables compute shaders on r600 and exposes GLSL 4.30 > support. They are pretty alpha level, but I'd like to land some of them > (maybe disabled) so I can avoid the rebasing fun with the more intrusive > ones. > > It is based

Re: [Mesa-dev] [PATCH] egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

On Thu, Nov 30, 2017 at 3:43 AM, Robert Foss wrote: > Hey, > > On Tue, 2017-11-28 at 11:49 +, Emil Velikov wrote: >> On 28 November 2017 at 10:45, Tapani Pälli >> wrote: >> > Hi; >> > >> > >> > On 11/27/2017 04:14 PM, Robert Foss wrote: >> > > >> > > From: Tomasz Figa >> > > >> > > There is

Re: [Mesa-dev] V2 Initial GS NIR support for radeonsi

Hello Timo, do you have a V3 handy...? ;-) Greetings, Dieter Am 23.11.2017 06:31, schrieb Timothy Arceri: On 23/11/17 15:09, Dieter Nützel wrote: Am 22.11.2017 10:29, schrieb Timothy Arceri: This series depends on [1] and [2]. V2  - use driver_location as per Nicolais suggestion  - tidy ups

[Mesa-dev] [PATCH v4 41/44] i965/fs: Use half_precision data_format on 16-bit fb writes

From: Alejandro Piñeiro --- src/intel/compiler/brw_fs_visitor.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 481d9c51e7..01e75ff7fc 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/int

[Mesa-dev] [PATCH v4 44/44] anv: Enable VK_KHR_16bit_storage for push_constant

Enables storagePushConstant16 feature of VK_KHR_16bit_storage for Gen8+. --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 26c0ace1ca..5b6032d794 100644 --- a/src/intel/vulkan/an

[Mesa-dev] [PATCH v4 42/44] i965/fs: Enable 16-bit render target write on SKL and CHV

Once the infrastruture to support Render Target Messages with 16-bit payload is available, this patch enables it on SKL and CHV platforms. Enabling it allows 16-bit payload that use half of the register on SIMD16 and avoids the spurious conversion from 16-bit to 32-bit needed on BDW, just to be co

[Mesa-dev] [PATCH v4 43/44] i965/fs: Support push constants of 16-bit types

We enable the use of 16-bit values in push constants modifying the assign_constant_locations function to work with 16-bit types. The API to access buffers in Vulkan use multiples of 4-byte for offsets and sizes. Current accountability of uniforms based on 4-byte slots will work for 16-bit values i

[Mesa-dev] [PATCH v4 39/44] i965/fs: Mark 16-bit outputs on FS store_output

On SKL the render target write operations allow 16-bit format output. This marks output registers as 16-bit using BRW_REGISTER_TYPE_HF on the proper outputs target. This allows to recognise when the data_format of 16-bit should be enabled on render_target_write messages. Signed-off-by: Jose Maria

[Mesa-dev] [PATCH v4 40/44] i965/fs: 16-bit source payloads always use 1 register

Render Target Message's payloads for 16bit values fit in only one register. From Intel PRM vol07, page 249 "Render Target Messages" / "Message Data Payloads" "The half precision Render Target Write messages have data payloads that can pack a full SIMD16 payload into 1 register instead of

[Mesa-dev] [PATCH v4 38/44] i965/disasm: Show half-precision data_format on rt_writes

--- src/intel/compiler/brw_disasm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 1a94ed3954..c752e15331 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -1676,6 +1676,10 @@ brw_d

[Mesa-dev] [PATCH v4 33/44] i965/fs: Unpack 16-bit from 32-bit components in VS load_input

The VS load input for 16-bit values receives pairs of 16-bit values packed in 32-bit values. Because of the adjusted format used at: anv/pipeline: Use 32-bit surface formats for 16-bit formats v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand) v3: Fix coding style and typo (Topi Po

[Mesa-dev] [PATCH v4 30/44] i965/compiler: includes 16-bit vertex input

Includes the info about 16-bit vertex inputs coming from nir on brw VS prog data, as we already do with 64-bit vertex input. v2: Renamed half_inputs_read to inputs_read_16bit (Jason Ekstrand) --- src/intel/compiler/brw_compiler.h | 1 + src/intel/compiler/brw_vec4.cpp | 1 + 2 files changed, 2

[Mesa-dev] [PATCH v4 37/44] i965/fs: Include support for SEND data_format bit for Render Targets

From intel Skylake PRM, vol 07, section "EU Overview", subsection "Send Message" (page 905): "Bit 30: Data format. This field specifies the width of data read from sampler or written to render target. Format = U1 0 Single Precision (32b), 1 Half Precision (16b)" Also pr

[Mesa-dev] [PATCH v4 36/44] anv: Enable VK_KHR_16bit_storage for input/output

Enables storageInputOutput16 feature of VK_KHR_16bit_storage for Gen8+. --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 2e5b914480..26c0ace1ca 100644 --- a/src/intel/vulkan/anv

[Mesa-dev] [PATCH v4 32/44] anv/cmd_buffer: Add a padding to the vertex buffer

From: Alejandro Piñeiro As we are using 32-bit surface formats with 16-bit elements we can be on a situation where a vertex element can poke over the buffer by 2 bytes. To avoid that we add a padding when flushing the state. This is similar to what the i965 drivers prior to Haswell do, as they u

[Mesa-dev] [PATCH v4 28/44] i965/fs: Use untyped_surface_read for 16-bit load_ssbo

SSBO loads were using byte_scattered read messages as they allow reading 16-bit size components. byte_scattered messages can only operate one component at a time so we needed to emit as many messages as components. But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the untyped_su

[Mesa-dev] [PATCH v4 27/44] i965/fs: Predicate byte scattered writes if needed

From: Alejandro Piñeiro While on Untyped Surface messages the bits of the execution mask are ANDed with the corresponding bits of the Pixel/Sample Mask, that is not the case for byte scattered writes. That is needed to avoid ssbo stores writing on helper invocations. So when that can affect, we l

[Mesa-dev] [PATCH v4 35/44] i965/fs: Enable Render Target Write for 16-bit outputs

Broadwell doesn't support half precisions data formats on render target writes (RTW) messages. So the solution to write 16-bit outputs is to use the conversion from 32-bit to 16-bit when writing 32-bit values on a 16-bit format surface using formats like R16_FLOAT. Half-precision outputs are conve

[Mesa-dev] [PATCH v4 29/44] compiler: Mark when input/ouput attribute at VS uses 16-bit

New shader attribute to mark when a location has 16-bit value. This patch includes support on mesa glsl and nir. v2: Remove use of is_half_slot as is a duplicate of is_16bit (Topi Pohjolainen) Renamed half_inputs_read to inputs_read_16bit (Jason Ekstrand) --- src/compiler/glsl_types.h

[Mesa-dev] [PATCH v4 34/44] i965/fs: Support 16-bit types at load_input and store_output

Enables the support of 16-bit types on load_input and store_outputs intrinsics intra-stages. The approach was based on re-using the 32-bit URB read and writes between stages, shuffling pairs of 16-bit values into 32-bit values at load_store intrinsic and un-shuffling the values at load_inputs. v2

[Mesa-dev] [PATCH v4 31/44] anv/pipeline: Use 32-bit surface formats for 16-bit formats

From: Alejandro Piñeiro From Vulkan 1.0.50 spec, Section 3.30.1. Format Definition: VK_FORMAT_R16G16_SFLOAT A two-component, 32-bit signed floating-point format that has a 16-bit R component in bytes 0..1, and a 16-bit G component in bytes 2..3. As vertex data and other inputs h

[Mesa-dev] [PATCH v4 25/44] anv: Enable VK_KHR_16bit_storage for SSBO and UBO

From: Alejandro Piñeiro It uses VK_KHR_get_physical_device_properties2 functionality to expose if the extension is supported or not. v2: update due rebase against master (Alejandro) v3: (Jason Ekstrand) - Move this patch up in VK_KHR_16bit_storage series enabling only storageBuffer16B

[Mesa-dev] [PATCH v4 26/44] i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg

From: Eduardo Lima Mitev Currently, we use byte-scattered write messages for storing 16-bit into an SSBO. This is because untyped surface messages have a fixed 32-bit size. This patch optimizes these 16-bit writes by combining 2 values (e.g, two consecutive components aligned with 32-bits) into

Re: [Mesa-dev] [PATCH v3] nir: add varying array splitting pass

Tested-by: Dieter Nützel Dieter Am 30.11.2017 01:19, schrieb Timothy Arceri: V2: - fix matrix support, non-array matrices were being skipped in v1 v3: - handle lowering of tcs output loads correctly - correctly mark indirect locations for either in or out not both when processing a stag

Re: [Mesa-dev] [PATCH v4] nir: add varying component packing helpers

Tested-by: Dieter Nützel Dieter Am 30.11.2017 01:20, schrieb Timothy Arceri: v2: update shader info input/output masks when pack components v3: make sure interpolation loc matches, this is required for the radeonsi NIR backend. v4: 33dca36f4f28 fixed nir_gather_info to update outputs_read

[Mesa-dev] [PATCH v4 23/44] i965/fs: Enables 16-bit load_ubo with sampler

load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit surface format defined. So when reading 16-bit components with the sampler we need to unshuffle two 16-bit components from each 32-bit component. Using the sampler avoids the use of the byte_scattered_read message that needs one mes

[Mesa-dev] [PATCH v4 22/44] i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit components

This helpers are used to load/store 16-bit types from/to 32-bit components. The functions shuffle_32bit_load_result_to_16bit_data and shuffle_16bit_data_for_32bit_write are implemented in a similar way than the analogous functions for handling 64-bit types. --- src/intel/compiler/brw_fs.h |

[Mesa-dev] [PATCH v4 24/44] anv: Enable SPV_KHR_16bit_storage on gen 8+

From: Eduardo Lima Mitev v2: minor changes after rebase against recent master (Alejandro) --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 907b24a758..c58bd2f9a1 100644 --- a/src/intel/

[Mesa-dev] [PATCH v4 21/44] i965/fs: Use byte scattered read for 16-bit load_ssbo

Used to enable 16-bit reads at do_untyped_vector_read, that is used on the following intrinsics: * nir_intrinsic_load_shared * nir_intrinsic_load_ssbo v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand) v3: - Add bitsize to scattered read operation (Jason Ekstrand) - Remov

[Mesa-dev] [PATCH v4 20/44] i965/fs: Add byte scattered read message and fs support

v2: Fix alignment style (Topi Pohjolainen) (Jason Ekstrand) - Enable bit_size parameter to scattered messages to enable different bitsizes byte/word/dword. - Remove use of brw_send_indirect_scattered_message in favor of brw_send_indirect_surface_message. - Move scattered

[Mesa-dev] [PATCH v4 19/44] i965/fs: Use byte_scattered_write on 16-bit store_ssbo

From: Alejandro Piñeiro We need to rely on byte scattered writes as untyped writes are 32-bit size. We could try to keep using 32-bit messages when we have two or four 16-bit elements, but for simplicity sake, we use the same message for any component number. We revisit this aproach in the follwi

[Mesa-dev] [PATCH v4 11/44] i965: Support for 16-bit base types in helper functions

v2: Fixed calculation of scalar size for 16-bit types. (Jason Ekstrand) Signed-off-by: Jose Maria Casanova Crespo Signed-off-by: Eduardo Lima Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs.cpp | 4 src/intel/compiler/brw_nir.c | 16 src/intel/compiler

[Mesa-dev] [PATCH v4 09/44] spirv/nir: Add support for SPV_KHR_16bit_storage

From: Eduardo Lima Mitev v2: Minor changes after rebase against recent master (Alejandro Pinheiro) Reviewed-by: Jason Ekstrand --- src/compiler/spirv/nir_spirv.h| 1 + src/compiler/spirv/spirv_to_nir.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/src/compiler/spirv/nir_s

[Mesa-dev] [PATCH v4 07/44] spirv/nir: Handle 16-bit types

From: Eduardo Lima Mitev v2: Added more missing implementations of 16-bit types. (Jason Ekstrand) v3: Store values in values[0].u16[i] (Jason Ekstrand) Include switches based on bitsize for 16-bit types (Chema Casanova) Signed-off-by: Jose Maria Casanova Crespo Signed-off-by: Eduardo L

[Mesa-dev] [PATCH v4 13/44] i965/fs: Handle 32-bit to 16-bit conversions

From: Alejandro Piñeiro Conversions to 16-bit need having aligment between the 16-bit and 32-bit types. So the conversion operations unpack 16-bit types to with an stride=2 and then applies a MOV with the conversion. v2 (Jason Ekstrand): - Avoid the general use of stride=2 for 16-bit register

[Mesa-dev] [PATCH v4 08/44] spirv: Enable FPRoundingMode decorator to nir operations

SpvOpFConvert now manages the FPRoundingMode decorator for the returning values enabling the nir_rounding_mode in the conversion operation to fp16 values. v2: Fixed breaking of specialization constants. (Jason Ekstrand) v3: Avoid nir_rounding_mode * casting. (Jason Ekstrand) Reviewed-by: Jason E

[Mesa-dev] [PATCH v4 17/44] i965/fs: Add remove_extra_rounding_modes optimization

From: Alejandro Piñeiro Although from SPIR-V point of view, rounding modes are attached to the operation/destination, on i965 it is a status, so we don't need to explicitly set the rounding mode if the one we want is already set. Taking into account that the default mode is RTE, one possible opt

[Mesa-dev] [PATCH v4 12/44] i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_type

From: Alejandro Piñeiro Note that we don't remove the assert at i965/vec4. At this point half float support is only for the scalar backend. Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_ir_fs.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/compiler/brw_ir_fs.h b/src/

[Mesa-dev] [PATCH v4 15/44] i965/fs: Define new shader opcode to set rounding modes

From: Alejandro Piñeiro Although it is possible to emit them directly as AND/OR on brw_fs_nir, having a specific opcode makes it easier to remove duplicate settings later. v2: (Curro) - Set thread control to 'switch' when using the control register - Use a single SHADER_OPCODE_RND_MODE opcod

[Mesa-dev] [PATCH v4 16/44] i965/fs: Enable rounding mode on f2f16 ops

From: Alejandro Piñeiro By default we don't set the rounding mode. We only set round-to-near-even or round-to-zero mode if explicitly set from nir. v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate with the rounding mode (Curro) v3: Use new helper brw_rnd_mode_from_nir_op

[Mesa-dev] [PATCH v4 18/44] i965/fs: Add byte scattered write message and fs support

v2: (Jason Ekstrand) - Enable bit_size parameter to scattered messages to enable different bitsizes byte/word/dword. - Remove use of brw_send_indirect_scattered_message in favor of brw_send_indirect_surface_message. - Move scattered messages to surface messages namespace.

[Mesa-dev] [PATCH v4 14/44] i965: Add support for control register

Control register cr0 in i965 can be used to change the rounding modes in 32-bit to 16-bit floating-point conversions. From intel Skylake PRM, vol 07, section "Register and Tegister Regions", subsection "Control Register" (page 754): "Subregister cr0.0:ud contains normal operation control fields

[Mesa-dev] [PATCH v4 10/44] i965/vec4: Handle 16-bit types at type_size_xvec4

From: Alejandro Piñeiro These types have similar vec4 sizes as their 32-bit counterparts. The vec4 backend doesn't support 16-bit types and probably never will, but this method is called by the scalar backend at fs_visitor::nir_setup_outputs(), so we still need to provide valid vec4 sizes for 16

[Mesa-dev] [PATCH v4 04/44] nir: Add rounding modes enum

v2: Added comments describing each of the rounding modes. (Jason Ekstrand) Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index d50e81b46d..883f371d1f 100644 --- a/src/comp

[Mesa-dev] [PATCH v4 01/44] glsl: Add 16-bit types

From: Eduardo Lima Mitev Adds new INT16, UINT16 and FLOAT16 base types. The corresponding GL types for half floats were reused from the AMD_gpu_shader_half_float extension. The int16 and uint16 types come from NV_gpu_shader_5 extension. This adds the builtins and the lexer support. To avoid a

[Mesa-dev] [PATCH v4 06/44] nir: Handle fp16 rounding modes at nir_type_conversion_op

nir_type_conversion enables new operations to handle rounding modes to convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne and nir_op_f2f16_rtz. The undefined behaviour doesn't has any effect and uses the original nir_op_f2f16 operation. v2: Indentation fixed (Jason Ekstrand) v

[Mesa-dev] [PATCH v4 02/44] mesa/st: Handle 16-bit types at st_glsl_storage_type_size()

From: Eduardo Lima Mitev This is basically to avoid "not handle in switch" warnings. v2: Let the new types hit the assertion instead. (Marek Olšák and Jason Ekstrand) Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle Reviewed-by: Jason Ekstrand --- src/mesa/state_tracker/st_glsl_type

[Mesa-dev] [PATCH v4 03/44] nir: Add support for 16-bit types (half float, int16 and uint16)

From: Eduardo Lima Mitev v2: Renamed glsl_half_float_type() to glsl_float16_t_type(). (Jason Ekstrand) Signed-off-by: Jose Maria Casanova Crespo Signed-off-by: Eduardo Lima Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir.c | 6 ++ src/compiler/nir/nir.h

[Mesa-dev] [PATCH v4 05/44] nir: Populate conversion opcodes to 16-bit types

From: Eduardo Lima Mitev This will include the following NIR ALU opcodes: * nir_op_i2i16 * nir_op_i2f16 * nir_op_u2u16 * nir_op_u2f16 * nir_op_f2i16 * nir_op_f2u16 * nir_op_f2f16 v2: Remove "from" 16-bit in commit subject (Topi Pohjolainen) Reviewed-by: Jason Ekstrand --- src/compiler/

[Mesa-dev] [PATCH v4 00/44] anv: SPV_KHR_16bit_storage/VK_KHR_16bit_storage for gen8+

Hello, this is the V4 series for the implementation of the SPV_KHR_16bit_storage and VK_KHR_16bit_storage extensions on the anv vulkan driver, in addition to the GLSL and NIR support needed. The original series can be found here [1], the following v2 [2] and v3 [3]. In short V4 includes the foll

Re: [Mesa-dev] [PATCH] i965: implement (un)mapImage

Julien, Mind if I ask what your use-case is? We've been talking about trying to remove tiled mapping from the driver and using blits instead. I don't want to suddenly drop someone off a performance cliff. Thanks, --Jason On Tue, Nov 14, 2017 at 3:05 AM, Julien Isorce wrote: > Already implem

Re: [Mesa-dev] [PATCH 00/12] anv: Add support for the variablePointers feature

On Mon 06 Nov 2017, Jason Ekstrand wrote: > On Mon, Nov 6, 2017 at 7:26 PM, Jason Ekstrand <[1]ja...@jlekstrand.net> > wrote: > The tests are fixed in CL #1915.  I feel like a dork now... The CL is still languishing in Gerrit. fyi, I've pushed a branch with the CL. http://git.kiwitree.net/c

[Mesa-dev] [PATCH 2/2] ac/surface: always compute DCC info when DCC is possible on GFX9

From: Marek Olšák The same code for VI doesn't check for scanout either. --- src/amd/common/ac_surface.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 8347c45..590920e 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/comm

[Mesa-dev] [PATCH 1/2] radeonsi/gfx9: fix importing shared textures with DCC

From: Marek Olšák VI has 11 dwords at least. GFX9 has 10 dwords. Cc: 17.2 17.3 --- src/gallium/drivers/radeon/r600_texture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 1a0503b.

Re: [Mesa-dev] [PATCH 2/4] i965/tex_image: Reference the renderbuffer miptree in setTexBuffer2

On Wed, Nov 29, 2017 at 4:42 PM, Chad Versace wrote: > On Tue 28 Nov 2017, Jason Ekstrand wrote: > > > > > > On Tue, Nov 21, 2017 at 3:05 PM, Chad Versace <[1] > chadvers...@chromium.org> > > wrote: > > > > @@ -442,7 +443,6 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, > GLint > > target,

Re: [Mesa-dev] [PATCH 2/4] i965/tex_image: Reference the renderbuffer miptree in setTexBuffer2

On Tue 28 Nov 2017, Jason Ekstrand wrote: > > > On Tue, Nov 21, 2017 at 3:05 PM, Chad Versace <[1]chadvers...@chromium.org> > wrote: > > @@ -442,7 +443,6 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint > target, > >     struct gl_texture_object *texObj; > >     struct gl_textu

Re: [Mesa-dev] Refactored st/omx/tizonia commits

Quoting Eric Engestrom (2017-11-29 07:19:02) > On Wednesday, 2017-11-29 09:32:09 +0530, Gurkirpal Singh wrote: > > These are the refactored commits related to the GSoC project involving > > adding a st/omx state tracker using tizonia. > > There are still some parts of code that i didn't refactor ye

[Mesa-dev] [PATCH v4] nir: add varying component packing helpers

v2: update shader info input/output masks when pack components v3: make sure interpolation loc matches, this is required for the radeonsi NIR backend. v4: 33dca36f4f28 fixed nir_gather_info to update outputs_read correct, make sure we also adjust this correctly when packing components.

[Mesa-dev] [PATCH v3] nir: add varying array splitting pass

V2: - fix matrix support, non-array matrices were being skipped in v1 v3: - handle lowering of tcs output loads correctly - correctly mark indirect locations for either in or out not both when processing a stage. - use nir_src_copy() when lowering stores. --- src/compiler/Makefile.sources

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On Wed, 29 Nov 2017 16:28:15 -0500 Rob Clark wrote: > On Wed, Nov 29, 2017 at 2:41 PM, Miguel Angel Vico > wrote: > > Many of you may already know, but James is going to be out for a few > > weeks and I'll be taking over this in the meantime. > > > > See inline for comments. > > > > On Wed, 2

Re: [Mesa-dev] [PATCH] radv: do not allocate CMASK or DCC for small surfaces

On 29 November 2017 at 23:48, Samuel Pitoiset wrote: > The idea is ported from RadeonSI, but using 512x512 instead of > 256x256 seems slightly better. This improves dota2 performance > by +2%. I wonder if the threshold is different on some sort of GPU basis (mem bw). But this seems like the best

Re: [Mesa-dev] [RFC] r600/evergreen compute shader + glsl 4.30 support

On 29 November 2017 at 22:46, Gert Wollny wrote: > Am Mittwoch, den 29.11.2017, 14:36 +1000 schrieb Dave Airlie: >> This set of patches enables compute shaders on r600 and exposes GLSL >> 4.30 support. They are pretty alpha level, but I'd like to land some >> of them (maybe disabled) so I can avoi

Re: [Mesa-dev] [PATCH 2/2] glsl: Fix gl_NormalScale.

Reviewed-by: Brian Paul On 11/23/2017 01:48 PM, Fabian Bieler wrote: GLSL shaders can access the normal scale factor with the built-in gl_NormalScale. Mesa's modelspace lighting optimization uses a different normal scale factor than defined in the spec. We have to take care not to use this

Re: [Mesa-dev] [PATCH 1/2] glsl: Match order of gl_LightSourceParameters elements.

Reviewed-by: Brian Paul I think you could tag both of your patches for the stable branch. On 11/23/2017 01:48 PM, Fabian Bieler wrote: spotExponent and spotCosCutoff were swapped in the gl_builtin_uniform_element struct. Now the order matches across gl_builtin_uniform_element, glsl_struct_fiel

Re: [Mesa-dev] [PATCH v2 09/32] anv: Require a dedicated allocation for modified images

On Wed, Nov 29, 2017 at 2:24 PM, Chad Versace wrote: > On Tue 28 Nov 2017, Jason Ekstrand wrote: > > This lets us set the BO tiling when we allocate the memory. This is > > required for GL to work properly. > > --- > > src/intel/vulkan/anv_device.c | 53 ++ >

Re: [Mesa-dev] [PATCH] glx: add support for GLX_ARB_create_context_no_error (v2)

On 11/29/2017 02:30 PM, Adam Jackson wrote: On Wed, 2017-11-29 at 16:20 -0500, Adam Jackson wrote: From: Grigori Goronzy v2: Only reject no-error contexts for too-old GL if we're actually trying to create a no-error context (Adam Jackson) Reviewed-by: Adam Jackson Note that the original se

Re: [Mesa-dev] [PATCH 3/6] radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side

On 29.11.2017 15:29, Marek Olšák wrote: On Wed, Nov 29, 2017 at 10:59 AM, Nicolai Hähnle wrote: On 28.11.2017 22:17, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/radeonsi/si_descriptors.c | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/ra

Re: [Mesa-dev] [PATCH v2 09/32] anv: Require a dedicated allocation for modified images

On Tue 28 Nov 2017, Jason Ekstrand wrote: > This lets us set the BO tiling when we allocate the memory. This is > required for GL to work properly. > --- > src/intel/vulkan/anv_device.c | 53 > +++ > 1 file changed, 49 insertions(+), 4 deletions(-) > > di

Re: [Mesa-dev] [PATCH v2 06/32] anv: Implement VK_EXT_external_memory_dma_buf

On Wed, Nov 29, 2017 at 1:44 PM, Chad Versace wrote: > On Tue 28 Nov 2017, Jason Ekstrand wrote: > > This is a modified version of the patch originally sent by Chad Versace. > > The primary difference is that this version claims that OPQAUE_FD and > > DMA_BUF are compatible handle types. > > ---

Re: [Mesa-dev] [PATCH 1/8] nir: add varying array splitting pass

On 29/11/17 21:47, Nicolai Hähnle wrote: On 21.11.2017 04:28, Timothy Arceri wrote: V2: fix matrix support, non-array matrices were being skipped in v1 ---   src/compiler/Makefile.sources  |   1 +   src/compiler/nir/meson.build   |   1 +   src/compiler/nir

Re: [Mesa-dev] [PATCH] glx: add support for GLX_ARB_create_context_no_error (v2)

On Wed, 2017-11-29 at 16:20 -0500, Adam Jackson wrote: > From: Grigori Goronzy > > v2: Only reject no-error contexts for too-old GL if we're actually > trying to create a no-error context (Adam Jackson) D'oh, this is still busted, sorry for the noise. We're not saving the no-error state in the c

Re: [Mesa-dev] [PATCH v2 07/32] radv: Implement VK_EXT_external_memory_dma_buf

On Wed, Nov 29, 2017 at 1:41 PM, Chad Versace wrote: > On Tue 28 Nov 2017, Jason Ekstrand wrote: > > --- > > src/amd/vulkan/radv_device.c | 8 ++-- > > src/amd/vulkan/radv_extensions.py | 1 + > > src/amd/vulkan/radv_formats.c | 8 ++-- > > 3 files changed, 13 insertions(+), 4 d

Re: [Mesa-dev] [PATCH v2 08/32] anv/image: Add a drm_format_mod field

On Tue 28 Nov 2017, Jason Ekstrand wrote: > At the moment, this is always initialized to DRM_FORMAT_MOD_INVALID. > --- > src/intel/vulkan/anv_image.c | 2 ++ > src/intel/vulkan/anv_private.h | 5 + > 2 files changed, 7 insertions(+) This patch is Reviewed-by: Chad Versace _

Re: [Mesa-dev] [PATCH v2 06/32] anv: Implement VK_EXT_external_memory_dma_buf

On Tue 28 Nov 2017, Jason Ekstrand wrote: > This is a modified version of the patch originally sent by Chad Versace. > The primary difference is that this version claims that OPQAUE_FD and > DMA_BUF are compatible handle types. > --- > src/intel/vulkan/anv_device.c | 13 ++--- > src/i

Re: [Mesa-dev] [PATCH v2 07/32] radv: Implement VK_EXT_external_memory_dma_buf

On Tue 28 Nov 2017, Jason Ekstrand wrote: > --- > src/amd/vulkan/radv_device.c | 8 ++-- > src/amd/vulkan/radv_extensions.py | 1 + > src/amd/vulkan/radv_formats.c | 8 ++-- > 3 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/src/amd/vulkan/radv_device.c b/src/am

Re: [Mesa-dev] [PATCH v2] configure: avoid testing for negative compiler options

Reviewed-by: Dylan Baker Quoting Marc Dietrich (2017-11-29 13:25:05) > gcc seems to always accept unsupported negative compiler warning options: > > echo "int i;" | gcc -c -xc -Wno-bob - # no error > echo "int i;" | gcc -c -xc -Walice - # unsupported compiler option > > Inverting the options f

Re: [Mesa-dev] [PATCH] glx: add support for GLX_ARB_create_context_no_error (v2)

On Wed, 2017-11-29 at 16:20 -0500, Adam Jackson wrote: > From: Grigori Goronzy > > v2: Only reject no-error contexts for too-old GL if we're actually > trying to create a no-error context (Adam Jackson) > > Reviewed-by: Adam Jackson Note that the original series for this also updated st/glx. T

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On Wed, Nov 29, 2017 at 2:41 PM, Miguel Angel Vico wrote: > Many of you may already know, but James is going to be out for a few > weeks and I'll be taking over this in the meantime. > > See inline for comments. > > On Wed, 29 Nov 2017 09:33:29 -0800 > Jason Ekstrand wrote: > >> On Sat, Nov 25, 2

[Mesa-dev] [PATCH v2] configure: avoid testing for negative compiler options

gcc seems to always accept unsupported negative compiler warning options: echo "int i;" | gcc -c -xc -Wno-bob - # no error echo "int i;" | gcc -c -xc -Walice - # unsupported compiler option Inverting the options fixes the tests. V2: fix options in meson build Reviewed-by: Matt Turner Signed-o

[Mesa-dev] [PATCH] glx: add support for GLX_ARB_create_context_no_error (v2)

From: Grigori Goronzy v2: Only reject no-error contexts for too-old GL if we're actually trying to create a no-error context (Adam Jackson) Reviewed-by: Adam Jackson --- src/glx/dri2_glx.c | 12 src/glx/dri3_glx.c | 8 src/glx/dri_common.c| 52 +

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On Wed, Nov 29, 2017 at 12:33 PM, Jason Ekstrand wrote: > On Sat, Nov 25, 2017 at 1:20 PM, Rob Clark wrote: >> >> On Sat, Nov 25, 2017 at 12:46 PM, Jason Ekstrand >> wrote: >> > On November 24, 2017 09:29:43 Rob Clark wrote: >> >> >> >> >> >> On Mon, Nov 20, 2017 at 8:11 PM, James Jones >> >>

Re: [Mesa-dev] [PATCH 1/5] xlib: remove empty GLX_NV_vertex_array_range stubs

On Wed, 2017-11-29 at 19:23 +, Emil Velikov wrote: > From: Emil Velikov > > The extension was never implemented and seemingly never will. > The DRI based libGL dropped support for it over 10 years ago. Series is: Reviewed-by: Adam Jackson There's some stubs in src/glx/glxcmds.c that can g

[Mesa-dev] [Bug 103732] [swr] often gets stuck in piglit's glx-multi-context-single-window test

https://bugs.freedesktop.org/show_bug.cgi?id=103732 --- Comment #10 from Bruce Cherniak --- On Nov 29, 2017, at 7:50 AM, bugzilla-dae...@freedesktop.org wrote: Comment # 9 on bug 103732

Re: [Mesa-dev] [PATCH v2 06/32] anv: Implement VK_EXT_external_memory_dma_buf

On Tue 28 Nov 2017, Jason Ekstrand wrote: > This is a modified version of the patch originally sent by Chad Versace. > The primary difference is that this version claims that OPQAUE_FD and > DMA_BUF are compatible handle types. > --- > src/intel/vulkan/anv_device.c | 13 ++--- > src/i

Re: [Mesa-dev] [PATCH 1/5] xlib: remove empty GLX_NV_vertex_array_range stubs

Series looks OK to me. Reviewed-by: Brian Paul On 11/29/2017 12:23 PM, Emil Velikov wrote: From: Emil Velikov The extension was never implemented and seemingly never will. The DRI based libGL dropped support for it over 10 years ago. Cc: Brian Paul Cc: Ian Romanick Signed-off-by: Emil Vel

Re: [Mesa-dev] [PATCH] configure: avoid testing for negative compiler options

On Wed, Nov 29, 2017 at 5:47 AM, Marc Dietrich wrote: > gcc seems to always accept unsupported negative compiler warning options: > > echo "int i;" | gcc -c -xc -Wno-bob - # no error > echo "int i;" | gcc -c -xc -Walice - # unsupported compiler option > > Inverting the options fixes the tests. T

Re: [Mesa-dev] [PATCH] i965/vec4: use a temp register to compute offsets for pull loads

On Wed, Nov 29, 2017 at 2:49 AM, Iago Toral Quiroga wrote: > 64-bit pull loads are implemented by emitting 2 separate > 32-bit pull load messages, where the second message loads from > an offset at +16B. > > That addition of 16B to the original offset should not alter the > original offset registe

Re: [Mesa-dev] [PATCH 08/29] anv/cmd_buffer: Recurse in transition_color_buffer instead of falling through

On Wed, Nov 29, 2017 at 12:01 PM, Jason Ekstrand wrote: > On Wed, Nov 29, 2017 at 11:57 AM, Pohjolainen, Topi < > topi.pohjolai...@gmail.com> wrote: > >> On Mon, Nov 27, 2017 at 07:05:58PM -0800, Jason Ekstrand wrote: >> > --- >> > src/intel/vulkan/genX_cmd_buffer.c | 17 - >> >

Re: [Mesa-dev] [PATCH 08/29] anv/cmd_buffer: Recurse in transition_color_buffer instead of falling through

On Wed, Nov 29, 2017 at 11:57 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Mon, Nov 27, 2017 at 07:05:58PM -0800, Jason Ekstrand wrote: > > --- > > src/intel/vulkan/genX_cmd_buffer.c | 17 - > > 1 file changed, 8 insertions(+), 9 deletions(-) > > > > diff --git

Re: [Mesa-dev] [PATCH 08/29] anv/cmd_buffer: Recurse in transition_color_buffer instead of falling through

On Mon, Nov 27, 2017 at 07:05:58PM -0800, Jason Ekstrand wrote: > --- > src/intel/vulkan/genX_cmd_buffer.c | 17 - > 1 file changed, 8 insertions(+), 9 deletions(-) > > diff --git a/src/intel/vulkan/genX_cmd_buffer.c > b/src/intel/vulkan/genX_cmd_buffer.c > index 0c1ae83..be717eb

Re: [Mesa-dev] [PATCH] configure: avoid testing for negative compiler options

Quoting Marc Dietrich (2017-11-29 05:47:55) > gcc seems to always accept unsupported negative compiler warning options: > > echo "int i;" | gcc -c -xc -Wno-bob - # no error > echo "int i;" | gcc -c -xc -Walice - # unsupported compiler option > > Inverting the options fixes the tests. > > Signed

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

Many of you may already know, but James is going to be out for a few weeks and I'll be taking over this in the meantime. See inline for comments. On Wed, 29 Nov 2017 09:33:29 -0800 Jason Ekstrand wrote: > On Sat, Nov 25, 2017 at 1:20 PM, Rob Clark wrote: > > > On Sat, Nov 25, 2017 at 12:46 PM

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