Re: [Mesa-dev] [ANNOUNCE] mesa 17.3.4

Bas Nieuwenhuizen writes: > (-mesa-announce + Mark, Dave and James) > > Hi Emil, > > radv is broken for nearly all commercial games in 17.3.4. The cause is > > commit ad764e365beb8a119369b97f5cb95fc7ea8c > Author: Bas Nieuwenhuizen > Date:

[Mesa-dev] [PATCH 10/13] radeonsi: allow fewer input SGPRs in 2nd shader of merged shaders

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 783d57f..6d0c81d 100644 ---

[Mesa-dev] [PATCH 09/13] radeonsi: don't use struct si_descriptors for vertex buffer descriptors

From: Marek Olšák VBO descriptor code will change a lot one day. --- src/gallium/drivers/radeonsi/si_blit.c| 2 +- src/gallium/drivers/radeonsi/si_cp_dma.c | 5 ++- src/gallium/drivers/radeonsi/si_debug.c | 14 ++--

[Mesa-dev] [PATCH 13/13] radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointers

From: Marek Olšák The effect of the last 13 commits on user SGPR counts: 64-bit pointers: TCS:14 -> 12 Merged VS-TCS: 24 -> 20 Merged VS-GS: 18 -> 16 Merged TES-GS: 18 -> 14 32-bit pointers: TCS:10 -> 8 Merged VS-TCS: 16 -> 12 Merged

[Mesa-dev] [PATCH 06/13] radeonsi: move tess ring address into TCS_OUT_LAYOUT, removes 2 TCS user SGPRs

From: Marek Olšák TCS_OUT_LAYOUT has 13 unused bits. That's enough for a 32-bit address aligned to 512KB. Hey, it's a 13-bit pointer! --- src/gallium/drivers/radeonsi/si_shader.c | 104 +++--- src/gallium/drivers/radeonsi/si_shader.h | 6

[Mesa-dev] [PATCH 11/13] radeonsi: set correct num_input_sgprs for VS prolog in merged shaders

From: Marek Olšák We need to take num_input_sgprs from VS, not the second shader. No apps suffered from this. --- src/gallium/drivers/radeonsi/si_shader.c | 48 1 file changed, 24 insertions(+), 24 deletions(-) diff --git

[Mesa-dev] [PATCH 08/13] radeonsi: remove si_descriptors parameter from emit_shader_pointer functions

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_descriptors.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index

[Mesa-dev] [PATCH 02/13] radeonsi: move tessellation ring info into si_screen

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_pipe.c | 38 - src/gallium/drivers/radeonsi/si_pipe.h | 3 ++ src/gallium/drivers/radeonsi/si_state_shaders.c | 56 ++--- 3 files changed, 52 insertions(+), 45

[Mesa-dev] [PATCH 07/13] radeonsi: preload the tess offchip ring in TES

From: Marek Olšák so that it's not done multiple times in branches --- src/gallium/drivers/radeonsi/si_shader.c | 21 + src/gallium/drivers/radeonsi/si_shader_internal.h | 1 + 2 files changed, 10 insertions(+), 12 deletions(-) diff --git

[Mesa-dev] [PATCH 03/13] radeonsi: put both tessellation rings into 1 buffer

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_pipe.c | 3 +- src/gallium/drivers/radeonsi/si_pipe.h | 3 +- src/gallium/drivers/radeonsi/si_state_draw.c| 2 +- src/gallium/drivers/radeonsi/si_state_shaders.c | 39 ++--- 4

[Mesa-dev] [PATCH 00/13] RadeonSI: Reduce user SGPR usage

Hi, This series has the following effect on user SGPRs: 64-bit pointers: TCS:14 -> 12 Merged VS-TCS: 24 -> 20 Merged VS-GS: 18 -> 16 Merged TES-GS: 18 -> 14 32-bit pointers: TCS:10 -> 8 Merged VS-TCS: 16 -> 12 Merged VS-GS: 11 -> 9 Merged TES-GS: 11 ->

[Mesa-dev] [PATCH 01/13] radeonsi: move TCS_OUT_LAYOUT.PatchVerticesIn to lower bits

From: Marek Olšák For a later patch. --- src/gallium/drivers/radeonsi/si_shader.c | 2 +- src/gallium/drivers/radeonsi/si_shader_internal.h | 2 +- src/gallium/drivers/radeonsi/si_state_draw.c | 7 --- 3 files changed, 6 insertions(+), 5 deletions(-) diff

[Mesa-dev] [PATCH 12/13] radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR input

From: Marek Olšák so that it can be removed and replaced with inline VBO descriptors, and the pointer can be packed in unused bits of VBO descriptors. This also removes the pointer from merged TES-GS where it's useless. --- src/gallium/drivers/radeonsi/si_descriptors.c |

[Mesa-dev] [PATCH 05/13] radeonsi: move 2nd-shader descriptor pointers into s[0:1]

From: Marek Olšák If 32-bit pointers are supported, both pointers can be moved into s[0:1] and then ESGS has exactly the same user data SGPR declarations as VS. If 32-bit pointers are not supported, only one pointer can be moved into s[0:1]. In that case, the 2nd pointer is

[Mesa-dev] [PATCH 04/13] radeonsi: change si_descriptors::shader_userdata_offset type to short

From: Marek Olšák We will want to use SH registers outside of user data SGPRs, like the GFX9 special SGPRs. --- src/gallium/drivers/radeonsi/si_descriptors.c | 12 ++-- src/gallium/drivers/radeonsi/si_state.h | 6 +++--- 2 files changed, 9 insertions(+), 9

[Mesa-dev] [Bug 105068] vulkaninfo gives an VK_ERROR_INITIALIZATION_FAILED

https://bugs.freedesktop.org/show_bug.cgi?id=105068 Pietro Pesci Feltri changed: What|Removed |Added Resolution|--- |FIXED

[Mesa-dev] [Bug 105068] vulkaninfo gives an VK_ERROR_INITIALIZATION_FAILED

https://bugs.freedesktop.org/show_bug.cgi?id=105068 --- Comment #6 from Pietro Pesci Feltri --- Problem solved :). As stated in https://wiki.archlinux.org/index.php/AMDGPU#Selecting_the_right_driver The parameters must be added to the kernel but the parameters depend on what

Re: [Mesa-dev] [ANNOUNCE] mesa 17.3.4

(-mesa-announce + Mark, Dave and James) Hi Emil, radv is broken for nearly all commercial games in 17.3.4. The cause is commit ad764e365beb8a119369b97f5cb95fc7ea8c Author: Bas Nieuwenhuizen Date: Mon Jan 22 09:01:29 2018 +0100 ac/nir: Use

Re: [Mesa-dev] Mesa 17.3.4 release candidate

Den 13.02.2018 kl. 18:05, skrev James Legg: The conflict resolution on this commit has a typo, it should use (index + i) instead of (index + 1). Yep, attached fix for 17.3 branch... -- Thomas Commmit: ad764e365beb8a119369b97f5cb95fc7ea8c (ac/nir: Use instance_rate_inputs per

Re: [Mesa-dev] [PATCH] anv/gpu_memcpy: CS Stall before a MI memcpy on gen7

On Sat, Feb 17, 2018 at 1:21 AM, Kenneth Graunke wrote: > On Saturday, February 17, 2018 1:09:10 AM PST Jason Ekstrand wrote: > > This fixes a pile of hangs caused by the recent shuffling of resolves > > and transitions. The particularly problematic case is when you have

Re: [Mesa-dev] [PATCH] anv/gpu_memcpy: CS Stall before a MI memcpy on gen7

On Saturday, February 17, 2018 1:09:10 AM PST Jason Ekstrand wrote: > This fixes a pile of hangs caused by the recent shuffling of resolves > and transitions. The particularly problematic case is when you have at > least three attachments with load ops of CLEAR, LOAD, CLEAR. In this > case, we

[Mesa-dev] [PATCH] anv/gpu_memcpy: CS Stall before a MI memcpy on gen7

This fixes a pile of hangs caused by the recent shuffling of resolves and transitions. The particularly problematic case is when you have at least three attachments with load ops of CLEAR, LOAD, CLEAR. In this case, we execute the first CLEAR followed by a MI memcpy to copy the clear values over