Yeah, noticed that CTS fail this morning too. :)
Reviewed-by: Samuel Pitoiset
On 03/08/2018 01:16 AM, Dave Airlie wrote:
From: Dave Airlie
The spec is pretty clear that this can be 0, and that it operates
as a reserved binding.
Fixes:
dEQP-VK.binding_model.descriptor_update.empty_descriptor
Hi,
This is the 5rd version of the series adding initial support for
ARB_gl_spirv. Although the development branch is bigger (more that 80
patches), as mentioned, we prefer to send small, self-contained
series, to make the review process easier.
This series is mostly equal to v4 except:
* New v
Needed for ARB_gl_spirv. Right now those are the same that the intel
vulkan driver, but those are not shared. From the ARB_spirv_extensions
spec:
"3. If a new GL extension is added that includes SPIR-V support via
a new SPIR-V extension does it's SPIR-V extension also get
enumerated by th
ARB_gl_spirv adds the ability to use SPIR-V binaries, and a new
method, glSpecializeShader. From OpenGL 4.6 spec, section 7.2.1
"Shader Specialization", error table:
INVALID_VALUE is generated if does not name a valid
entry point for .
INVALID_VALUE is generated if any element
From: Nicolai Hähnle
For drivers to declare which SPIR-V features they support.
v2: Don't use a pointer (Ian Romanick)
---
src/mesa/main/mtypes.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2df2288899d..463c2696c38 100644
--- a/sr
Refactored from spirv_to_nir, in order to be reused later.
---
src/compiler/spirv/spirv_to_nir.c | 48 ++-
src/compiler/spirv/vtn_private.h | 4
2 files changed, 36 insertions(+), 16 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/comp
From: Nicolai Hähnle
v2: * Use gl_spirv_validation instead of spirv_to_nir.
This method just validates the shader. The conversion to NIR will
happen later, during linking. (Alejandro Piñeiro)
* Use gl_shader_spirv_data struct to store the SPIR-V data.
(Eduardo Lima)
* Use the '
From: Eduardo Lima Mitev
This is basically a wrapper around spirv_to_nir() that includes
arguments setup and post-conversion validation.
v2: * Rebase update (SpirVCapabilities not a pointer anymore,
spirv_to_nir_options added, and others).
* Code-style improvements and remove debug hunk.
From: Eduardo Lima Mitev
v2: Use 'spirv_data' from gl_linked_shader instead, to check if shader
is SPIR-V. (Timothy Arceri)
Reviewed-by: Timothy Arceri
---
src/mesa/drivers/dri/i965/brw_link.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/
From: Eduardo Lima Mitev
This is a reference to the spirv_data object stored in gl_shader, which
stores shader SPIR-V data that is needed during linking too.
Reviewed-by: Timothy Arceri
---
src/mesa/main/mtypes.h| 8
src/mesa/main/shaderobj.c | 1 +
2 files changed, 9 insertions(+
From: Eduardo Lima Mitev
This is the main fork of the shader compilation code-path, where a NIR
shader is obtained by calling spirv_to_nir() or glsl_to_nir(),
depending on its nature..
v2: Use 'spirv_data' member from gl_linked_shader to know which method
to call. (Timothy Arceri)
Reviewed-b
From: Eduardo Lima Mitev
---
src/mesa/program/ir_to_mesa.cpp | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 74089605029..4d45b0a4cd5 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/progr
From: Eduardo Lima Mitev
This is the equivalent to link_shaders() from
src/compiler/glsl/linker.cpp, but for SPIR-V programs. It just
creates the program and its gl_linked_shader objects, giving drivers
the opportunity to implement any linking of SPIR-V shaders they choose,
at a later stage.
v2:
Noticed while passing by. nNot sure if it impacts anything, but
likely to impact GFX9 more than anything else since we lower
inputs, outputs and locals there.
---
src/amd/vulkan/radv_shader.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_shader.c
On Thu, Mar 8, 2018 at 9:37 AM, Timothy Arceri wrote:
> Noticed while passing by. nNot sure if it impacts anything, but
> likely to impact GFX9 more than anything else since we lower
> inputs, outputs and locals there.
> ---
> src/amd/vulkan/radv_shader.c | 10 +-
> 1 file changed, 9 inse
Thanks for the kind words Jason, this is a superb achievement and we
are very proud to had the chance to work on this with you!
Iago
On Wed, 2018-03-07 at 15:08 -0800, Jason Ekstrand wrote:
> Hi all,
>
> I just wanted to give a shout out and a huge "Thank You!" to all of
> the people who made this
Am Montag, den 05.03.2018, 23:26 +0100 schrieb Christian Gmeiner:
> Signed-off-by: Christian Gmeiner
Reviewed-by: Lucas Stach
> ---
> src/gallium/drivers/etnaviv/etnaviv_query_sw.c | 30
> --
> src/gallium/drivers/etnaviv/etnaviv_query_sw.h | 5 +
> 2 files change
Am Montag, den 05.03.2018, 23:26 +0100 schrieb Christian Gmeiner:
> This enables AMD_performance_monitor extension.
>
> Signed-off-by: Christian Gmeiner
Reviewed-by: Lucas Stach
> ---
> src/gallium/drivers/etnaviv/etnaviv_query.c | 13 +
> 1 file changed, 13 insertions(+)
>
> dif
Vivante hardware supports this just fine. There is no reason why this shouldn't
be advertised as a valid combination.
Signed-off-by: Lucas Stach
---
src/gallium/drivers/etnaviv/etnaviv_screen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/etnaviv/etnavi
Am 07.03.2018 um 21:34 schrieb Marek Olšák:
From: Marek Olšák
Cc: 17.3 18.0
Reviewed-by: Christian König .
---
src/amd/common/ac_gpu_info.c | 21 -
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/drivers/radeonsi/si_pm4.c
Am 07.03.2018 um 21:34 schrieb Marek Olšák:
From: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index d9a95c0..9cd3343 100644
--- a/src/g
Am 07.03.2018 um 21:34 schrieb Marek Olšák:
From: Marek Olšák
This is only required with the latest libdrm.
This fixes 32-bit support with high addresses.
(and possibly 64-bit support too because the high bits need to be masked out)
Acked-by: Christian König
---
src/gallium/drivers/rade
Reviewed-by: Karol Herbst
On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote:
> Signed-off-by: Pierre Moreau
> ---
> src/gallium/state_trackers/clover/Makefile.am | 11 +-
> src/gallium/state_trackers/clover/Makefile.sources | 4 -
> src/gallium/state_trackers/clover/core/program.cpp
Reviewed-by: Karol Herbst
On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote:
> Reviewed-by: Aaron Watry
> Signed-off-by: Pierre Moreau
> ---
>
> Notes:
> v3:
> * Dropped supported_irs() (Francisco Jerez)
> * Changed supports_ir() argument type to `enum pipe_shader_ir` (Francisco
Reviewed-by: Karol Herbst
On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote:
> Reviewed-by: Aaron Watry
> Signed-off-by: Pierre Moreau
> ---
> src/gallium/state_trackers/clover/core/device.cpp | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/src/gallium/state_tr
I think it would be valuable to put some comment on what kind of
llvm-spirv we really need. I know the situation isn't perfect. Link to
your branch or something should be good enough.
With that:
Reviewed-by: Karol Herbst
On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote:
> Signed-off-by: Pie
Reviewed-by: Karol Herbst
On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote:
> Signed-off-by: Pierre Moreau
> ---
>
> Notes:
> Changes in v4: Use the core define instead of the extension one (Karol
> Herbst)
>
> v3: Throw an exception if the cl_khr_il_program extension is not support
Reviewed-by: Karol Herbst
On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote:
> Signed-off-by: Pierre Moreau
> ---
>
> Notes:
> v3: Remove the const from the length argument of clCreateProgramWithIL
>
> src/gallium/state_trackers/clover/api/dispatch.cpp | 2 +-
> src/gallium/state_tracker
Reviewed-by: Karol Herbst
On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote:
> Signed-off-by: Pierre Moreau
> ---
>
> Notes:
> Changes in v4: do not advertise SPIR-V support if CLOVER_ALLOW_SPIRV is
> not defined
>
> v3: Advertise cl_khr_il_program if if the device support NATIVE as
Many thanks to you Jason!
On Wed, Mar 7, 2018 at 11:08 PM, Jason Ekstrand wrote:
> Hi all,
>
> I just wanted to give a shout out and a huge "Thank You!" to all of the
> people who made this release possible. There were a large number of
> features packed into the 1.1 release and implementing it
https://bugs.freedesktop.org/show_bug.cgi?id=105171
--- Comment #6 from Clemens Eisserer ---
Strange, after tinkering around with my system, I cannot reproduce the issue
anymore. Even with Mesa-17.3.x x11perf -shnmput10 is now at ~70-80kOps/s - so
maybe it was a configuration issue that was someh
https://bugs.freedesktop.org/show_bug.cgi?id=105171
--- Comment #7 from Michel Dänzer ---
(In reply to Clemens Eisserer from comment #6)
> This still leaves the question to be answered, how/why the nvidia blob can
> be magnitudes faster for XPutImage based workloads.
If somebody wants to improve
On Wednesday, 2018-03-07 23:24:59 -0800, Keith Packard wrote:
> This adds support for the KHR_display extension support to the vulkan
> WSI layer. Driver support will be added separately.
>
> v2:
> * fix double ;; in wsi_common_display.c
>
> * Move mode list from wsi_display to wsi_di
https://bugs.freedesktop.org/show_bug.cgi?id=105171
--- Comment #8 from Clemens Eisserer ---
> If somebody wants to improve this,
> the place to start is probably glamor rather than the drivers.
I wonder, what could glamor do better (especially for small uploads) than call
into glTexSubImage2D?
https://bugs.freedesktop.org/show_bug.cgi?id=105396
Bug ID: 105396
Summary: tc compatible htile sets depth of htiles of discarded
fragments to 1.0
Product: Mesa
Version: git
Hardware: Other
OS: All
https://bugs.freedesktop.org/show_bug.cgi?id=105396
--- Comment #1 from James Legg ---
Created attachment 137888
--> https://bugs.freedesktop.org/attachment.cgi?id=137888&action=edit
Source for application used in RenderDoc frame capture
--
You are receiving this mail because:
You are the QA
On Wed, Mar 07, 2018 at 10:08:59AM -0800, Dylan Baker wrote:
> Quoting Thierry Reding (2018-03-07 07:55:37)
> > From: Thierry Reding
> >
> > The meson build file for Apple GLX is not listed in the EXTRA_DIST make
> > variable and therefore isn't shipped as part of the release tarball, so
> > meso
[Adding Andres, Juan since they'll be doing the next 17.3]
On 7 March 2018 at 16:35, Marek Olšák wrote:
> I can test piglit+CTS+deqp on the GPU that I have. (currently Polaris12)
>
Yes please - that sounds great. If we have more than one device that
would be amazing.
FTR the Lunarg team seems to
Thanks a lot Jason! As Iago said, we are pleased to had the opportunity
to work with you on this :-D
Sam
On 08/03/18 00:08, Jason Ekstrand wrote:
> Hi all,
>
> I just wanted to give a shout out and a huge "Thank You!" to all of
> the people who made this release possible. There were a large num
On Wed, Mar 07, 2018 at 01:15:35PM -0500, Ilia Mirkin wrote:
> On Wed, Mar 7, 2018 at 10:53 AM, Thierry Reding
> wrote:
> > From: Thierry Reding
> >
> > This adds support for framebuffer modifiers to Nouveau. This will be
> > used by the Tegra driver to share metadata about the format of buffers
On Tue, 2018-02-20 at 13:47 -0800, Jordan Justen wrote:
> On 2018-02-20 06:46:24, Andres Gomez wrote:
> > Jordan, this looks like a good candidate to nominate for inclusion in
> > the 17.3 stable queue.
> >
> > What do you think?
>
> I saw this on i965, which does not have shader cache support in
This avoids bug 105396 somehow. I suspect it is a VI and GFX9 hardware
bug which PAL calls WaTcCompatZRange, but I don't know for sure.
In the VK_FORMAT_D32_SFLOAT case, TILE_STENCIL_DISABLE is not set for
tc compatible image formats regardless of not having a stencil aspect.
If TILE_STENCIL_DISAB
On Wed, 2018-02-21 at 08:40 +0100, Iago Toral wrote:
> Yes, I agree, thanks for bringing it up.
>
> Iago
>
Thanks. I'm including it in next 17.3 release.
BTW, this patch was also included in 17.2.8.
J.A.
> On Tue, 2018-02-20 at 16:38 +0200, Andres Gomez wrote:
> > Iago, this looks l
On 7 March 2018 at 19:56, Emil Velikov wrote:
> On 7 March 2018 at 18:32, Bas Nieuwenhuizen wrote:
>
>>>
>>> Missing break?
>>
>> So much for the tests ...
>>
> Speaking of tests, I hope they check that both KHR and non KHR
> annotated functions (the ones changed in 04/16) are tested.
> We don't
From: Kevin Rogovin
Gen9 GPU's suffer from a HW bug where the GPU will hang if
the GPU accesses a texture with a an auxilary buffer and
an ASTC5x5 texture without having a pipeline cs stall (and
texture cache flush) between such accesses. This patch
creates the infrastucture to track such potenti
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/blorp/blorp.c | 16
src/intel/blorp/blorp.h | 6 ++
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 9 +
3 files changed, 31 insertions(+)
diff --git a/src/intel/
From: Kevin Rogovin
This patch series implements a needed workaround for Gen9 for ASTC5x5
sampler reads. The crux of the work around is to make sure that the
sampler does not read an ASTC5x5 texture and a surface with an auxilary
buffer without having a texture cache invalidate and command stream
From: Kevin Rogovin
If ASTC5x5 textures are present, resolve all textures that the sampler
accesses so that auxilary buffer is unneeded when the astc5x5 workaround
is needed and also program the sampler state to not use the auxilary
buffer as well.
Signed-off-by: Kevin Rogovin
---
src/mesa/dri
From: Thierry Reding
Add a new macro that can be used to extract the tiling mode from a
tile_mode value. This is will be used to determine the number of GOBs
used in block linear mode.
Acked-by: Emil Velikov
Tested-by: Andre Heider
Signed-off-by: Thierry Reding
---
src/gallium/drivers/nouvea
From: Thierry Reding
The existing format modifier definitions were merged prematurely, and
recent work has unveiled that the definitions are suboptimal in several
ways:
- The format specifiers, except for one, are not Tegra specific, but
the names don't reflect that.
- The number space i
From: Thierry Reding
Avoid a compiler warnings when the val parameter is an expression.
This is based on commit 5843f4e02fbe86a59981e35adc6cabebee46fdc0 from
Linux v4.16-rc1.
Acked-by: Emil Velikov
Tested-by: Andre Heider
Signed-off-by: Thierry Reding
---
include/drm-uapi/drm_fourcc.h | 2 +
From: Thierry Reding
This adds support for framebuffer modifiers to Nouveau. This will be
used by the Tegra driver to share metadata about the format of buffers
(such as the tiling mode or compression).
Changes in v2:
- remove unused parameters to nouveau_buffer_create()
- move format modifier q
From: Thierry Reding
This series of patches implements initial support for Tegra. The first
two patches import DRM UAPI from v4.16-rc1 that provides framebuffer
modifiers that can be used to specify buffers shared between Nouveau
and the Tegra DRM driver.
Patches 3 and 4 add support for framebuf
Tegra K1 and later use a GPU that can be driven by the Nouveau driver.
But the GPU is a pure render node and has no display engine, hence the
scanout needs to happen on the Tegra display hardware. The GPU and the
display engine each have a separate DRM device node exposed by the
kernel.
To make th
From: Thierry Reding
This allows the driver to be built on a make distcheck and makes sure
that it properly builds when a distribution tarball is made.
Suggested-by: Emil Velikov
Signed-off-by: Thierry Reding
---
Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
On 5 March 2018 at 19:08, Ian Romanick wrote:
> On 03/05/2018 10:48 AM, Emil Velikov wrote:
>> Hi all,
>>
>> It seems like these two extensions were never implemented or advertised.
>> Be that in:
>> - glx/dri
>> - glx/apple
>> - classic xlib-glx
>> - gallium xlib-glx
>>
>> Yet, the entry poin
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 9 ++---
src/amd/common/ac_shader_info.c | 12
src/amd/common/ac_shader_info.h | 2 ++
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_shader_info.c | 4
src/amd/common/ac_shader_info.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c
index fad4245986..c495879280 100644
--- a/src/amd/common/ac_shader_i
This adds a new level of gathering ("post-analysis") because
we have to bump the number of interp when the layer is needed.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 1 -
src/amd/common/ac_nir_to_llvm.h | 1 -
src/amd/common/ac_shader_info.c | 35
This allows us to remove one nir_foreach_variable loop.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 16 ++--
src/amd/common/ac_shader_info.c | 11 ---
src/amd/common/ac_shader_info.h | 2 ++
3 files changed, 12 insertions(+), 17 deletions(-)
diff --
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_shader_info.c | 30 ++
src/amd/common/ac_shader_info.h | 1 +
2 files changed, 31 insertions(+)
diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c
index c495879280..55b87cb96a 100644
---
RadeonSI does something similar, the VGPRs decrease is a win
but not sure if we really want to implement that.
Polaris10:
Totals from affected shaders:
SGPRS: 116376 -> 116768 (0.34 %)
VGPRS: 76556 -> 74868 (-2.20 %)
Spilled SGPRs: 10347 -> 10466 (1.15 %)
Code Size: 072 -> 5569024 (0.25 %) byt
This changes how we index flat_shaded_mask for generic varyings,
now it's based on location and not on ps_offset.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 2 --
src/amd/common/ac_nir_to_llvm.h | 1 -
src/amd/common/ac_shader_info.c | 5 +
src/amd/common/ac_shader_
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 9 +
src/amd/common/ac_nir_to_llvm.h | 1 -
src/amd/common/ac_shader_info.c | 5 +
src/amd/common/ac_shader_info.h | 2 ++
src/amd/vulkan/radv_pipeline.c | 4 ++--
5 files changed, 10 insertions(+), 11 deletions(-)
Using the input_interp_{mode,loc} arrays which are filled
in ac_shader_info.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_
On 5 March 2018 at 21:05, Brian Paul wrote:
>
> I'm fine with removing them too. If someone really complains, they can
> always be restored.
>
Seriously doubt it'll happen, yet I fully agree.
Small correction: only the Xlib based libGLs expose the API. I'll add
a note in the release notes, just
This pass moves load UBO operations just before their first use,
loosely based on nir_opt_move_comparisons.
Signed-off-by: Samuel Pitoiset
---
src/compiler/Makefile.sources| 1 +
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir.h | 2 +
src
Polaris10:
Totals from affected shaders:
SGPRS: 106656 -> 105952 (-0.66 %)
VGPRS: 73464 -> 73400 (-0.09 %)
Spilled SGPRs: 7121 -> 6861 (-3.65 %)
Code Size: 4157792 -> 4158716 (0.02 %) bytes
Max Waves: 9316 -> 9330 (0.15 %)
Vega10:
Totals from affected shaders:
SGPRS: 106720 -> 106032 (-0.64 %)
VGP
v2:
* Mention extension gap at gl_API.xml (Emil Velikov)
* Bail with INVALID_ENUM if extension not available on getStringi (Emil
Velikov)
* Use EXTRA_EXT macro when defining the extension at
get.c/get_hash_params.py (Emil Velikov)
* Rename source files (spirvextensions.[ch] -> spirv_ex
So now, during spirv_to_nir, it uses the capability instead of the
extension. Note that we are really doing here is treating
SPV_AMD_gcn_shader as other supported extensions. SPV_AMD_gcn_shader
is not the first SPV extension supported. For example, the capability
draw_parameters infers if the exten
Hi,
This series is the latest version of the support for
ARB_spirv_extensions on i965. The patches are basically the same that
v4 series we sent some time ago. This is rebased against master and
updated due the changes for the support of SPV_AMD_gcn_shader (sorry
for missing that one). So it inclu
Ideally this should be generated somehow. One option would be gather
all the extension dependencies listed on the core grammar, but there
would be the possibility of not including some of the extensions.
Note that spirv-tools is doing it just slightly better, as it has a
hardcoded list of extensio
Add a struct to maintain which SPIR-V extensions are supported, and an
utility method to initialize it based on
nir_spirv_supported_capabilities.
v2:
* Fixing code style (Ian Romanick)
* Adding a prefix (spirv) to fill_supported_spirv_extensions (Ian Romanick)
v3: rebase update (nir_spirv_sup
We can use it to get real values for ARB_spirv_extensions methods.
v2: Rebase update after changes on previous patches.
---
src/mesa/main/mtypes.h | 3 +++
src/mesa/main/spirv_extensions.c | 20 +++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/mes
v2: Rebase update after changes on previous patches.
---
src/mesa/drivers/dri/i965/brw_context.c | 10 +-
src/mesa/main/context.c | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw
first series here:
https://lists.freedesktop.org/archives/mesa-dev/2018-February/187275.html
change summery since v1:
* removed 64 bit shift patch
* reworked new intrinsics
* fixed some int8/uint8 issues
* add handling for CL types
* add support for lowering loading kernel args in nir_lower_i
From: Rob Clark
Otherwise nir_validate may complain about 8 bit floats, which do not exist.
Signed-off-by: Karol Herbst
---
src/compiler/spirv/spirv_to_nir.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to
OpenCL kernels have raw pointers to global memory, so we need
instructions to load/store in order to dereference these pointers.
In some ways similar to other load/store intrinsics, but rather
than taking an offset as a src argument, they take a raw pointer
value (which can be 32b or 64b depending
Signed-off-by: Karol Herbst
---
src/compiler/spirv/spirv_to_nir.c | 3 +++
src/compiler/spirv/vtn_private.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 48ade2c1ca..c5c4da853e 100644
--- a/src/compiler/spirv/s
From: Rob Clark
This assert is not valid for OpenCL kernels.
TODO can we somehow conditionally assert based on glsl vs cl??
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/nir/nir.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler
OpenCL kernels also have int8/uint8.
v2: remove changes in nir_search as Jason posted a patch for that
Reviewed-by: Jason Ekstrand
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/builtin_type_macros.h | 10
src/compiler/glsl/ast_to_hir.cpp
From: Rob Clark
Unlike glsl/vk compute shaders, this isn't a builtin constant.
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/spirv/vtn_variables.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compil
From: Rob Clark
These are just hints so we can ignore them.
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/spirv/spirv_to_nir.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index c5c4da853
From: Rob Clark
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/spirv/spirv_to_nir.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 6c4d28cddc..2e74e634eb 100644
--- a/s
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/nir/nir_lower_system_values.c | 8
src/compiler/shader_enums.c| 1 +
src/compiler/shader_enums.h| 2 ++
src/compiler/spirv/vtn_variables.c | 4
4 files changed, 15 insertio
From: Rob Clark
An attempt to add physical pointer support to vtn. I'm not totally
happy about the handling of logical pointers vs physical pointers.
So this is really more of an RFS (request for suggestions)
v2: treat vec3 types as vec4 when dereferencing
Signed-off-by: Karol Herbst
---
src
From: Rob Clark
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/spirv/vtn_alu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index d0c9e31693..9397240912 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src
We need this for OpenCL kernels because we have to apply C rules for alignment
and padding inside structs and for this we also have to know if a struct is
packed or not.
Signed-off-by: Karol Herbst
---
src/compiler/glsl_types.cpp | 17 +++--
src/compiler/glsl_types.h |
OpenCL kernels have parameters (see pipe_grid_info::input), and so we
need a way to access them.
The offset source is the offset of the parameter to load in the kernel input
buffer.
v2: improve commit message
remove BASE
split lower_io changes into separate commit
Signed-off-by: Karol He
Signed-off-by: Karol Herbst
---
src/compiler/glsl_types.cpp | 48 +
src/compiler/glsl_types.h | 10 ++
src/compiler/nir_types.cpp | 12
src/compiler/nir_types.h| 4
4 files changed, 74 insertions(+)
diff --git a/src/co
From: Rob Clark
If local_size is not known at compile time, which is the case with
clover, use the load_local_group_size intrinsic instead.
Signed-off-by: Karol Herbst
---
src/compiler/nir/nir_lower_system_values.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
Signed-off-by: Karol Herbst
---
src/compiler/glsl_types.h | 34 ++
src/compiler/nir_types.h | 30 +-
2 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index 34d03505ae
From: Rob Clark
I think a new intrinsic is the easiest way to do this. We can lower
this to a sequence of load/stores after vtn.
Signed-off-by: Rob Clark
Signed-off-by: Karol Herbst
---
src/compiler/nir/nir_intrinsics.h | 2 ++
src/compiler/spirv/vtn_variables.c | 17 -
2 f
For OpenCL kernels we have an input buffer where most of the parameters are
stored. For this we have to keep track of alignment and padding rules to
correctly identify the offset of each parameter inside that buffer.
For this we can just rely on the new cl_size and cl_alignment glsl_type
functions
We want to reuse it later on.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +
src/mesa/drivers/dri/i965/brw_performance_query.c | 146 +++---
2 files changed, 73 insertions(+), 76 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
We already have the same function in brw_queryobj.c
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/
This register contains the frequency of the GT, it's one of the value
GPA would like to have as part of their queries.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_defines.h | 10 +
src/mesa/drivers/dri/i965/brw_performance_query.c | 45 +++
Hi all,
One of the tool that Intel provides as part of a suite called GPA [1]
is a frame analyzer. This provides a way to look at per draw call or
frame workloads on the GPU through the OA hardware.
This tool relies on another library called MDAPI which requires a
somewhat specific format of data
The combinaison of GPA/MDAPI components expects a particular name &
layout for their pipeline statistics query.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 1 +
.../drivers/dri/i965/brw_performance_query_mdapi.c | 60 ++
.../driv
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 37 +++
src/mesa/drivers/dri/i965/brw_performance_query.h | 12
2 files changed, 49 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drive
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