Further info on this:
The original patch in Debian is at
https://sources.debian.org/src/mesa/18.1.2-1/debian/patches/07_gallium-fix-build-failure-on-powerpcspe.diff/
(URL will change based on version of Mesa in Debian - URL is current when I
sent this email).
PowerPCSPE port page in Debian which
PowerPC variants with the Signal Processing Engine do not support
Altivec instructions, as the SPE instruction set uses the same
instruction codes as the Altivec set available in most PowerPC
cores. Note that this is not related to the "Synergistic Processing
Element" units on IBM Cell microprocess
HI Marek,
Thank you, could you merge commits?
I don't have commit rights.
On Sat, Jun 30, 2018 at 12:29 AM Marek Olšák wrote:
> For the series:
>
> Reviewed-by: Marek Olšák
>
> Marek
>
> On Tue, Jun 26, 2018 at 4:30 PM, Denis Pauk wrote:
> > v2: none
> > v3: none
> >
> > Signed-off-by: Deni
On Sat, Jun 30, 2018 at 10:56 PM, Karol Herbst wrote:
> On Mon, Jun 11, 2018 at 5:10 PM, Marek Olšák wrote:
>> The series is OK with me, even though radeonsi can't support the new
>> opcodes.
>>
>
> How would you handle the case when a local variable might get a
> bindless or a non bindless sampl
On Mon, Jun 11, 2018 at 5:10 PM, Marek Olšák wrote:
> The series is OK with me, even though radeonsi can't support the new
> opcodes.
>
How would you handle the case when a local variable might get a
bindless or a non bindless sampler value assigned? Meaning, how can a
compliant implementation of
On Sat, Jun 30, 2018 at 4:05 PM, Karol Herbst wrote:
> On Sat, Jun 30, 2018 at 9:30 PM, Ilia Mirkin wrote:
>> Tes too, right? Also does the logic that forces recompiles work ok? I seem
>> to recall it was tied to vs.
>>
>
> well, I didn't want to touch stuff where we don't have a piglit test
> ye
On Sat, Jun 30, 2018 at 9:30 PM, Ilia Mirkin wrote:
> Tes too, right? Also does the logic that forces recompiles work ok? I seem
> to recall it was tied to vs.
>
well, I didn't want to touch stuff where we don't have a piglit test
yet, so everything else is untested. And as we don't start to expo
Tes too, right? Also does the logic that forces recompiles work ok? I seem
to recall it was tied to vs.
On Sat, Jun 30, 2018, 10:18 Karol Herbst wrote:
> this will be needed for compatibility profiles
>
> Signed-off-by: Karol Herbst
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi
Fix build error after llvm-7.0svn r336028 ("[instsimplify] Move the
instsimplify pass to use more obvious file names and diretory.").
rasterizer/jitter/blend_jit.cpp:873:20: error: use of undeclared identifier
'createInstructionSimplifierPass'
passes.add(createInstructionSimplifierPass())
this will be needed for compatibility profiles
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouvea
it turned out that the failures with GATHER*O were the result of a faulty
optimization done by sb. So for consistensy I'll also add the offset for
GATHER4_O and GATHER4_C_O in the SET_TEXTURE_OFFSET call which alleviates the
problems with sb.
Apart from that I've just fixed some comments followin
From: Gert Wollny
The evaluation of the array layer index is "floor(z+0.5)", and the default
rounding mode doesn't correctly evaluate this. Therefore, set the rounding
mode to "trunc" and and z-filter mode to "point".
For other textures make sure the the default rounding mode and z-filter are
use
From: Gert Wollny
For texture array lookup the slice index is evaluated according to
idx = floor(z + 0.5)
This patch implements the first part by adding 0.5 to the according
texture coordinate when appropriate.
Fixes multi-sample tests out of:
dEQP-GLES3.functional.texture.shadow.2d_array.*
Reviewed-by: Timothy Arceri
On 30/06/18 00:29, Alejandro Piñeiro wrote:
From: Antia Puentes
This will perform the CS shared lowering. See 8761a04d0d93
---
src/mesa/main/glspirv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index c58
Reviewed-by: Timothy Arceri
On 30/06/18 00:29, Alejandro Piñeiro wrote:
From: Neil Roberts
---
src/mesa/drivers/dri/i965/brw_link.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 8bc97fa4f3e..10
Reviewed-by: Timothy Arceri
On 30/06/18 00:29, Alejandro Piñeiro wrote:
That is the same gen requirement for ARB_shader_atomic_counters.
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers
On 30/06/18 00:29, Alejandro Piñeiro wrote:
From: Antia Puentes
From the SPIR-V specification, OpAtomicIDecrement:
"The instruction's result is the Original Value."
However, we were implementing it, for uniform atomic counters, as a
pre-decrement operation.
Renamed the former nir intrinsic
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