Am So., 21. Okt. 2018 um 20:37 Uhr schrieb Alyssa Rosenzweig
:
>
> On scalar ISAs, nir_lower_io_to_scalar_early enables significant
> optimizations. However, on vector ISAs, it is counterproductive and
> impedes optimal codegen. This patch only calls
> nir_lower_io_to_scalar_early for scalar ISAs.
STATE_BASE_ADDRESS only modifies various bases if the "modify" bit is
set. Otherwise, we want to keep the existing base address.
Iris uses this for updating Surface State Base Address while leaving the
others as-is.
---
src/intel/common/gen_batch_decoder.c | 24 +---
1 file c
> I'm also working on a pass to recombine io to vectors which should
> hopefully allow you to have the best of both worlds in future.
Ooo, exciting. Thank you! :)
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https://bugs.freedesktop.org/show_bug.cgi?id=108508
--- Comment #2 from Timothy Arceri ---
Thanks for testing, although its kind of strange to use bugzilla to report
issues in patches that have not landed yet. You may wish to report this type of
thing on the mailing list in future.
Anyway my gue
On 21/10/18 4:00 am, Eric Engestrom wrote:
Signed-off-by: Eric Engestrom
---
src/amd/common/ac_nir_to_llvm.c| 1 -
src/broadcom/compiler/vir_live_variables.c | 2 --
src/broadcom/compiler/vir_lower_uniforms.c | 1 -
src/compiler/glsl/ast_to_hir.cpp
Reviewed-by: Timothy Arceri
I'm also working on a pass to recombine io to vectors which should
hopefully allow you to have the best of both worlds in future.
On 22/10/18 5:29 am, Alyssa Rosenzweig wrote:
On scalar ISAs, nir_lower_io_to_scalar_early enables significant
optimizations. However,
https://bugs.freedesktop.org/show_bug.cgi?id=108508
--- Comment #1 from Ahmed Elsayed ---
Created attachment 142124
--> https://bugs.freedesktop.org/attachment.cgi?id=142124&action=edit
Mafia 3
The faces looks weird and the games is unplayable.
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https://bugs.freedesktop.org/show_bug.cgi?id=108508
Bug ID: 108508
Summary: Graphic glitches with stream output support on OLAND
AMD GPU GCN 1.0
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux
1. When using Meson 0.48.x both -Dc_args -Dcpp_args and -Db_vscrt methods of
selecting the CRT are ineffective on changing the CRT from MD to MT resulting
in build failure if LLVM is built with MT CRT. This issue persists from last
time I tested this WIP branch. However if MT built LLVM is indee
Reviewed-by: Bas Nieuwenhuizen
for patch 1-4. (Also, I don't see patch 7?)
On Sat, Oct 20, 2018 at 7:56 PM Jason Ekstrand wrote:
>
> ---
> src/compiler/nir/nir.c | 92 ++
> src/compiler/nir/nir.h | 16
> 2 files changed, 108 insertions(+)
>
> dif
On scalar ISAs, nir_lower_io_to_scalar_early enables significant
optimizations. However, on vector ISAs, it is counterproductive and
impedes optimal codegen. This patch only calls
nir_lower_io_to_scalar_early for scalar ISAs. It appears that at present
there are no upstreamed drivers using Gallium,
https://bugs.freedesktop.org/show_bug.cgi?id=107369
--- Comment #15 from Jan Vesely ---
(In reply to infinity0 from comment #14)
> Did you get a chance to analyze my dump?
>
> I filed a LLVM bug here https://bugs.llvm.org/show_bug.cgi?id=38979
>
> Didn't yet get a chance to test it with LLVM 7
TGSI has no I64MAD/U64MAD opcode.
Fixes: 278580729a5 ('st/glsl_to_tgsi: add support for 64-bit integers')
Signed-off-by: Rhys Perry
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_
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